阅读说明：本技术 一种阻抗调节电路和方法、偏置电路结构和放大器 (Impedance adjusting circuit and method, bias circuit structure and amplifier ) 是由 邓金亮 李平 于 2020-05-13 设计创作，主要内容包括：本发明实施例提供了一种阻抗调节电路和方法、偏置电路结构和放大器,所述阻抗调节电路与偏置电路的偏置电流输出端并联；所述偏置电路,用于向第一电路单元提供偏置电流；所述阻抗调节电路,用于调节所述第一电路单元的源阻抗。如此,可以通过阻抗调节电路实现对第一电路单元的源阻抗的调节,在阻抗调节电路位于放大器的情况下,有利于放大器的记忆效应。(The embodiment of the invention provides an impedance adjusting circuit, an impedance adjusting method, a bias circuit structure and an amplifier, wherein the impedance adjusting circuit is connected with a bias current output end of a bias circuit in parallel; the bias circuit is used for providing bias current for the first circuit unit; the impedance adjusting circuit is used for adjusting the source impedance of the first circuit unit. In this way, the adjustment of the source impedance of the first circuit unit can be achieved by the impedance adjusting circuit, which in the case of an amplifier is located in the impedance adjusting circuit, is advantageous for the memory effect of the amplifier.)

1. An impedance adjusting circuit is characterized in that the impedance adjusting circuit is connected with a bias current output end of a bias circuit in parallel; the bias circuit is used for providing bias current for the first circuit unit; the impedance adjusting circuit is used for adjusting the source impedance of the first circuit unit.

2. The impedance adjusting circuit of claim 1, comprising a first series branch formed by an inductor in series with a forward conducting diode.

3. The impedance adjustment circuit of claim 2, wherein the current of the diode is derived by current shunting of a current source.

4. The impedance adjustment circuit of claim 1, comprising a second series branch formed by a resistor, an inductor, and a forward conducting diode in series.

5. The impedance adjustment circuit of claim 4, wherein the current of the diode is derived by current splitting of an adjustable current source.

6. The impedance adjustment circuit of claim 4, wherein the resistor is an adjustable resistor.

7. The impedance adjustment circuit of claim 1, comprising a third series branch formed by a resistor, L C parallel branch, and a forward conducting diode in series.

8. The impedance adjustment circuit of claim 7, wherein the current of the diode is derived by current shunting of a current source.

9. The impedance adjustment circuit of claim 7, wherein the resistor is an adjustable resistor.

10. The impedance adjusting circuit of claim 7, wherein the L C parallel branch is a circuit with adjustable resonant frequency.

11. A bias circuit structure, comprising: a biasing circuit and an impedance adjusting circuit as claimed in any one of claims 1 to 10.

12. An amplifier comprising the bias circuit arrangement of claim 11 and a first circuit unit connected to a bias current output of the bias circuit, the first circuit unit being configured to perform signal amplification.

13. The impedance adjusting method is characterized by being applied to an impedance adjusting circuit, wherein the impedance adjusting circuit is connected with a bias current output end of a bias circuit in parallel;

the method comprises the following steps: adjusting a source impedance of a first circuit unit with the impedance adjustment circuit while the bias circuit provides a bias current to the first circuit unit.

Technical Field

The present invention relates to impedance adjusting technology, and in particular, to an impedance adjusting circuit and method, a bias circuit structure, and an amplifier.

Background

Disclosure of Invention

The embodiment of the invention provides a technical scheme for adjusting impedance.

In order to achieve the above purpose, the technical solution of the embodiment of the present invention is realized as follows:

the embodiment of the invention provides an impedance adjusting circuit, which is connected with a bias current output end of a bias circuit in parallel; the bias circuit is used for providing bias current for the first circuit unit; the impedance adjusting circuit is used for adjusting the source impedance of the first circuit unit.

An embodiment of the present invention further provides a bias circuit structure, where the bias circuit structure includes: a bias circuit and an impedance adjusting circuit as described in any of the above.

An embodiment of the present invention further provides an amplifier, including the bias circuit structure and the first circuit unit, where the first circuit unit is connected to a bias current output end of the bias circuit, and the first circuit unit is configured to amplify a signal.

The embodiment of the invention also provides an impedance adjusting method, which is applied to an impedance adjusting circuit, wherein the impedance adjusting circuit is connected with the bias current output end of the bias circuit in parallel;

the method comprises the following steps: adjusting a source impedance of a first circuit unit with the impedance adjustment circuit while the bias circuit provides a bias current to the first circuit unit.

According to the impedance adjusting circuit provided by the embodiment of the invention, the impedance adjusting circuit is connected with the bias current output end of the bias circuit in parallel; the bias circuit is used for providing bias current for the first circuit unit; the impedance adjusting circuit is used for adjusting the source impedance of the first circuit unit, so that the source impedance of the first circuit unit can be adjusted through the impedance adjusting circuit, and the memory effect of the amplifier can be improved under the condition that the impedance adjusting circuit is located in the amplifier.

Drawings

FIG. 1 is a diagram of the third order Intermodulation distortion (IM 3) of the upper and lower sidebands of a memory effect free system according to the related art;

FIG. 2 is a diagram of IM3 of the upper and lower sidebands of a memory effect system according to the related art;

FIG. 3 is a diagram illustrating upper and lower asymmetry of Adjacent Channel Power Ratio (ACPR) of upper and lower sidebands of a memory effect system according to the related art;

FIG. 4 is a schematic diagram of a bias circuit in the related art;

FIG. 5 is a schematic diagram of the connection of the impedance adjusting circuit, the bias circuit and the first circuit unit according to the embodiment of the present invention;

FIG. 6 is a first schematic diagram of the connection of the impedance adjusting circuit and the bias circuit in an embodiment of the present invention;

FIG. 7 is a second schematic diagram of the impedance adjusting circuit coupled to the bias circuit in an embodiment of the present invention;

FIG. 8 is a third schematic diagram of the impedance adjusting circuit coupled to the bias circuit in an embodiment of the present invention;

fig. 9 is a flowchart of an impedance adjusting method according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The embodiment of the invention discloses an impedance adjusting circuit and method, a bias circuit structure and an amplifier, which can improve the memory effect of a power amplifier applied to a wireless communication system, wherein the power amplifier is an important key device in wireless communication, and the requirement on the linearity of the power amplifier is higher and higher along with the development of long-term evolution (L ong TermEsolution, &lTtTtranslation = L' &gTtL &lTt/T &gTtTE) and 5G NR in the wireless communication.

FIG. 1 shows a related artA schematic diagram of the third order intermodulation distortion IM3 of the upper and lower sidebands of a system without memory effect is shown in FIG. 1, wherein the horizontal axis represents frequency and the vertical axis represents signal amplitude, and it can be seen that the frequencies are f₁And f₂In a system without memory effect, the two carrier signals are subjected to intermodulation due to nonlinear factors and are respectively at the frequency 2f₁-f₂And 2f₂-f₁Generating a symmetrical third order intermodulation distortion signal.

FIG. 2 is a schematic diagram of IM3 of the upper and lower sidebands of a memory effect system of the related art, as shown in FIG. 2, where the horizontal axis represents frequency and the vertical axis represents signal amplitude, and thus, the frequency is f₁And f₂In a system with memory effect, intermodulation occurs due to non-linear factors, and the intermodulation occurs at the frequency 2f₁-f₂And 2f₂-f₁An asymmetric third order intermodulation distortion signal is generated. Due to the asymmetry of the intermodulation distortion of the upper and lower sidebands, the upper and lower asymmetries of the ACPR can be caused, and the linearity characteristic of the power amplifier is deteriorated. Here, ACPR refers to the ratio of the average power of the adjacent frequency channels to the average power of the transmit frequency channel.

Fig. 3 is a schematic diagram showing upper and lower asymmetries of ACPR of upper and lower sidebands of a system in which a memory effect exists in the related art, as shown in fig. 3, in which the horizontal axis represents target output power and the vertical axis represents a value of ACPR, wherein a solid line represents ACPR of the upper sideband of the system and a dotted line represents ACPR of the lower sideband of the system, and it can be seen that ACPR of the upper and lower sidebands of the system do not coincide.

Fig. 4 is a schematic diagram of a bias circuit in the related art, as shown in fig. 4, where Iref is a current source, a forward-conducting first diode D1 and a second diode D2 are connected in series to form a diode series branch, and a branch formed by the diode series branch and a first capacitor C1 in parallel is connected between the current source Iref and a ground node; the base electrode of the triode T is connected with the common node of the first diode D1, the first capacitor C1 and the current source Iref, the collector electrode is connected with the voltage source Vbatt, and the emitter electrode is connected with one end of the first resistor R1; the first resistor R1 may be a DC ballast equivalent electrical bank; the current source Iref, the first diode D1, the second diode D2 and the capacitor C1 cooperate to provide a base clamping voltage of the transistor T, and the other end of the first resistor R1 provides a bias current Ibias for a first circuit unit (not shown in fig. 4), where the first circuit unit may be a circuit amplifying unit, and specifically, the circuit amplifying unit may be a power amplifier tube. As the baseband signal belongs to a low-frequency signal, for the baseband signal, the first capacitor C1 is equivalent to an open circuit, and when viewed from the first circuit unit to the bias current input end, the baseband signal passes through the first resistor R1 and is connected to the BE junction of the base and the emitter of the triode T, where the current value of the bias current Ibias is relatively small, and the impedance value of the BE junction is relatively large, for example, the impedance value may BE 100 ohm; after passing through the BE junction and then through the first diode D1 and the second diode D2, respectively, to ground, the path current of the first diode D1 and the second diode D2 is very small, the series resistance of the first diode D1 and the second diode D2 is very large, and it can BE seen that the source resistance of the first circuit unit in fig. 4 is equivalent to the sum of the series resistances of the first resistor R1, the BE junction of the transistor T, the first diode D1 and the second diode D2, and therefore, when the current value of the current source Iref corresponding to the Ibias value is fixed, the current value of the Ibias is fixed, the current value flowing through the BE junction of the triode T is also fixed, and the channel currents of the first diode D1 and the second diode D2 are also fixed, further, the sum of the resistance value of the first resistor R1, the resistance value of the BE junction of the transistor T, and the series resistance of the first diode D1 and the second diode D2 is fixed, and thus, the source resistance of the first circuit unit is not adjustable.

The following embodiments are proposed to solve the technical problem of non-adjustable input impedance.

Fig. 5 is a schematic diagram of the connection of the impedance adjusting circuit, the bias circuit and the first circuit unit in the embodiment of the present invention, as shown in fig. 5, the impedance adjusting circuit 501 is connected in parallel with the bias current output terminal of the bias circuit 502; the bias circuit 502 is configured to provide a bias current to the first circuit unit 503; the impedance adjusting circuit 501 is configured to adjust a source impedance of the first circuit unit 503.

Here, the bias circuit 502 may be the bias circuit shown in fig. 4, and specifically, the base of the transistor T is connected to a common node of the first diode D1, the first capacitor C1 and the current source Iref, so that the emitting junction of the transistor T is in a forward bias state; the triode T can be an NPN type triode, and the collector of the triode T is connected with a voltage source Vbatt, so that the collector junction of the triode can be in a reverse bias state. As an embodiment, the first circuit unit may be a circuit unit for implementing signal amplification, for example, the first circuit unit may be a power amplifier tube, and of course, the first circuit unit herein may be other units than the circuit unit for implementing signal amplification, and is not specifically limited herein.

It can be seen that, the impedance adjusting circuit is connected in parallel with the bias current output terminal of the bias circuit, the bias circuit is used for providing the bias current to the first circuit unit, and the impedance adjusting circuit is used for adjusting the input impedance of the first circuit unit, so that the source impedance of the first circuit unit can be adjusted by adjusting the impedance of the impedance adjusting circuit under the condition of ensuring that the bias current is not changed.

Optionally, the impedance adjusting circuit includes a first series branch formed by connecting an inductor and a forward conducting diode in series.

It can be understood that the inductor has frequency-selective characteristics, and specifically, the inductor is in a short-circuit state for baseband signals, but in a high-impedance state for high-frequency signals such as fundamental waves and harmonic waves. Meanwhile, the forward conducting diode has the characteristic of adjustable impedance, and the impedance of the diode can be adjusted by adjusting the current flowing through the diode. Therefore, the impedance of the diode can be adjusted by adjusting the current flowing through the diode on the first series branch, so that the impedance of the impedance adjusting circuit can be adjusted, and further, the source impedance of the first circuit unit can be adjusted by adjusting the impedance of the impedance adjusting circuit.

Fig. 6 is a first schematic diagram of the connection between the impedance adjusting circuit and the bias circuit according to the embodiment of the present invention, as shown in fig. 6, the impedance adjusting circuit 501 may include a first inductor L1 and a forward-conducting third diode D3, the first inductor L1 and the third diode D3 are connected in series to form a first series branch, the first inductor L1 is connected to an emitter of the transistor T, and a cathode of the third diode D3 is grounded, and the structure of the bias circuit in fig. 6 is the same as that of the bias circuit shown in fig. 4, and is not repeated here.

Since the first inductor L1 is in a short circuit state for baseband (low frequency) signals, and forms a high resistance for high frequency signals such as fundamental waves and harmonics, and the impedance of the third diode D3 can be adjusted by adjusting the current flowing through the third diode D3, that is, the source impedance of the first circuit unit can be adjusted without affecting the fundamental waves and harmonics impedance due to the frequency selection characteristic of the first inductor L1 and the impedance adjustable characteristic of the third diode D3, and the impedance of the third diode D3 can be reduced with the increase of the passing current, the source impedance of the first circuit unit can be adjusted in a large range, and the optimal source impedance of the first circuit unit can be obtained.

Specifically, as shown in fig. 6, based on the constant value of the bias current Ibias and the presence of the impedance adjusting circuit 501 formed by the first inductor L1 and the third diode D3 connected in series, the current flowing through the BE junction of the transistor T is increased, that is, the impedance value of the BE junction of the transistor T may BE decreased, for example, from the original 25ohm to 20ohm, but since the impedance values of the first diode D1 and the second diode D2 are relatively large, the sum of the impedance values of the first diode D1 and the second diode D2 may BE 500ohm, and therefore, the impedance value of the second impedance circuit is equivalent to decrease from 525ohm to 520ohm, and the change is relatively small, and further, the impedance value of the first impedance circuit is close to the impedance value of the third diode D3, and the impedance value of the third diode D3 may BE adjusted by adjusting the current value of the third diode D3, thereby achieving the adjustment of the source impedance of the first circuit unit 503.

Optionally, the current of the diode is derived by current splitting of an adjustable current source.

Specifically, the current source Iref may be an adjustable current source, and the magnitude of the current value of the third diode D3 in the impedance adjusting circuit 501 corresponds to the magnitude of the current value of the current source Iref, specifically, in the case that the bias current Ibias is not changed, the current value of the current source Iref is increased, and the current value of the third diode D3 is increased.

Optionally, the impedance adjusting circuit comprises a second series branch formed by a resistor, an inductor and a forward conducting diode in series.

Here, the resistance may be a resistance whose resistance value can be adjusted.

Fig. 7 is a second schematic diagram of the connection between the impedance adjusting circuit and the bias circuit in the embodiment of the present invention, as shown in fig. 7, the impedance adjusting circuit 501 may include a second resistor R2, a second inductor L2, and a forward-conducting fourth diode D4, the second resistor R2, the second inductor L2, and the fourth diode D4 are connected in series to form a second series branch, the second resistor R2 is connected to an emitter of the triode T, and a cathode of the fourth diode D4 is grounded, where the second resistor R2 may be an adjustable resistor, and the structure of the bias circuit in fig. 7 is the same as that of the bias circuit shown in fig. 4, and details are not repeated here.

The second inductor L is in a short-circuit state for baseband (low frequency) signals, and forms a high resistance for high frequency signals such as fundamental waves and harmonic waves, and the impedance of the fourth diode D4 can be adjusted by adjusting the current of the fourth diode D4, so that the impedance of the impedance adjusting circuit 501 can be adjusted, and the impedance of the impedance adjusting circuit 501 can also be adjusted by adjusting the resistance of the second resistor R2.

Specifically, as shown in fig. 7, based on the constant value of the bias current Ibias and the presence of the impedance adjusting circuit 501 formed by the second resistor R2, the second inductor L2 and the forward-conducting fourth diode D4 connected in series, the current flowing through the BE junction of the transistor T is increased, that is, the impedance value of the BE junction of the transistor T may BE decreased, for example, from 25ohm to 20ohm, but since the impedance values of the first diode D1 and the second diode D2 are relatively large, the sum of the impedance values of the first diode D1 and the second diode D2 may BE 500ohm, and thus, the impedance value of the second impedance circuit is equivalent to decrease from 525ohm to 520ohm, the variation is relatively small, and further, the impedance value of the first impedance circuit is close to the sum of the impedance values of the fourth diode D4 and the second resistor R2, and the impedance value of the fourth diode D4 may BE adjusted by adjusting the current value of the fourth diode D4, and/or the impedance value of the first resistor R2 of the first impedance adjusting circuit may BE realized by adjusting the resistance of the first resistor R2.

Optionally, the current of the diode is derived by current splitting of an adjustable current source.

Specifically, the current source Iref may be an adjustable current source, and the magnitude of the current value of the fourth diode D4 in the impedance adjusting circuit 501 corresponds to the magnitude of the current value of the current source Iref, specifically, in the case that the bias current Ibias is not changed, the current value of the current source Iref is increased, and the current value of the fourth diode D4 is increased.

Optionally, the impedance adjusting circuit comprises a third series branch formed by a resistor, an L C parallel branch and a forward conducting diode in series.

Here, the resistance may be a resistance whose resistance value can be adjusted.

Here, the L C parallel branch is a circuit with adjustable resonant frequency.

Fig. 8 is a third schematic diagram of the connection between the impedance adjusting circuit and the bias circuit in the embodiment of the present invention, as shown in fig. 8, the impedance adjusting circuit 501 may include a third resistor R3, a third inductor L3, a second capacitor C2, and a forward-conducting fifth diode D5, the third resistor R3 is connected to an emitter of the triode T, a L3C 2 parallel branch formed by the third inductor L3 and the second capacitor C2 in parallel is connected between the third resistor R3 and an anode of the fifth diode D5, and a cathode of the fifth diode D5 is grounded, where the third resistor R3 may be an adjustable resistor, and the structure of the bias circuit in fig. 8 is the same as that of the bias circuit shown in fig. 4, and is not described herein.

Further, based on the impedance adjustable characteristic of the fifth diode D5, the impedance value of the third resistor R3 and the resonance characteristic of the L C2 parallel branch, the impedance of the whole impedance adjusting circuit 501 at baseband, fundamental wave and harmonic frequency can be adjusted by adjusting the current of the fifth diode D5 and the impedance value of the third resistor R3 on the parallel branch and the resonance frequency of the L C2 parallel branch.

Specifically, as shown in fig. 8, based on the constant value of the bias current Ibias and the impedance adjusting circuit 501 formed by the parallel branch of the third resistors R3, L C2 and the series connection of the fifth diode D5, the current flowing through the BE junction of the transistor T in the second impedance circuit is increased, that is, the impedance value of the BE junction of the transistor T may BE decreased, for example, the original 25ohm may BE decreased to 20ohm, but since the impedance values of the first diode D1 and the second diode D2 in the second impedance are relatively large, the sum of the impedance values of the first diode D1 and the second diode D2 may BE 500ohm, and thus, the impedance value of the second impedance circuit is decreased from 525ohm to 520ohm, and the change is relatively small, and further, the impedance value of the first impedance circuit is close to the impedance value of the fifth diode D5, the impedance of the third resistor R3 and the impedance value of the parallel circuit resonant impedance of the L C2, and the impedance value of the first impedance circuit may BE adjusted by at least one of the impedance adjusting unit 2, the frequency of the parallel connection of the first diode D6328, the first impedance adjusting circuit, the third resistor R73725, the third resistor R633, and the impedance adjusting unit 2.

Optionally, the current of the diode is derived by current splitting of an adjustable current source.

Specifically, the current source Iref may be an adjustable current source, and the magnitude of the current value of the fifth diode D5 in the impedance adjusting circuit 501 corresponds to the magnitude of the current value of the current source Iref, specifically, in the case that the bias current Ibias is not changed, the current value of the current source Iref is increased, and the current value of the fifth diode D5 is increased.

The embodiment of the present invention further provides a bias circuit structure, where the bias circuit structure includes: a bias circuit 502 and an impedance adjusting circuit 501 as described above.

The embodiment of the invention also provides an amplifier, which comprises the bias circuit structure and the first circuit unit, wherein the circuit amplification unit is connected with the bias current output end of the bias circuit, and the first circuit unit is used for amplifying signals.

The embodiment of the invention also provides an impedance adjusting method, which is applied to an impedance adjusting circuit, wherein the impedance adjusting circuit is connected with the bias current output end of the bias circuit in parallel; fig. 9 is a flowchart of an impedance adjusting method according to an embodiment of the disclosure, and as shown in fig. 9, the flowchart may include:

step 901: adjusting a source impedance of a first circuit unit with the impedance adjustment circuit while the bias circuit provides a bias current to the first circuit unit.

The specific implementation of the impedance adjusting method has been described in the foregoing embodiments, and is not described herein again.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.