阅读说明：本技术 一种高分辨率可调增益的低噪声开关电容放大器及其设计方法 (High-resolution gain-adjustable low-noise switched capacitor amplifier and design method thereof ) 是由 王磊 古振刚 于 2020-04-13 设计创作，主要内容包括：本发明公开了一种高分辨率可调增益的低噪声开关电容放大器及其设计方法,该开关电容放大器包括信号输入电路、放大电路、反馈电路,算法调制电路和delta-sigma编码器,所述放大电路的输入通过一对输入电容采样输入信号电压,然后再将采样的电压通过运算放大器运放积分,放大电路的反馈是通过一对反馈电容采样输出电压,然后再将采样的电压通过运算放大器运放积分,所述delta-sigma编码器通过编码控制两对CMOS开关管的通断进而调制所述输入电容或反馈电容。本发明中PGA增益的调整由编码完成而输入电容和输出电容的容值不随增益的调节而变化,折算到输入的开关电容噪声就不会改变,相比常规PGA改变电容容值的调节方式信噪比更好控制。(The invention discloses a high-resolution gain-adjustable low-noise switched capacitor amplifier and a design method thereof, the switched capacitor amplifier comprises a signal input circuit, an amplifying circuit, a feedback circuit, an algorithm modulation circuit and a delta-sigma encoder, wherein the input of the amplifying circuit samples the voltage of an input signal through a pair of input capacitors, then the sampled voltage is subjected to operational amplifier integration, the feedback of the amplifying circuit samples the output voltage through a pair of feedback capacitors, then the sampled voltage is subjected to operational amplifier integration, and the delta-sigma encoder controls the on-off of two pairs of CMOS switching tubes through encoding so as to modulate the input capacitor or the feedback capacitor. The PGA gain is adjusted by coding, the capacitance values of the input capacitor and the output capacitor are not changed along with the adjustment of the gain, the noise of the input switched capacitor is not changed after conversion, and the signal-to-noise ratio is better controlled compared with the conventional PGA adjusting mode of changing the capacitance value.)

1. The high-resolution gain-adjustable low-noise switched capacitor amplifier comprises a switched capacitor signal input circuit, an amplifying circuit and a feedback circuit, and is characterized by further comprising an algorithm modulation circuit and a delta-sigma encoder, wherein the algorithm modulation circuit comprises two pairs of CMOS switching tubes, the input of the amplifying circuit samples input signal voltage through a pair of input capacitors, then the sampled voltage is subjected to operational amplifier integration, the feedback of the amplifying circuit samples output voltage through a pair of feedback capacitors, then the sampled voltage is subjected to operational amplifier integration, and the delta-sigma encoder controls the on-off of the two pairs of CMOS switching tubes through encoding so as to modulate the input capacitors or the feedback capacitors.

2. The high resolution adjustable gain low noise switched capacitor amplifier according to claim 1, wherein the input capacitor comprises a first input capacitor (201) and a second input capacitor (202), the feedback capacitor comprises a first feedback capacitor (203) and a second feedback capacitor (204), and the two pairs of CMOS switch transistors are a first CMOS switch transistor (210), a second CMOS switch transistor (211), a third CMOS switch transistor (212) and a fourth CMOS switch transistor (213); one end of the first input capacitor (201) is connected with a source end, the other end of the first input capacitor is respectively connected with one end of a first CMOS switch tube (210) and one end of a second CMOS switch tube (211), one end of the second input capacitor (202) is connected with the source end, and the other end of the second input capacitor is respectively connected with one end of a third CMOS switch tube (212) and one end of a fourth CMOS switch tube (213); the other ends of the first CMOS switch tube (210) and the third CMOS switch tube (212) are both connected with one end of a first feedback capacitor (203), the other ends of the first CMOS switch tube and the third CMOS switch tube are grounded after being connected with a ninth CMOS switch tube (107) and are connected with the inverting input end of an operational amplifier (150) through a fifteenth CMOS switch tube (113), the other end of the first feedback capacitor (203) is grounded after being connected with an eleventh CMOS switch tube (109), on the other hand, the other end of the first feedback capacitor is respectively connected with one end of a first integrating capacitor (140) and the non-inverting output end of the operational amplifier (150) through a thirteenth CMOS switch tube (111), and the other end of the first integrating capacitor (140) is connected with the inverting input end of the operational amplifier (150); the other ends of the second CMOS switch tube (211) and the fourth CMOS switch tube (213) are both connected with one end of a second feedback capacitor (204), the other ends of the second CMOS switch tube and the fourth CMOS switch tube are grounded after being connected with a tenth CMOS switch tube (108) and are connected with the non-inverting input end of the operational amplifier (150) through a sixteenth CMOS switch tube (114), the other end of the second feedback capacitor (204) is grounded after being connected with a twelfth CMOS switch tube (110), on the other hand, the other end of the second feedback capacitor is respectively connected with one end of a second integrating capacitor (141) and the inverting output end of the operational amplifier (150) through a fourteenth CMOS switch tube (112), and the other end of the second integrating capacitor (141) is connected with the non-inverting input end of the operational amplifier (150).

3. The high resolution adjustable gain low noise switched capacitor amplifier according to claim 1, wherein the input capacitor comprises a first input capacitor (201) and a second input capacitor (202), the feedback capacitor comprises a first feedback capacitor (203) and a second feedback capacitor (204), and the two pairs of CMOS switch transistors are a first CMOS switch transistor (210), a second CMOS switch transistor (211), a third CMOS switch transistor (212) and a fourth CMOS switch transistor (213); one end of the first input capacitor (201) is connected with a source end, the other end of the first input capacitor is respectively connected with one end of a first CMOS switch tube (210) and one end of a second CMOS switch tube (211), the first input capacitor is further connected with the ground after being connected with a ninth CMOS switch tube (107) and is connected with the inverting input end of the operational amplifier (150) through a fifteenth CMOS switch tube (113), one end of the second input capacitor (202) is connected with the source end, the other end of the second input capacitor is respectively connected with one end of a third CMOS switch tube (212) and one end of a fourth CMOS switch tube (213), the first input capacitor is further connected with the ground after being connected with a tenth CMOS switch tube (108) and is connected with the non-inverting input end of the operational amplifier (150) through a sixteenth CMOS switch; the other ends of the first CMOS switch tube (210) and the third CMOS switch tube (212) are both connected with one end of a first feedback capacitor (203), the other end of the first feedback capacitor (203) is grounded after being connected with an eleventh CMOS switch tube (109) on one hand, and is also respectively connected with one end of a first integrating capacitor (140) and the in-phase output end of an operational amplifier (150) through a thirteenth CMOS switch tube (111) on the other hand, and the other end of the first integrating capacitor (140) is connected with the anti-phase input end of the operational amplifier (150); the other ends of the second CMOS switch tube (211) and the fourth CMOS switch tube (213) are both connected with one end of a second feedback capacitor (204), the other end of the second feedback capacitor (204) is grounded after being connected with a twelfth CMOS switch tube (110), on the other hand, the other end of the second feedback capacitor is also respectively connected with one end of a second integrating capacitor (141) and the inverted output end of the operational amplifier (150) through a fourteenth CMOS switch tube (112), and the other end of the second integrating capacitor (141) is connected with the non-inverting input end of the operational amplifier (150).

4. The high-resolution gain-adjustable low-noise switched capacitor amplifier according to claim 2 or 3, wherein the source terminal comprises a differential signal source (101), a common-mode voltage (102), a fifth CMOS switch tube (103), a sixth CMOS switch tube (104), a seventh CMOS switch tube (105), and an eighth CMOS switch tube (106), the differential signal source (101) is connected to the common-mode voltage (102) and is also connected to one end of the fifth CMOS switch tube (103) and one end of the sixth CMOS switch tube (104), respectively, the other end of the fifth CMOS switch tube (103) is connected to the first input capacitor (201) on the one hand, and is connected to the ground by connecting the seventh CMOS switch tube (105) on the other hand, and the other end of the sixth CMOS switch tube (104) is connected to the second input capacitor (202) on the one hand, and is connected to the ground by connecting the eighth CMOS switch tube (106) on the other hand.

5. A design method of a low-noise switched capacitor amplifier with high resolution and adjustable gain is characterized in that a set gain value is modulated by a delta-sigma algorithm and then a code which is composed of 1 and 0 and is synchronous with a switching clock is output, and the code controls connection and disconnection of an input capacitor or a feedback capacitor, wherein: "1" means closed, "0" means open, and a code "1" is designed in the circuit to integrate the input signal or feedback signal in the forward direction, and a code "0" is designed to integrate the input signal or feedback signal in the reverse direction.

6. The design method of claim 5, wherein the input capacitance of the PGA is connected to the integrating amplifier through two pairs of switches, one pair of switches is a forward integrating path to increase the integrated output voltage, the other pair is a reverse integrating path to decrease the integrated output voltage, and the binary '1' and '0' coded outputs of the digital delta-sigma coder are connected to the forward and reverse integrating paths of the integrating amplifier, respectively.

7. The design method as claimed in claim 5, wherein the clock signals of the two phases are mutually inverse, and the clock levels of the two phases do not have an overlap time of "1" at the same time, which is used to provide the switch control of HRPGA switch capacitor with each clock cycle.

8. The design method of claim 5, wherein the input is a multi-bit binary digit vector for setting gain, the number of bits defines the resolution for adjusting gain, the vector is processed by the modulation function and then output as a pair of biphase non-overlapping 1-bit binary digital signals, the quantization noise in the low frequency band is transferred to the high frequency band by the delta-sigma modulation algorithm, and the order of the modulator is increased according to the requirement for increasing the gain resolution.

9. The design method of claim 6, wherein an analog low pass filter is placed after the HRPGA to filter the high frequency delta-sigma coded modulation and introduce quantization noise, and the bandwidth and order of the low pass filter needs to match the bandwidth and order of the delta-sigma modulator to achieve a sufficient amount of attenuation of the quantization noise.

10. The design method of claim 9, wherein the order of the filter is greater than the order of the delta-sigma modulation algorithm.

Technical Field

The invention belongs to the field of analog integrated circuits, relates to acquisition, amplification and analog-to-digital conversion (ADC) of signals by an analog integrated circuit, in particular to a low-noise switched capacitor amplifier with high resolution and adjustable gain, which is suitable for acquiring and conditioning signals of a high-sensitivity signal link system, especially a weak signal sensor, and finely adjusting gain in an automatic control system; and the system also has wide applicability in the fields of automobiles, household appliances, industrial automation, robots, Internet of things and military industry.

Background

A variable gain switched capacitor signal amplifier (PGA) is often used in a sensor signal detection, analog-to-digital signal conversion (ADC) and digital-to-analog (DAC) conversion circuit. However, the amplification factor of the currently-used PGA circuit is realized by the ratio of the input capacitor to the feedback capacitor. When the very subdivided amplification times are adjusted, series-parallel combination of a plurality of input capacitors or feedback capacitors is commonly used for completing the adjustment, or combination of subdivided gains is realized by a method of cascading two-stage switch capacitor amplifiers. However, the above methods have great limitations, mainly including: (1) due to the limitation of the size of the internal capacitor of the chip, the series-parallel combination of a plurality of capacitors increases the accumulation of matching errors among the capacitors, so that the PGA gain is difficult to be accurately subdivided and graded; (2) control of switched capacitor noise tends to be complex and difficult because the gain of some PGAs requires that the series-parallel combination of capacitors be equivalent to a smaller capacitance value, resulting in increased switched capacitor noise.

Fig. 1 is a schematic diagram of a conventional fully differential output switch capacitor PGA, where a control clock signal of a CMOS switch is an equal-duration two-phase square wave with non-overlapping characteristics, a pulse square wave of a first phase is sampling time, a pulse square wave of a second phase is amplification or integration time, and charges sampled at a differential output end by input capacitors 130 to 133 for an input differential signal 101 and feedback capacitors 134 to 137 are integrated by a feedback path through an operational amplifier 150. This achieves sampling of the signal + PGA amplification within the time of one cycle. The gain adjustment is achieved with a simple different parallel combination of two pairs of input capacitors and two pairs of output capacitors. The circuit diagram of fig. 1 is illustrated as follows:

101 is a differential signal source, 102 is a common-mode voltage;

103/104,107/108, and 111/112 are CMOS switch tubes that are closed during periods of φ 1;

105/106, 109/110, and 113/114 are CMOS switch tubes that are closed during periods of φ 2;

130/131/132/133 is the input signal sampling capacitance, the capacitance values of 130 and 132,131 and 133 are equal;

134/135/136/137 is the feedback path sampling capacitance, the capacitance values of 134 and 136,135 and 137 are equal;

140/141 integrating capacitance, both capacitance values are equal;

150 is a fully differential operational amplifier;

111 is an operational amplifier;

c L K1 and C L K2 are the gate control signals of the switching tube generated by a pair of inverted non-overlapping pulse generators respectively, and phi 1 and phi 2 are the sampling and integrating periods respectively;

120/121, 122/123, 124/125, and 126/127 are switches that combine input and feedback capacitors to control the closing and opening of the switches according to gain requirements.

According to the working principle of the switch capacitor, when the PGA finishes the integral time phi 2, the amplification factor of the output voltage is the proportion of the input capacitor and the feedback capacitor,

Gain＝Vout(n)/Vin(n)＝(C₁₃₀+C₁₃₁)/(C₁₃₄+C₁₃₅) Wherein n is the number of pulse periods,

as for the grading of the gains, 4 different connections of capacitors 130/131 and 134/135 may constitute 4 different gains. It is clear that if a more subdivided gain adjustment capability is desired, more capacitors and switches need to be added to the input and feedback paths. According to the relation between the matching error of two equal capacitors and the area of the capacitor,

where Δ C is the error value of the capacitance, W. L represents the width and length of the capacitance occupied on the chip,

therefore, each capacitor occupied area required for controlling the matching error cannot be too small, so that the increasing and avoiding of the PGA gain subdivision gear needs larger capacitor occupied area, and meanwhile, the accumulation of the matching error is increased along with the increase of the capacitor, so that the precision of gain subdivision is influenced.

The formula of the effective value of the thermal noise voltage of the switched capacitor is as follows:

wherein K is a constant, T is an absolute temperature value, C is a capacitance value, (1)

It can be seen that when the combined capacitance value is reduced due to the requirement of gain adjustment, the noise of the switched capacitor is increased, so that the signal-to-noise ratio of the PGA signal amplification is degraded. Usually, only the capacitance of the switched capacitor can be increased to maintain a reasonable signal-to-noise ratio, which not only increases the chip area cost, but also increases the power consumption of the chip due to the increase of the current required for charging and discharging the capacitor.

Disclosure of Invention

The invention aims to provide a low-noise switched capacitor amplification circuit (HRPGA) capable of adjusting amplification factor with high resolution and a design method thereof, which can keep low noise of the switched capacitor circuit under the condition of realizing wide range and fine adjustment of amplification factor, simultaneously reduce power consumption and cost and improve detection precision and efficiency of a signal detection circuit.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

on one hand, the invention provides a high-resolution gain-adjustable low-noise switched capacitor amplifier, which comprises a signal input circuit of a switched capacitor, an amplifying circuit and a feedback circuit, and also comprises an algorithm modulation circuit and a delta-sigma encoder, wherein the algorithm modulation circuit comprises two pairs of CMOS switching tubes, the input of the amplifying circuit samples the voltage of an input signal through a pair of input capacitors, then the sampled voltage is subjected to operational amplifier integration, the feedback of the amplifying circuit samples the output voltage through a pair of feedback capacitors, then the sampled voltage is subjected to operational amplifier integration, and the delta-sigma encoder controls the on-off of the two pairs of CMOS switching tubes through encoding so as to modulate the input capacitor or the feedback capacitor.

As a first preferred circuit structure scheme, the input capacitor includes a first input capacitor and a second input capacitor, the feedback capacitor includes a first feedback capacitor and a second feedback capacitor, and the two pairs of CMOS switch tubes are respectively a first CMOS switch tube, a second CMOS switch tube, a third CMOS switch tube and a fourth CMOS switch tube; one end of the first input capacitor is connected with the source end, the other end of the first input capacitor is respectively connected with one end of the first CMOS switch tube and one end of the second CMOS switch tube, one end of the second input capacitor is connected with the source end, and the other end of the second input capacitor is respectively connected with one end of the third CMOS switch tube and one end of the fourth CMOS switch tube; the other ends of the first CMOS switch tube and the third CMOS switch tube are both connected with one end of a first feedback capacitor, the other ends of the first CMOS switch tube and the third CMOS switch tube are also connected with the ground after being connected with a ninth CMOS switch tube and are connected with the inverting input end of the operational amplifier through a fifteenth CMOS switch tube, the other end of the first feedback capacitor is connected with the ground after being connected with an eleventh CMOS switch tube on one hand, and is also connected with one end of a first integrating capacitor and the non-inverting output end of the operational amplifier through a thirteenth CMOS switch tube on the other hand, and the other end of the first integrating capacitor is connected with the inverting input end of the operational; the other ends of the second CMOS switch tube and the fourth CMOS switch tube are both connected with one end of a second feedback capacitor, the other ends of the second CMOS switch tube and the fourth CMOS switch tube are grounded after being connected with a tenth CMOS switch tube and are connected with the non-inverting input end of the operational amplifier through a sixteenth CMOS switch tube, the other end of the second feedback capacitor is grounded after being connected with a twelfth CMOS switch tube on the one hand, and is connected with one end of a second integrating capacitor and the inverting output end of the operational amplifier through a fourteenth CMOS switch tube on the other hand, and the other end of the second integrating capacitor is connected with the non-inverting input end of the operational amplifier.

As a second preferred circuit structure scheme, the input capacitor includes a first input capacitor and a second input capacitor, the feedback capacitor includes a first feedback capacitor and a second feedback capacitor, and the two pairs of CMOS switch tubes are respectively a first CMOS switch tube, a second CMOS switch tube, a third CMOS switch tube and a fourth CMOS switch tube; one end of the first input capacitor is connected with the source end, the other end of the first input capacitor is respectively connected with one end of the first CMOS switch tube and one end of the second CMOS switch tube, the first input capacitor is further connected with the negative phase input end of the operational amplifier through the ninth CMOS switch tube and then grounded and the fifteenth CMOS switch tube, one end of the second input capacitor is connected with the source end, the other end of the second input capacitor is respectively connected with one end of the third CMOS switch tube and one end of the fourth CMOS switch tube, the first input capacitor is further connected with the positive phase input end of the operational amplifier through the tenth CMOS switch tube and then grounded and the sixteenth CMOS switch tube; the other ends of the first CMOS switch tube and the third CMOS switch tube are both connected with one end of a first feedback capacitor, the other end of the first feedback capacitor is grounded after being connected with an eleventh CMOS switch tube on one hand, and is also respectively connected with one end of a first integrating capacitor and the in-phase output end of the operational amplifier through a thirteenth CMOS switch tube on the other hand, and the other end of the first integrating capacitor is connected with the anti-phase input end of the operational amplifier; the other ends of the second CMOS switch tube and the fourth CMOS switch tube are both connected with one end of a second feedback capacitor, the other end of the second feedback capacitor is grounded after being connected with the twelfth CMOS switch tube on one hand, and is also respectively connected with one end of a second integrating capacitor and the inverted output end of the operational amplifier through a fourteenth CMOS switch tube on the other hand, and the other end of the second integrating capacitor is connected with the non-inverting input end of the operational amplifier.

Furthermore, the source ends in the two structures comprise a differential signal source, a common-mode voltage, a fifth CMOS switch tube, a sixth CMOS switch tube, a seventh CMOS switch tube and an eighth CMOS switch tube, the differential signal source is connected with the common-mode voltage and is also respectively connected with one end of the fifth CMOS switch tube and one end of the sixth CMOS switch tube, the other end of the fifth CMOS switch tube is connected with the first input capacitor on one hand and is grounded through being connected with the seventh CMOS switch tube on the other hand, and the other end of the sixth CMOS switch tube is connected with the second input capacitor on the one hand and is grounded through being connected with the eighth CMOS switch tube on the other hand.

On the other hand, the invention also provides a design method of the high-resolution gain-adjustable low-noise switched capacitor amplifier, which is characterized in that a set gain value is modulated by a delta-sigma algorithm and then a code which is composed of 1 and 0 and is synchronous with a switch clock is output, and the code controls the connection and disconnection of an input capacitor or a feedback capacitor, wherein: "1" means closed, "0" means open, and a code "1" is designed in the circuit to integrate the input signal or feedback signal in the forward direction, and a code "0" is designed to integrate the input signal or feedback signal in the reverse direction.

Furthermore, the input capacitance of the PGA is respectively connected to the integrating amplifier through two pairs of switches, one pair of switches is a forward integrating path to increase the integrated output voltage, the other pair of switches is a reverse integrating path to decrease the integrated output voltage, and the binary '1' and '0' coded outputs of the digital delta-sigma coder are respectively communicated with the forward integrating path and the reverse integrating path of the integrating amplifier.

Further, the clock signals of the two phases are mutually opposite in phase, and the clock levels of the two phases do not have the overlapping time of "1" at the same time, which is used for providing the switching control of each clock period for the switching capacitor of the HRPGA.

Furthermore, the input is a multi-bit binary digit vector for setting gain, the bit number of the multi-bit binary digit vector defines the resolution for adjusting the gain, the multi-bit binary digit vector is output as a pair of biphase non-overlapping 1-bit binary digit signals after being processed by a modulation function, the quantization noise of a low frequency band is transferred to a high frequency band after being processed by a delta-sigma modulation algorithm, and the order of the modulator is increased according to the improvement requirement of the gain resolution.

Further, an analog low pass filter following the HRPGA filters the high frequency delta-sigma coded modulation to introduce quantization noise, and the bandwidth and order of the low pass filter needs to be matched with the bandwidth and order of the delta-sigma modulator to achieve a sufficient amount of attenuation of the quantization noise. Preferably, the order of the filter is greater than the order of the delta-sigma modulation algorithm.

The invention has the beneficial effects that: the invention modulates the equivalent capacitance value of the input or feedback capacitor of the switch capacitor PGA through the 1-bit digital coding generated by the delta-sigma algorithm, thereby achieving the aim of adjusting the PGA gain with high resolution. Because there is no matching error and parasitic capacitance between multiple capacitors, the gain adjustment resolution of the HRPGA is not achievable by the conventional method of adjusting gain by combining multiple capacitors in series and parallel. From the viewpoint of chip area cost, it is a better cost performance to replace a plurality of capacitors which need a certain area with digital circuits. In addition, the signal-to-noise ratio of the HRPGA is simple in design and easy to design, and does not have complex consideration brought by multi-capacitor combination.

Drawings

Fig. 1 is a schematic diagram of a conventional fully-differential switched capacitor PGA.

Fig. 2a is a schematic diagram of an HRPGA with a fully differential structure, delta-sigma coded modulation input switched capacitor.

Fig. 2b is a schematic diagram of the CMOS switch control signal and Vout waveform of the fully differential HRPGA.

Fig. 3 is a schematic diagram of an HRPGA with a fully differential structure, and a delta-sigma coded modulation feedback switch capacitor.

Fig. 4a is a two-order digital delta-sigma modulator.

Fig. 4b is a schematic diagram of the frequency spectrum of a 1-bit modulated control signal.

Fig. 5 is a simplified diagram of the hrpa system.

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments.