阅读说明：本技术 核壳式结构GaN结型场效应管器件及其制备方法 (Core-shell structure GaN junction field effect transistor device and preparation method thereof ) 是由 邵鹏飞 郭慧 陈敦军 谢自力 于 2020-05-14 设计创作，主要内容包括：本发明公开了一种核壳式结构GaN结型场效应管器件及其制备方法。该方法首先利用MBE/MOCVD技术在蓝宝石衬底生长第二重掺n-GaN层,作为后续的漏端欧姆接触层,再继续外延核壳式纳米柱状p-n结,内层n-GaN为沟道层,最后再外延一层重掺的n-GaN作为源端欧姆接触层。器件结构生长完后再利用刻蚀和电极蒸发工艺形成源漏极和栅极,得到GaN-JFET器件；核壳式p-n结结构因沟道被环形包夹,其内部电场分布更均匀,栅对沟道具有更强的控制能力。(The invention discloses a core-shell structure GaN junction field effect transistor device and a preparation method thereof. The method comprises the steps of firstly growing a second heavily doped n-GaN layer on a sapphire substrate by using an MBE/MOCVD technology to serve as a subsequent drain-end ohmic contact layer, then continuing to epitaxially grow a core-shell type nano columnar p-n junction, taking the inner layer n-GaN as a channel layer, and finally epitaxially growing a layer of heavily doped n-GaN as a source-end ohmic contact layer. After the device structure grows, a source drain and a grid are formed by etching and electrode evaporation processes to obtain a GaN-JFET device; the core-shell type p-n junction structure has the advantages that the channel is annularly wrapped, the electric field distribution in the core-shell type p-n junction structure is more uniform, and the grid has stronger control capability on the channel.)

1. A core-shell structure GaN junction field effect transistor device, the structure of which comprises:

a substrate layer;

a semi-insulating GaN layer grown on the substrate layer;

a first heavily doped n-GaN layer grown on the semi-insulating GaN layer;

an n-GaN nanorod channel layer grown on the heavily doped n-GaN layer;

a graphical mask Si3N4 layer grows on the heavily doped N-GaN layer except the nano columnar N-GaN layer;

and p-GaN growing on the mask Si3N4 layer, wherein the p-GaN is annular and wraps the N-GaN nanorod channel layer to form a core-shell p-N junction;

the silicon-doped N-GaN substrate further comprises a Si3N4 layer extending on the top of the annular p-GaN layer and a second heavily-doped N-GaN layer extending on the top of the N-GaN nanorod channel layer;

the source electrode and the drain electrode are respectively arranged on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer;

and the gate electrode is arranged around the annular p-GaN and is in contact with the side wall surface of the annular p-GaN to form a gate electrode with an annular structure.

2. The core-shell structure GaN junction field effect device of claim 1, wherein: the substrate layer is a sapphire substrate, a Si substrate or a SiC substrate.

3. The core-shell structure GaN junction field effect device of claim 1, wherein: the height of the semi-insulating GaN layer is 2-5 mu m.

4. The core-shell structure GaN junction field effect device of claim 1, wherein: the thickness of the first heavily doped n-GaN layer is 300-400nm, and a patterned mask Si is formed₃N₄The layer thickness is 80-100 nm.

5. The core-shell structure GaN junction field effect device of any of claims 1-4, wherein: the diameter of the n-GaN nanorod channel layer is 200-300nm, and the channel length is 0.8-1 μm; the top of the p-GaN is lower than that of the n-GaN nanorod channel layer, the thickness of the p-GaN is 100-200nm, the length of the p-GaN is 600-700nm, and the doping concentration is 1 x 10¹⁸-1*10¹⁹cm^-3And controlling the diameter of the n-GaN nanorod channel layer to enable the channel to be in a depletion state under zero bias.

6. The core-shell structure GaN junction field effect device of claim 5, wherein: the thickness of the second heavily doped n-GaN layer is 300-400nm, and Si is deposited on the annular p-GaN layer₃N₄The layer thickness is 80-100 nm.

7. The core-shell structure GaN junction field effect device of claim 6, wherein: the source electrode and the drain electrode are made of Ti/Al/Ni/Au multilayer metal and have the thickness of 30/150/50/150nm, and the gate electrode is made of Ni/Au multilayer metal and have the thickness of 50/100 nm.

8. The method for preparing the core-shell structure GaN junction field effect transistor device of any of claims 1-7, comprising the steps of:

(1) depositing a semi-insulating GaN layer, a first heavily doped n-GaN layer and Si on the surface of the substrate by MOCVD method₃N₄A mask layer on the mask Si₃N₄A space for the growth of the n-GaN nano column is reserved on the layer;

(2) growing a core-shell type nano-column p-n junction on the first heavily doped n-GaN layer by an MBE method, wherein the inner layer n-GaN nano-column is a channel layer, and the outer layer is annular p-GaN to form the core-shell type p-n junction;

(3) adopting a mask region selection process, and using an MBE system to regrow a second heavily doped n-GaN layer on the n-GaN nanorod channel layer; etching p-GaN at the contact end of the annular p-GaN and the second heavily doped n-GaN by photoetching, ICP etching and PECVD, and depositing Si₃N₄A layer;

(4) exposing a first heavily doped n-GaN layer at one end of the device by adopting photoetching and ICP (inductively coupled plasma) etching methods, manufacturing Ti/Al/Ni/Au source and drain metal electrodes on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer respectively by using an electron beam evaporation method, and manufacturing a Ni/Au gate metal electrode with an annular structure on the surface of the side wall of the p-GaN.

9. The method for manufacturing the core-shell structure GaN junction field effect transistor device according to claim 8, wherein:

the method for growing the semi-insulating GaN in the step (1) comprises the following steps: trimethyl gallium and NH₃Respectively as Ga source and N source, and H as carrier gas₂Or N₂The growth temperature is 1000-1100 ℃, and the growth time is 3-5 h; the growth method of the heavily doped n-GaN layer comprises the following steps: the temperature is 950-¹⁹cm^-3The growth time is 25-30 min; growing patterned Si on heavily doped n-GaN layer by PECVD and photoetching technology₃N₄A mask layer;

the method for growing the core-shell type nano columnar p-N junction in the step (2) is that ① N-GaN nano columns grow metal gallium and N₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the silicon doping concentration is 1 x 10¹⁸cm^-3Growing under N-rich condition for 3-4 hr, ② growing annular p-GaN shellGallium and N₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the magnesium doping concentration is 1 x 10¹⁸cm^-3Growing under the Ga-rich condition for 3-4 h;

and (3) epitaxially growing a heavily doped n-GaN layer on the n-GaN channel: gallium and N metal₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the silicon doping concentration is 1 x 10¹⁹cm^-3The growth time is 1-2 h;

and (4) respectively manufacturing Ti/Al/Ni/Au source and drain metal electrodes on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer by using an electron beam evaporation method, manufacturing a Ni/Au gate metal electrode with a ring structure on the surface of the side wall of the p-GaN layer, and performing annealing at 850 ℃ for 30s in a rapid thermal annealing furnace.

Technical Field

The invention relates to a core-shell structure GaN junction field effect transistor device, and belongs to the field of semiconductor devices.

Background

Junction field effect transistors are core devices in circuits or devices such as complementary transistor logic circuits, current sense amplifiers, analog-to-digital converter drivers, photodiode transimpedance amplifiers and the like, and the circuits or devices have important applications in the fields of power transmission, transportation, consumer electronics and the like. The GaN-based field effect transistor has the advantages of high working frequency, low on resistance, high power density, high breakdown voltage resistance and the like, and has important application prospects in the fields of variable resistors and power amplifiers. The conventional Junction Field Effect Transistor (JFET) needs to realize a p-n junction by utilizing a regrowth or ion implantation process, and the preparation process is complex.

Disclosure of Invention

The invention describes a method for designing and manufacturing a core-shell type p-n junction structure GaN Junction Field Effect Transistor (JFET). The n-type nano-pillar channel on the inner layer of the core-shell structure is surrounded by the outer layer of p-type GaN, and the current of the n-type nano-pillar channel can be controlled through the gate electrode on the p-type GaN layer, so that the junction field effect transistor with the core-shell structure is realized.

The invention aims to design and manufacture a core-shell type p-n junction structure GaN Junction Field Effect Transistor (JFET).

The purpose of the invention is realized by the following technical scheme:

a core-shell structure GaN junction field effect transistor device, the structure of which comprises:

a substrate layer;

a semi-insulating GaN layer grown on the substrate layer;

a first heavily doped n-GaN layer grown on the semi-insulating GaN layer and used as a subsequent drain ohmic contact layer;

an n-GaN nanorod channel layer grown on the heavily doped n-GaN layer;

a graphical mask Si is grown on the heavily doped n-GaN layer except the nano columnar n-GaN layer₃N₄A layer;

and grown on mask Si₃N₄The p-GaN on the layer is annular and wraps the n-GaN nanorod channel layer to form a core-shell type p-n junction;

further comprising Si epitaxially atop the annular p-GaN₃N₄The second heavily doped n-GaN layer is extended on the top of the n-GaN nanorod channel layer and serves as a source ohmic contact layer;

the source electrode and the drain electrode are respectively arranged on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer;

and the gate electrode is arranged around the annular p-GaN and is in contact with the side wall surface of the annular p-GaN to form a gate electrode with an annular structure.

Preferably, the substrate layer is a sapphire substrate, a Si substrate or a SiC substrate.

Preferably, the height of the semi-insulating GaN layer is 2-5 μm.

Preferably, the thickness of the first heavily doped N-GaN layer is 300-400nm, and the thickness of the patterned mask Si3N4 layer is 80-100 nm.

Preferably, the diameter of the n-GaN nanorod channel layer is 200-300nm, and the channel length is 0.8-1 μm; the top of the p-GaN is lower than the top of the n-GaN nanorod channel layer, the thickness of the p-GaN is 100-.

Preferably, the thickness of the second heavily doped N-GaN layer is 300-400nm, and the thickness of the Si3N4 layer deposited on the annular p-GaN layer is 80-100 nm.

Preferably, the source electrode and the drain electrode are made of Ti/Al/Ni/Au multilayer metal and have the thickness of 30/150/50/150nm, and the gate electrode is made of Ni/Au multilayer metal and have the thickness of 50/100 nm.

The invention also discloses a preparation method of the core-shell structure GaN junction field effect transistor device, which comprises the following steps:

(1) depositing a semi-insulating GaN layer, a first heavily doped n-GaN layer and Si on the surface of the substrate by MOCVD method₃N₄A mask layer on the mask Si₃N₄A space for the growth of the n-GaN nano column is reserved on the layer;

(2) growing a core-shell type nano-column p-n junction on the first heavily doped n-GaN layer by an MBE method, wherein the inner layer n-GaN nano-column is a channel layer, and the outer layer is annular p-GaN to form the core-shell type p-n junction;

(3) adopting a mask region selection process, and using an MBE system to regrow a second heavily doped n-GaN layer on the n-GaN nanorod channel layer; etching p-GaN at the contact end of the annular p-GaN and the second heavily doped n-GaN by photoetching, ICP etching and PECVD, and depositing Si₃N₄A layer;

(4) exposing a first heavily doped n-GaN layer at one end of the device by adopting photoetching and ICP (inductively coupled plasma) etching methods, manufacturing Ti/Al/Ni/Au source and drain metal electrodes on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer respectively by using an electron beam evaporation method, and manufacturing a Ni/Au gate metal electrode with an annular structure on the surface of the side wall of the p-GaN.

Preferably, the method for growing semi-insulating GaN in the step (1): trimethyl gallium and NH₃Respectively as Ga source and N source, and H as carrier gas₂Or N₂The growth temperature is 1000-1100 ℃, and the growth time is 3-5 h; the growth method of the heavily doped n-GaN layer comprises the following steps: the temperature is 950-¹⁹cm^-3The growth time is 25-30 min; growing patterned Si on heavily doped n-GaN layer by PECVD and photoetching technology₃N₄A mask layer;

the method for growing the core-shell type nano columnar p-N junction in the step (2) is that ① N-GaN nano columns grow metal gallium and N₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the silicon doping concentration is 1 x 10¹⁸cm^-3Growing under N-rich condition for 3-4 hr, ② growing annular p-GaN shell of gallium and N₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the magnesium doping concentration is 1 x 10¹⁸cm^-3Growing under the Ga-rich condition for 3-4 h;

and (3) epitaxially growing a heavily doped n-GaN layer on the n-GaN channel: gallium and N metal₂Respectively used as Ga source and N source, the growth temperature is 890-930 ℃, the plasma power is 450W, the nitrogen flow is 0.7sccm, the silicon doping concentration is 1 x 10¹⁹cm^-3The growth time is 1-2 h;

and (4) respectively manufacturing Ti/Al/Ni/Au source and drain metal electrodes on the surfaces of the second heavily doped n-GaN layer and the first heavily doped n-GaN layer by using an electron beam evaporation method, manufacturing a Ni/Au gate metal electrode with a ring structure on the surface of the side wall of the p-GaN layer, and performing annealing at 850 ℃ for 30s in a rapid thermal annealing furnace.

The core-shell type p-n junction nano columnar structure can be prepared by directly controlling a growth mode, an n-type channel is annularly enclosed by a p-type layer, the distribution of an internal electric field is more uniform, and a gate has stronger control capability on channel current. The invention provides a core-shell structure GaN JFET with high grid control capability, and the grid of the traditional JFET is planar and obviously inferior to the control capability of a ring-shaped clamping structure on a channel. The core-shell type p-n junction structure GaN junction field effect transistor has the advantages that the control capability of the gate electrode on the channel is strong, the channel has better electric field uniformity, and the reliability of the device is improved.

Drawings

FIG. 1 shows heavily doped n-GaN and patterned Si obtained in step (1) of example 1₃N₄And the structure of the epitaxial wafer is shown schematically.

Fig. 2 is a schematic structural diagram of the core-shell type nano-pillar p-n junction epitaxial wafer obtained in step (2) of example 1.

Fig. 3 is a schematic structural view of the top-end epitaxial heavily-doped n-GaN epitaxial wafer of the n-GaN nano-pillar channel layer obtained in step (3) of example 1.

Fig. 4 is a schematic view of a core-shell GaN jfet structure obtained in step (4) of example 1.

Fig. 5 is a schematic diagram of the core-shell GaN jfet of fig. 3 with dimensions in various directions.

Detailed description of the invention

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.