阅读说明：本技术 一种基于应变的光集成器件结构 (Optical integrated device structure based on strain ) 是由 尹晓雪 于 2018-12-20 设计创作，主要内容包括：本发明涉及一种基于应变的光集成器件结构。该结构包括：硅衬底(001)；LED(10)、波导(20)、探测器(30)、NMOS器件(40)和PMOS器件(50),均依次横向设置在所述硅衬底(001)上；两个第一沟槽(0021),设置在所述硅衬底(001)上,并位于所述LED(10)、波导(20)、探测器(30)的两侧；第一沟槽(0022),设置在所述NMOS器件(40)和所述PMOS器件(50)的中间；两个第三沟槽(016),设置在所述波导(20)的两侧；应力氮化硅膜,设置在所述波导(20)、所述探测器(30)、所述NMOS器件(40)和所述PMOS器件(50)上。本发明将LED、波导、探测器、NMOS器件以及PMOS器件集成到一块衬底上集成到一块衬底上制作形成基于应变的光集成器件,器件结构新颖兼容性好、器件集成度高、工艺成本低。(The invention relates to a strain-based optical integrated device structure which comprises a silicon substrate (001), L ED (10), a waveguide (20), a detector (30), an NMOS device (40) and a PMOS device (50), wherein the L ED (10), the waveguide (20), the detector (30), the NMOS device (40) and the PMOS device (50) are sequentially and transversely arranged on the silicon substrate (001), two first grooves (0021) are arranged on the silicon substrate (001) and are positioned on two sides of the L ED (10), the waveguide (20) and the detector (30), first grooves (0022) are arranged in the middle of the NMOS device (40) and the PMOS device (50), two third grooves (016) are arranged on two sides of the waveguide (20), stress silicon nitride films are arranged on the waveguide (20), the detector (30), the NMOS device (40) and the PMOS device (50), L ED, the waveguide, the detector, the NMOS device and the PMOS device are integrated on one substrate to form the strain-based optical integrated device, and the strain-based optical integrated device is good in structure compatibility, novel, high in degree, and low in process cost.)

1. A strain-based photonic integrated device structure, comprising:

a silicon substrate (001);

l ED (10), a waveguide (20), a detector (30), an NMOS device (40) and a PMOS device (50), all arranged on the silicon substrate (001) horizontally in sequence;

two first trenches (0021) disposed on the silicon substrate (001) and located on both sides of the L ED (10), waveguide (20), detector (30);

a first trench (0022) disposed intermediate the NMOS device (40) and the PMOS device (50);

two third trenches (016) disposed on both sides of the waveguide (20);

a stressed silicon nitride film disposed on the waveguide (20), the detector (30), the NMOS device (40), and the PMOS device (50).

2. The method of claim 1, wherein the L ED (10) comprises a third epitaxial layer (008), a first Ge layer (009), and a first step portion disposed in that order.

3. The method of claim 2, wherein the first step portion includes a first intrinsic Ge layer (010), an intrinsic GeSn alloy layer (011), a second intrinsic Ge layer (012), a second Ge layer (013), an n-type Si layer (014), and a second oxide layer (015) sequentially disposed.

4. A method as claimed in claim 3, wherein the detector (30) comprises the third epitaxial layer (008), the first Ge layer (009), and a second step portion arranged in that order.

5. The method of claim 4, wherein the second step portion comprises the first intrinsic Ge layer (010), the intrinsic GeSn alloy layer (011), the second intrinsic Ge layer (012), the second Ge layer (013), the n-type Si layer (014), and the second oxide layer (015) sequentially disposed.

6. The method of claim 5, wherein the waveguide (20) comprises the first intrinsic Ge layer (010), the intrinsic GeSn alloy layer (011), and a capping layer (017).

7. The method of claim 1, wherein the first intrinsic Ge layer (010) has a thickness of 40 to 50nm, the intrinsic GeSn alloy layer (011) has a thickness of 250nm and an Sn component content of 8%, the second intrinsic Ge layer (012) has a thickness of 40 to 50nm, and the second Ge layer (013) has a thickness of 100nm and a doping concentration of 3 x 10¹⁹cm^-3The n-type Si layer (014) has a thickness of 100nm and a doping concentration of 10²⁰cm^-3And the thickness of the second oxide layer (015) is 10 nm.

8. The method of claim 7, wherein the NMOS device (40) comprises a first epi sub-region (0024A), a second source region (007A), a second drain region (007B), a second polysilicon gate (018B), and a second electrode (019B).

9. The method of claim 8, wherein the PMOS device (50) includes an n-well (005), a first source region (006A), a first drain region (006B), a first polysilicon gate (018A), and a first electrode (019A).

10. The method of claim 1, wherein the stressed silicon nitride film comprises:

a compressively stressed silicon nitride film 020 disposed over the waveguide (20) and PMOS device (50);

and the tensile stress silicon nitride film 021 is arranged on the detector (30) and the NMOS device.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a strain-based optical integrated device structure.

Background

A photodetector is a kind of photodetector device made by using the photoconductive effect of semiconductor materials. The photoelectric detector has wide application in various fields of military and national economy. The infrared radiation sensor is mainly used for ray measurement and detection, industrial automatic control, photometric measurement and the like in visible light or near infrared wave bands; the infrared band is mainly used for missile guidance, infrared thermal imaging, infrared remote sensing and the like.

With the development of large-scale integrated circuit technology, the feature size of devices is continuously reduced, the integration scale is larger and larger, the information processing capability is continuously enhanced, and how to realize the integration of photoelectric detection devices, namely optical devices and MOS devices, on a single chip becomes a problem to be solved urgently.

Disclosure of Invention

Therefore, in order to solve the technical defects and shortcomings of the prior art, the invention provides a strain-based optical integrated device structure.

Specifically, an embodiment of the present invention provides a strain-based optical integrated device structure, including:

a silicon substrate 001;

l ED10, waveguide 20, detector 30, NMOS device 40, and PMOS device 50, all disposed laterally in that order on the silicon substrate 001;

two first trenches 0021 disposed on the silicon substrate 001 and located on both sides of the L ED10, waveguide 20, and detector 30;

a first trench 0022 disposed intermediate the NMOS device 40 and the PMOS device 50;

two third trenches 016 disposed at both sides of the waveguide 20;

a stressed silicon nitride film disposed over the waveguide 20, the detector 30, the NMOS device 40, and the PMOS device 50.

In one embodiment of the present invention, the L ED10 includes a third epitaxial layer 008, a first Ge layer 009, and a first step portion 10 sequentially disposed¹⁶cm^-3。

In one embodiment of the present invention, the first step portion includes a first intrinsic Ge layer 010, an intrinsic GeSn alloy layer 011, a second intrinsic Ge layer 012, a second Ge layer 013, an n-type Si layer 014, and a second oxide layer 015, which are sequentially disposed.

In one embodiment of the present invention, the detector 30 includes the third epitaxial layer 008, the first Ge layer 009, and a second stepped portion, which are sequentially disposed.

In one embodiment of the present invention, the second step portion includes the first intrinsic Ge layer 010, the intrinsic GeSn alloy layer 011, the second intrinsic Ge layer 012, the second Ge layer 013, the n-type Si layer 014, and the second oxide layer 015, which are sequentially disposed.

In one embodiment of the present invention, the waveguide 20 includes the first intrinsic Ge layer 010, the intrinsic GeSn alloy layer 011, and a capping layer 017.

In an embodiment of the present invention, the first intrinsic Ge layer 010 has a thickness of 40 to 50nm, the intrinsic GeSn alloy layer 011 has a thickness of 250nm and a Sn composition content of 8%, the second intrinsic Ge layer 012 has a thickness of 40 to 50nm, the second Ge layer 013 has a thickness of 100nm and a doping concentration of 3 x 10¹⁹cm^-3The n-type Si layer 014 has a thickness of 100nm and a doping concentration of 10²⁰cm^-3The second oxide layer 015 is 10nm thick.

In one embodiment of the invention, the NMOS device 40 includes a first epi sub-layer sub-region 0024A, a second source region 007A, a second drain region 007B, a second polysilicon gate 018B, and a second electrode 019B.

In one embodiment of the present invention, the PMOS device 50 includes an n-well 005, a first source region 006A, a first drain region 006B, a first polysilicon gate 018A, and a first electrode 019A.

In one embodiment of the present invention, a stressed silicon nitride film comprises:

a compressive stress silicon nitride film 020 disposed on the waveguide 20 and the PMOS device 50;

and a tensile stress silicon nitride film 021 arranged on the detector 30 and the NMOS device.

The invention has the following beneficial effects:

according to the invention, L ED, a waveguide, a detector, an NMOS device and a PMOS device are integrated on a substrate, stress is introduced through the stress silicon nitride film, and on the basis of improving the performance of the device, the device has the advantages of novel structure, good compatibility, high integration level of the device and low process cost.

Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a strain-based optical integrated device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another strain-based optical integrated device according to an embodiment of the present invention;

fig. 3a to fig. 3u are schematic views illustrating a process for fabricating a strain-based photonic integrated device according to an embodiment of the present invention;

FIG. 4a is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 3n according to an embodiment of the present invention;

FIG. 4b is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 3o according to an embodiment of the present invention;

FIG. 4c is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 3p according to an embodiment of the present invention;

FIG. 4d is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 3q according to an embodiment of the present invention;

FIG. 4e is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 3r according to an embodiment of the present invention;

FIG. 4f is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 3s according to an embodiment of the present invention;

FIG. 4g is a top view of a device formed by the strain-based optical integrated device of FIG. 3t according to an embodiment of the present invention;

FIG. 4h is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 3u according to an embodiment of the present invention;

FIGS. 5 a-5 c are schematic top views of three tapered waveguides provided in embodiments of the present invention;

FIG. 6 is a schematic diagram of transmittance at different wavelengths of three types of tapered waveguides, namely, a linear type waveguide, a convex type waveguide and a concave type waveguide, according to an embodiment of the present invention;

FIG. 7 is a graph showing the transmittance of a tapered waveguide at three lengths of 5 μm, 10 μm, and 15 μm for different wavelengths according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of the transmittance of the isolation layer at different thicknesses according to an embodiment of the present invention;

fig. 9 is a schematic diagram of the transmittance of the cover layer at different wavelengths according to the embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.