阅读说明：本技术 一种基于应变的光集成器件及其制备方法 (Optical integrated device based on strain and preparation method thereof ) 是由 尹晓雪 于 2018-12-20 设计创作，主要内容包括：本发明涉及一种基于应变的光集成器件及其制备方法。该制备方法包括：在硅衬底上生长硅外延层；在所述硅外延层上刻蚀第一沟槽形成第一外延层区域以及第二外延层区域；在所述第二外延层区域刻蚀第二沟槽形成第一外延层子区域以及第二外延层子区域；在所述第一外延层子区域以及所述第二外延层子区域中分别制备NMOS器件以及PMOS器件；在所述第一外延层区域中制备LED、波导以及探测器；在所述NMOS器件、PMOS器件、波导以及探测器生长应力氮化硅膜最终形成基于应变的光集成器件。本发明将LED、波导、探测器、NMOS器件以及PMOS器件集成到一块衬底上集成到一块衬底上制作形成基于应变的光集成器件,器件结构新颖兼容性好、器件集成度高、工艺成本低。(The invention relates to a strain-based optical integrated device and a preparation method thereof.)

1. A method for preparing a strain-based optical integrated device is characterized by comprising the following steps:

growing a silicon epitaxial layer on a silicon substrate;

etching a first groove on the silicon epitaxial layer to form a first epitaxial layer region and a second epitaxial layer region;

etching a second groove in the second epitaxial layer region to form a first epitaxial layer sub-region and a second epitaxial layer sub-region;

respectively preparing an NMOS device and a PMOS device in the first epitaxial layer sub-region and the second epitaxial layer sub-region;

preparing L ED, waveguide and detector in the first epitaxial layer region;

and growing a stress silicon nitride film on the NMOS device, the PMOS device, the waveguide and the detector to finally form the optical integrated device based on strain.

2. The method of claim 1, wherein growing a silicon epitaxial layer on a silicon substrate comprises:

selecting a silicon substrate;

growing the silicon substrate with the doping concentration of 10¹⁶cm^-3P-type silicon epitaxial layer.

3. The method of claim 1, wherein after etching the second trench in the second epitaxial layer region to form a first epitaxial layer sub-region and a second epitaxial layer sub-region, further comprising:

and depositing a first oxide layer with the thickness of 10-20 nm on the first trench, the first epitaxial layer region, the first epitaxial layer sub-region, the second epitaxial layer sub-region and the second trench by using a low-temperature plasma enhanced chemical vapor deposition process at the temperature of 250-450 ℃.

4. The method of claim 3, wherein fabricating an NMOS device and a PMOS device in the first epitaxial layer sub-region and the second epitaxial layer sub-region, respectively, comprises:

performing P ion implantation on the second epitaxial layer sub-region at the temperature of 200-300 ℃ by using an ion implantation process to form a second epitaxial layer with the concentration of 10^#6cm^-3An n-well of (1);

performing B ion implantation on the n-well by using an ion implantation process at the temperature of 200-300 ℃ to form a doped concentration of 10²⁰cm^-3A first source region and a first drain region;

performing P ion implantation on the first epitaxial layer sub-region by using an ion implantation process at the temperature of 200-300 ℃ to form doping concentrations of 10²⁰cm^-3A second source region and a second drain region;

respectively preparing a first polysilicon gate and a second polysilicon gate with the thickness of 50-60 nm on the n well and the first oxide layer on the first epitaxial layer sub-region;

growing metal Al with the thickness of 70-80 nm on the first source region and the first drain region by using an electron beam evaporation process, and selectively etching the metal Al by using an etching process to form a first electrode;

and growing metal Al with the thickness of 70-80 nm on the second source region and the second drain region by using an electron beam evaporation process, and selectively etching the metal Al by using an etching process to form a second electrode.

5. The method of claim 3, wherein fabricating L EDs, waveguides, and detectors in the first epitaxial layer region comprises:

etching the first epitaxial layer region by using an etching process to form a third epitaxial layer;

sequentially growing a first Ge layer, a first intrinsic Ge layer, an intrinsic GeSn alloy layer, a second intrinsic Ge layer, a second Ge layer, an n-type Si layer and a second oxide layer on the third epitaxial layer;

and etching the first intrinsic Ge layer, the intrinsic GeSn alloy layer, the second intrinsic Ge layer, the second Ge layer, the n-type Si layer and the second oxide layer by using a dry etching process to form L ED, a waveguide and a detector respectively.

6. The method of claim 5, wherein sequentially growing a first Ge layer, a first intrinsic Ge layer, an intrinsic GeSn alloy layer, a second intrinsic Ge layer, a second Ge layer, an n-type Si layer, and a second oxide layer on the third epitaxial layer comprises:

growing the third epitaxial layer with the thickness of 50nm and the doping concentration of 10 by using a CVD process at the temperature of 330 DEG C²⁰cm^-3A first Ge layer of (a);

growing a first intrinsic Ge layer with the thickness of 40-50 nm on the first Ge layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃;

growing an intrinsic GeSn alloy layer with the thickness of 250nm on the first intrinsic Ge layer by utilizing a reduced pressure CVD process at the temperature of 350 ℃, wherein the Sn component is 8 percent;

growing a second intrinsic Ge layer with the thickness of 40-50 nm on the intrinsic GeSn alloy layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃;

growing a layer of 100nm thick with a doping concentration of 3 x 10 on the second intrinsic Ge layer by CVD process at 160 deg.C^#9cm^-3A second Ge layer of (a);

growing the second Ge layer by a CVD process at 275-325 ℃ to a thickness of 100nm and a doping concentration of 10²⁰cm^-3An n-type Si layer of (1);

a second oxide layer was grown on the n-type Si layer to a thickness of 10nm using L PCVD process.

7. The method of claim 1, wherein growing a stressed silicon nitride film on the NMOS device, PMOS device, waveguide, and detector comprises:

growing compressive stress silicon nitride films on the surfaces and the periphery of the PMOS device and the waveguide;

and growing tensile stress silicon nitride films on the surfaces and the periphery of the NMOS device and the detector.

8. The method of claim 7, wherein growing a compressive silicon nitride film on the surfaces and around the PMOS device and the waveguide comprises:

and growing a compressive stress silicon nitride film with the thickness of 10-20 nm on the surfaces and the periphery of the PMOS device and the waveguide by using a plasma enhanced chemical vapor deposition process at the temperature of 340-360 ℃.

9. The method of claim 7, wherein growing a tensile silicon nitride film on and around the NMOS device and the detector comprises:

and growing tensile stress silicon nitride films with the thickness of 10-20 nm on the surfaces and the periphery of the NMOS device and the detector by using a plasma enhanced chemical vapor deposition process at the temperature of 240-280 ℃.

10. A strain-based photonic integrated device prepared by the method of any of claims 1 to 9.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a strain-based optical integrated device and a preparation method thereof.

Background

A photodetector is a kind of photodetector device made by using the photoconductive effect of semiconductor materials. The photoelectric detector has wide application in various fields of military and national economy. The infrared radiation sensor is mainly used for ray measurement and detection, industrial automatic control, photometric measurement and the like in visible light or near infrared wave bands; the infrared band is mainly used for missile guidance, infrared thermal imaging, infrared remote sensing and the like.

With the development of large-scale integrated circuit technology, the feature size of devices is continuously reduced, the integration scale is larger and larger, the information processing capability is continuously enhanced, and how to realize the integration of photoelectric detection devices, namely optical devices and MOS devices, on a single chip becomes a problem to be solved urgently.

Disclosure of Invention

Therefore, in order to solve the technical defects and shortcomings of the prior art, the invention provides a strain-based optical integrated device and a preparation method thereof.

Specifically, an embodiment of the present invention provides a method for manufacturing a strain-based photonic integrated device, including:

growing a silicon epitaxial layer on a silicon substrate;

etching a first groove on the silicon epitaxial layer to form a first epitaxial layer region and a second epitaxial layer region;

etching a second groove in the second epitaxial layer region to form a first epitaxial layer sub-region and a second epitaxial layer sub-region;

respectively preparing an NMOS device and a PMOS device in the first epitaxial layer sub-region and the second epitaxial layer sub-region;

preparing L ED, waveguide and detector in the first epitaxial layer region;

and growing a stress silicon nitride film on the NMOS device, the PMOS device, the waveguide and the detector to finally form the optical integrated device based on strain.

In one embodiment of the present invention, growing a silicon epitaxial layer on a silicon substrate comprises:

selecting a silicon substrate;

growing a doped concentration on the silicon substrateDegree of 10¹⁶cm^-3P-type silicon epitaxial layer 10¹⁶cm^-3. In an embodiment of the present invention, after the second trench is etched in the second epitaxial layer region to form a first epitaxial layer sub-region and a second epitaxial layer sub-region, the method further includes:

and depositing a first oxide layer with the thickness of 10-20 nm on the first trench, the first epitaxial layer region, the first epitaxial layer sub-region, the second epitaxial layer sub-region and the second trench by using a low-temperature plasma enhanced chemical vapor deposition process at the temperature of 250-450 ℃.

In an embodiment of the present invention, the preparing an NMOS device and a PMOS device in the first epitaxial layer sub-region and the second epitaxial layer sub-region respectively includes:

performing P ion implantation on the second epitaxial layer sub-region at the temperature of 200-300 ℃ by using an ion implantation process to form a second epitaxial layer with the concentration of 10¹⁶cm^-3An n-well of (1);

performing B ion implantation on the n-well by using an ion implantation process at the temperature of 200-300 ℃ to form a doped concentration of 10²⁰cm^-3A first source region and a first drain region;

performing P ion implantation on the first epitaxial layer sub-region by using an ion implantation process at the temperature of 200-300 ℃ to form doping concentrations of 10²⁰cm^-3A second source region and a second drain region;

respectively preparing a first polysilicon gate and a second polysilicon gate with the thickness of 50-60 nm on the n well and the first oxide layer on the first epitaxial layer sub-region;

growing metal Al with the thickness of 70-80 nm on the first source region and the first drain region by using an electron beam evaporation process, and selectively etching the metal Al by using an etching process to form a first electrode;

and growing metal Al with the thickness of 70-80 nm on the second source region and the second drain region by using an electron beam evaporation process, and selectively etching the metal Al by using an etching process to form a second electrode.

In one embodiment of the present invention, fabricating L EDs, waveguides, and detectors in the first epitaxial layer region includes:

etching the first epitaxial layer region by using an etching process to form a third epitaxial layer;

sequentially growing a first Ge layer, a first intrinsic Ge layer, an intrinsic GeSn alloy layer, a second intrinsic Ge layer, a second Ge layer, an n-type Si layer and a second oxide layer on the third epitaxial layer;

and etching the first intrinsic Ge layer, the intrinsic GeSn alloy layer, the second intrinsic Ge layer, the second Ge layer, the n-type Si layer and the second oxide layer by using a dry etching process to form L ED, a waveguide and a detector respectively.

In one embodiment of the present invention, sequentially growing a first Ge layer, a first intrinsic Ge layer, an intrinsic GeSn alloy layer, a second intrinsic Ge layer, a second Ge layer, an n-type Si layer, and a second oxide layer on the third epitaxial layer includes:

growing the third epitaxial layer with the thickness of 50nm and the doping concentration of 10 by using a CVD process at the temperature of 330 DEG C²⁰cm^-3A first Ge layer of (a);

growing a first intrinsic Ge layer with the thickness of 40-50 nm on the first Ge layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃;

growing an intrinsic GeSn alloy layer with the thickness of 250nm on the first intrinsic Ge layer by utilizing a reduced pressure CVD process at the temperature of 350 ℃, wherein the Sn component is 8 percent;

growing a second intrinsic Ge layer with the thickness of 40-50 nm on the intrinsic GeSn alloy layer by using a CVD (chemical vapor deposition) process at the temperature of 275-325 ℃;

growing a layer of 100nm thick with a doping concentration of 3 x 10 on the second intrinsic Ge layer by CVD process at 160 deg.C¹⁹cm^-3A second Ge layer of (a);

growing the second Ge layer by a CVD process at 275-325 ℃ to a thickness of 100nm and a doping concentration of 10²⁰cm^-3An n-type Si layer of (1);

a second oxide layer was grown on the n-type Si layer to a thickness of 10nm using L PCVD process.

In one embodiment of the present invention, growing a stressed silicon nitride film on the NMOS device, the PMOS device, the waveguide and the detector comprises:

growing compressive stress silicon nitride films on the surfaces and the periphery of the PMOS device and the waveguide;

and growing tensile stress silicon nitride films on the surfaces and the periphery of the NMOS device and the detector. In one embodiment of the present invention, a compressive silicon nitride film is grown on the surface and around the PMOS device and the waveguide, including:

and growing a compressive stress silicon nitride film with the thickness of 10-20 nm on the surfaces and the periphery of the PMOS device and the waveguide by using a plasma enhanced chemical vapor deposition process at the temperature of 340-360 ℃. In one embodiment of the present invention, a tensile silicon nitride film is grown on the surface and around the NMOS device and the detector, including:

and growing tensile stress silicon nitride films with the thickness of 10-20 nm on the surfaces and the periphery of the NMOS device and the detector by using a plasma enhanced chemical vapor deposition process at the temperature of 240-280 ℃.

Another embodiment of the present invention provides a photonic integrated device, which is formed by the method of any of the above embodiments.

The invention has the following beneficial effects:

according to the invention, L ED, the waveguide, the detector, the NMOS device and the PMOS device are integrated on one substrate, and the optical integrated device based on strain is manufactured after stress is introduced, so that on the basis of improving the performance of the device, the device has the advantages of novel structure, good compatibility, high integration level of the device and low process cost.

Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic flow chart of a method for manufacturing a strain-based optical integrated device according to an embodiment of the present invention;

fig. 2a to fig. 2u are schematic views illustrating a process for fabricating a strain-based photonic integrated device according to an embodiment of the present invention;

FIG. 3a is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 2n according to an embodiment of the present invention;

FIG. 3b is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 2o according to an embodiment of the present invention;

FIG. 3c is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 2p according to an embodiment of the present invention;

FIG. 3d is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 2q according to an embodiment of the present invention;

FIG. 3e is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 2r according to an embodiment of the present invention;

FIG. 3f is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 2s according to an embodiment of the present invention;

FIG. 3g is a top view of a device formed by the strain-based optical integrated device manufacturing process shown in FIG. 2t according to an embodiment of the present invention;

FIG. 3h is a top view of a device formed by the strain-based photonic integrated device manufacturing process shown in FIG. 2u according to an embodiment of the present invention;

FIGS. 4 a-4 c are schematic top views of three tapered waveguides provided in accordance with embodiments of the present invention;

FIG. 5 is a schematic diagram of transmittance at different wavelengths of three types of tapered waveguides, a linear type waveguide, a convex type waveguide, and a concave type waveguide, according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the transmittance of a tapered waveguide at three lengths of 5 μm, 10 μm, and 15 μm for different wavelengths according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the transmittance of the isolation layer at different thicknesses according to an embodiment of the present invention;

FIG. 8 is a graph illustrating the transmittance of a cover layer at different wavelengths according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a strain-based optoelectronic integrated device according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.