阅读说明：本技术 单片光电集成电路及其形成方法 (Monolithic optoelectronic integrated circuit and method of forming the same ) 是由 王永进 严嘉彬 朴金龙 于 2020-02-25 设计创作，主要内容包括：本发明涉及一种单片光电集成电路及其形成方法。所述单片光电集成电路包括：衬底,包括光子集成器件区域和外围电路区域；第一GaN基多量子阱光电PN结器件,位于光子集成器件区域,用作发光二极管,包括第一P-型欧姆接触电极和第一N-型欧姆接触电极；第一GaN基场效应晶体管,位于外围电路区域,包括具有第一凹槽的第一栅极介质层、填充于第一凹槽中的第一栅极、以及第一源极和第一漏极；第一源极电连接第一P-型欧姆接触电极,第一漏极用于与第一电位电连接,第一N-型欧姆接触电极用于与低于第一电位的第二电位电连接,第一栅极电连接控制端口,以控制发光二极管的亮灭。本发明制备的单片光电集成电路具有高性能,且能够有效降低其加工难度。(The invention relates to a monolithic optoelectronic integrated circuit and a method of forming the same. The monolithic optoelectronic integrated circuit includes: a substrate including a photonic integrated device region and a peripheral circuit region; the first GaN-based multi-quantum well photoelectric PN junction device is positioned in the photonic integrated device region, is used as a light emitting diode and comprises a first P-type ohmic contact electrode and a first N-type ohmic contact electrode; the first GaN-based field effect transistor is positioned in the peripheral circuit region and comprises a first grid dielectric layer with a first groove, a first grid filled in the first groove, a first source electrode and a first drain electrode; the first source electrode is electrically connected with the first P-type ohmic contact electrode, the first drain electrode is electrically connected with a first potential, the first N-type ohmic contact electrode is electrically connected with a second potential lower than the first potential, and the first grid electrode is electrically connected with the control port to control the on and off of the light-emitting diode. The monolithic photoelectric integrated circuit prepared by the invention has high performance and can effectively reduce the processing difficulty.)

1. A monolithic optoelectronic integrated circuit, comprising:

a substrate including a photonic integrated device region and a peripheral circuit region;

the first GaN-based multi-quantum well photoelectric PN junction device is positioned in the photonic integrated device region on the surface of the substrate, is used as a light emitting diode in a monolithic photoelectric integrated circuit and comprises a first P-type ohmic contact electrode and a first N-type ohmic contact electrode;

the first GaN-based field effect transistor is positioned in a peripheral circuit region on the surface of the substrate and comprises a first grid dielectric layer which is positioned on the surface of the substrate and is provided with a first groove, a first grid which is filled in the first groove, and a first source electrode and a first drain electrode which are positioned on two opposite sides of the first grid;

the first source electrode is electrically connected with the first P-type ohmic contact electrode, the first drain electrode is used for being electrically connected with a first potential, the first N-type ohmic contact electrode is used for being electrically connected with a second potential lower than the first potential, and the first grid electrode is electrically connected with a control port so as to control the on and off of the light emitting diode.

2. The monolithic optoelectronic integrated circuit of claim 1, further comprising:

the second GaN-based multiple quantum well photoelectric PN junction device is positioned in the photonic integrated device region on the surface of the substrate, is used as a photoelectric detector in the monolithic photoelectric integrated circuit, comprises a second P-type ohmic contact electrode and a second N-type ohmic contact electrode, and is connected with the first GaN-based multiple quantum well photoelectric PN junction device through an optical waveguide;

the resistor is positioned in a peripheral circuit area on the surface of the substrate;

the second GaN-based field effect transistor is positioned in a peripheral circuit region on the surface of the substrate and comprises a second grid dielectric layer which is positioned on the surface of the substrate and is provided with a second groove, a second grid which is filled in the second groove, and a second source electrode and a second drain electrode which are positioned on two opposite sides of the second grid;

one end of the resistor is electrically connected with the second N-type ohmic contact electrode, the other end of the resistor is used for being electrically connected with a third potential, the second P-type ohmic contact electrode is used for being electrically connected with a fourth potential lower than the third potential, and the potential between the second N-type ohmic contact electrode and the resistor is electrically connected with the second grid so as to control whether the second GaN-based field effect transistor is conducted or not.

3. The monolithic optoelectronic integrated circuit of claim 2, wherein the substrate surface further comprises an AlGaN buffer layer, and an undoped GaN layer on a surface of the AlGaN buffer layer; the monolithic optoelectronic integrated circuit further comprises a cavity penetrating through the AlGaN buffer layer and the undoped GaN layer from the substrate, the optical waveguide is of a GaN clamped beam structure suspended above the cavity, and the first GaN-based multiple quantum well photoelectric PN junction device and the second GaN-based multiple quantum well photoelectric PN junction device are formed on the surface of the undoped GaN layer and are suspended above the cavity.

4. The monolithic optoelectronic integrated circuit of claim 3, wherein the first GaN-based multiple quantum well optoelectronic PN junction device further comprises a first N-type GaN epitaxial layer, a first InGaN/GaN multiple quantum well layer, and a first P-type GaN epitaxial layer sequentially stacked in a direction perpendicular to the substrate, and the second GaN-based multiple quantum well optoelectronic PN junction device further comprises a second N-type GaN epitaxial layer, a second InGaN/GaN multiple quantum well layer, and a second P-type GaN epitaxial layer sequentially stacked in a direction perpendicular to the substrate;

in the peripheral circuit region, the semiconductor device further comprises a third N-type GaN epitaxial layer arranged on the surface of the undoped GaN layer, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all arranged on the surface of the third N-type GaN epitaxial layer;

the third N-type GaN epitaxial layer is provided with a first through hole and a second through hole which expose the undoped GaN layer, the first grid dielectric layer covers the inner wall of the first through hole and part of the surface of the third N-type GaN epitaxial layer, and the second grid dielectric layer covers the inner wall of the second through hole and part of the surface of the third N-type GaN epitaxial layer.

5. The monolithic optoelectronic integrated circuit of claim 3, further comprising:

an isolation trench penetrating the undoped GaN layer and the AlGaN buffer layer and exposing the substrate, the isolation trench for isolating the photonic integrated device region and the peripheral circuit region.

6. The monolithic optoelectronic integrated circuit as recited in claim 2, wherein the first P-type ohmic contact electrode has a circular cross-section in a direction parallel to the substrate, and the first N-type ohmic contact electrode has an arc-shaped cross-section disposed around an outer periphery of the first P-type ohmic contact electrode;

and in the direction parallel to the substrate, the section of the second P-type ohmic contact electrode is circular, and the section of the second N-type ohmic contact electrode is arranged around the periphery of the second P-type ohmic contact electrode in an arc shape.

7. The monolithic optoelectronic integrated circuit of claim 2, wherein the resistor comprises:

two resistance electrodes located on the surface of the substrate;

and the resistance arms are positioned on the surface of the substrate, and two ends of each resistance arm are electrically connected with the two resistance electrodes in a one-to-one correspondence manner.

8. A method of forming a monolithic optoelectronic integrated circuit according to any one of claims 1 to 7, comprising the steps of:

providing a substrate, and defining a photonic integrated device region and a peripheral circuit region on the surface of the substrate;

forming a first GaN-based multiple quantum well photoelectric PN junction device in the photonic integrated device region on the surface of the substrate and used as a light emitting diode in a monolithic photoelectric integrated circuit, wherein the first GaN-based multiple quantum well photoelectric PN junction device comprises a first P-type ohmic contact electrode and a first N-type ohmic contact electrode;

forming a first GaN-based field effect transistor in a peripheral circuit region on the surface of the substrate, wherein the first GaN-based field effect transistor comprises a first grid dielectric layer which is positioned on the surface of the substrate and is provided with a first groove, a first grid which is filled in the first groove, and a first source electrode and a first drain electrode which are positioned on two opposite sides of the first grid;

and the first source electrode, the first P-type ohmic contact electrode, the first drain electrode, the first potential, the first N-type ohmic contact electrode, the second potential lower than the first potential, the first grid electrode and the control port are electrically connected so as to control the on and off of the light-emitting diode.

9. The method of forming a monolithic optoelectronic integrated circuit according to claim 8, further comprising the steps of:

forming a second GaN-based multiple quantum well photovoltaic PN junction device in the photonic integrated device region on the surface of the substrate, wherein the second GaN-based multiple quantum well photovoltaic PN junction device is used as a photodetector in the monolithic photovoltaic integrated circuit and comprises a second P-type ohmic contact electrode and a second N-type ohmic contact electrode;

connecting the first GaN-based multiple quantum well photoelectric PN junction device with the second GaN-based multiple quantum well photoelectric PN junction device through an optical waveguide;

forming a second GaN-based field effect transistor in a peripheral circuit region on the surface of the substrate, wherein the second GaN-based field effect transistor comprises a second grid dielectric layer which is positioned on the surface of the substrate and is provided with a second groove, a second grid which is filled in the second groove, and a second source electrode and a second drain electrode which are positioned on two opposite sides of the second grid;

forming a resistor in a peripheral circuit area on the surface of the substrate;

one end of the resistor is electrically connected with the second N-type ohmic contact electrode, the other end of the resistor is electrically connected with a third potential, the second P-type ohmic contact electrode is electrically connected with a fourth potential lower than the third potential, and meanwhile, the potential between the second N-type ohmic contact electrode and the resistor is electrically connected with the second grid electrode so as to control whether the second GaN-based field effect transistor is conducted or not.

10. The method of forming a monolithic optoelectronic integrated circuit according to claim 9, further comprising the steps of:

forming an AlGaN buffer layer and an undoped GaN layer positioned on the surface of the AlGaN buffer layer on the surface of the substrate;

depositing an N-type GaN material on the surface of the doped GaN layer to form an N-type GaN material layer;

etching the N-type GaN material layer, and simultaneously forming a first N-type GaN epitaxial layer of the first GaN-based multiple quantum well photoelectric PN junction device, a second N-type GaN epitaxial layer of the second GaN-based multiple quantum well photoelectric PN junction device and a third N-type GaN epitaxial layer located in the peripheral circuit region;

etching the third N-type GaN epitaxial layer to form a first through hole and a second through hole which expose the undoped GaN layer;

and forming a first grid dielectric layer covering the inner wall of the first through hole and part of the surface of the third N-type GaN epitaxial layer, and simultaneously forming a second grid dielectric layer covering the inner wall of the second through hole and part of the surface of the third N-type GaN epitaxial layer.

Technical Field

The invention relates to the technical field of integrated photoelectronics, in particular to a monolithic optoelectronic integrated circuit and a forming method thereof.

Background

The photoelectric monolithic integrated circuit is an important direction for future communication and information technology development, and compared with the traditional off-chip interconnection mode, the monolithic photoelectric integrated circuit has the advantages of small area, high reliability, low noise, high speed, strong anti-interference capability and the like. With advances in material science and manufacturing technology, it has become possible to integrate optical, optoelectronic and electronic components on monolithic substrates. However, current monolithic optoelectronic integrated circuits suffer from a number of deficiencies in electrical performance, manufacturing process, and structural complexity.

Therefore, how to improve the performance of the monolithic optoelectronic integrated circuit, reduce the manufacturing complexity of the monolithic optoelectronic integrated circuit, and simplify the structure of the monolithic optoelectronic integrated circuit is a technical problem to be solved.

Disclosure of Invention

The invention provides a monolithic photoelectric integrated circuit and a forming method thereof, which are used for solving the problem of poor performance of the conventional monolithic photoelectric integrated circuit.

In order to solve the above problems, the present invention provides a monolithic optoelectronic integrated circuit comprising:

a substrate including a photonic integrated device region and a peripheral circuit region;

the first GaN-based multi-quantum well photoelectric PN junction device is positioned in the photonic integrated device region on the surface of the substrate, is used as a light emitting diode in a monolithic photoelectric integrated circuit and comprises a first P-type ohmic contact electrode and a first N-type ohmic contact electrode;

the first GaN-based field effect transistor is positioned in a peripheral circuit region on the surface of the substrate and comprises a first grid dielectric layer which is positioned on the surface of the substrate and is provided with a first groove, a first grid which is filled in the first groove, and a first source electrode and a first drain electrode which are positioned on two opposite sides of the first grid;

the first source electrode is electrically connected with the first P-type ohmic contact electrode, the first drain electrode is used for being electrically connected with a first potential, the first N-type ohmic contact electrode is used for being electrically connected with a second potential lower than the first potential, and the first grid electrode is electrically connected with a control port so as to control the on and off of the light emitting diode.

Optionally, the method further includes:

the second GaN-based multiple quantum well photoelectric PN junction device is positioned in the photonic integrated device region on the surface of the substrate, is used as a photoelectric detector in the monolithic photoelectric integrated circuit, comprises a second P-type ohmic contact electrode and a second N-type ohmic contact electrode, and is connected with the first GaN-based multiple quantum well photoelectric PN junction device through an optical waveguide;

the resistor is positioned in a peripheral circuit area on the surface of the substrate;

the second GaN-based field effect transistor is positioned in a peripheral circuit region on the surface of the substrate and comprises a second grid dielectric layer which is positioned on the surface of the substrate and is provided with a second groove, a second grid which is filled in the second groove, and a second source electrode and a second drain electrode which are positioned on two opposite sides of the second grid;

one end of the resistor is electrically connected with the second N-type ohmic contact electrode, the other end of the resistor is used for being electrically connected with a third potential, the second P-type ohmic contact electrode is used for being electrically connected with a fourth potential lower than the third potential, and the potential between the second N-type ohmic contact electrode and the resistor is electrically connected with the second grid so as to control whether the second GaN-based field effect transistor is conducted or not.

Optionally, the substrate surface further includes an AlGaN buffer layer and an undoped GaN layer located on the surface of the AlGaN buffer layer;

the monolithic optoelectronic integrated circuit further comprises a cavity penetrating through the AlGaN buffer layer and the undoped GaN layer from the substrate, the optical waveguide is of a GaN clamped beam structure suspended above the cavity, and the first GaN-based multiple quantum well photoelectric PN junction device and the second GaN-based multiple quantum well photoelectric PN junction device are formed on the surface of the undoped GaN layer and are suspended above the cavity.

Optionally, the first GaN-based multiple quantum well photoelectric PN junction device further includes a first N-type GaN epitaxial layer, a first InGaN/GaN multiple quantum well layer, and a first P-type GaN epitaxial layer that are sequentially stacked in a direction perpendicular to the substrate, and the second GaN-based multiple quantum well photoelectric PN junction device further includes a second N-type GaN epitaxial layer, a second InGaN/GaN multiple quantum well layer, and a second P-type GaN epitaxial layer that are sequentially stacked in a direction perpendicular to the substrate;

in the peripheral circuit region, the semiconductor device further comprises a third N-type GaN epitaxial layer arranged on the surface of the undoped GaN layer, and the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all arranged on the surface of the third N-type GaN epitaxial layer;

the third N-type GaN epitaxial layer is provided with a first through hole and a second through hole which expose the undoped GaN layer, the first grid dielectric layer covers the inner wall of the first through hole and part of the surface of the third N-type GaN epitaxial layer, and the second grid dielectric layer covers the inner wall of the second through hole and part of the surface of the third N-type GaN epitaxial layer.

Optionally, the method further includes:

an isolation trench penetrating the undoped GaN layer and the AlGaN buffer layer and exposing the substrate, the isolation trench for isolating the photonic integrated device region and the peripheral circuit region.

Optionally, in a direction parallel to the substrate, a cross section of the first P-type ohmic contact electrode is circular, and a cross section of the first N-type ohmic contact electrode is arranged around an outer periphery of the first P-type ohmic contact electrode in an arc shape;

and in the direction parallel to the substrate, the section of the second P-type ohmic contact electrode is circular, and the section of the second N-type ohmic contact electrode is arranged around the periphery of the second P-type ohmic contact electrode in an arc shape.

Optionally, the resistor includes:

two resistance electrodes located on the surface of the substrate;

and the resistance arms are positioned on the surface of the substrate, and two ends of each resistance arm are electrically connected with the two resistance electrodes in a one-to-one correspondence manner.

In order to solve the above problem, the present invention further provides a method for forming a monolithic optoelectronic integrated circuit as described in any one of the above, including the steps of:

providing a substrate, and defining a photonic integrated device region and a peripheral circuit region on the surface of the substrate;

forming a first GaN-based multiple quantum well photoelectric PN junction device in the photonic integrated device region on the surface of the substrate and used as a light emitting diode in a monolithic photoelectric integrated circuit, wherein the first GaN-based multiple quantum well photoelectric PN junction device comprises a first P-type ohmic contact electrode and a first N-type ohmic contact electrode;

forming a first GaN-based field effect transistor in a peripheral circuit region on the surface of the substrate, wherein the first GaN-based field effect transistor comprises a first grid dielectric layer which is positioned on the surface of the substrate and is provided with a first groove, a first grid which is filled in the first groove, and a first source electrode and a first drain electrode which are positioned on two opposite sides of the first grid;

and the first source electrode, the first P-type ohmic contact electrode, the first drain electrode, the first potential, the first N-type ohmic contact electrode, the second potential lower than the first potential, the first grid electrode and the control port are electrically connected so as to control the on and off of the light-emitting diode.

Optionally, the method further comprises the following steps:

forming a second GaN-based multiple quantum well photovoltaic PN junction device in the photonic integrated device region on the surface of the substrate, wherein the second GaN-based multiple quantum well photovoltaic PN junction device is used as a photodetector in the monolithic photovoltaic integrated circuit and comprises a second P-type ohmic contact electrode and a second N-type ohmic contact electrode;

connecting the first GaN-based multiple quantum well photoelectric PN junction device with the second GaN-based multiple quantum well photoelectric PN junction device through an optical waveguide;

forming a second GaN-based field effect transistor in a peripheral circuit region on the surface of the substrate, wherein the second GaN-based field effect transistor comprises a second grid dielectric layer which is positioned on the surface of the substrate and is provided with a second groove, a second grid which is filled in the second groove, and a second source electrode and a second drain electrode which are positioned on two opposite sides of the second grid;

forming a resistor in a peripheral circuit area on the surface of the substrate;

one end of the resistor is electrically connected with the second N-type ohmic contact electrode, the other end of the resistor is electrically connected with a third potential, the second P-type ohmic contact electrode is electrically connected with a fourth potential lower than the third potential, and meanwhile, the potential between the second N-type ohmic contact electrode and the resistor is electrically connected with the second grid electrode so as to control whether the second GaN-based field effect transistor is conducted or not.

Optionally, the method further comprises the following steps:

forming an AlGaN buffer layer and an undoped GaN layer positioned on the surface of the AlGaN buffer layer on the surface of the substrate;

depositing an N-type GaN material on the surface of the doped GaN layer to form an N-type GaN material layer;

etching the N-type GaN material layer, and simultaneously forming a first N-type GaN epitaxial layer of the first GaN-based multiple quantum well photoelectric PN junction device, a second N-type GaN epitaxial layer of the second GaN-based multiple quantum well photoelectric PN junction device and a third N-type GaN epitaxial layer located in the peripheral circuit region;

etching the third N-type GaN epitaxial layer to form a first through hole and a second through hole which expose the undoped GaN layer;

and forming a first grid dielectric layer covering the inner wall of the first through hole and part of the surface of the third N-type GaN epitaxial layer, and simultaneously forming a second grid dielectric layer covering the inner wall of the second through hole and part of the surface of the third N-type GaN epitaxial layer.

On one hand, the first GaN-based multiple quantum well photoelectric PN junction device and the first GaN-based field effect transistor are integrated on the surface of the same substrate, and the first GaN-based multiple quantum well photoelectric PN junction device and the first GaN-based field effect transistor in the prepared monolithic photoelectric integrated circuit have high performance by utilizing the excellent characteristics of high electron mobility, high thermal conductivity, high temperature resistance, corrosion resistance, radiation resistance and the like of a GaN material; on the other hand, the first GaN-based field effect transistor provided by the invention does not need to introduce the growth of epitaxial materials in the preparation and processing process by using a complex ion implantation technology, and is completely compatible with the preparation process of the first GaN-based multi-quantum-well photoelectric PN junction device, so that the processing difficulty of a single-chip photoelectric integrated circuit is effectively reduced.

Drawings

FIG. 1 is a schematic diagram of the overall structure of a monolithic optoelectronic integrated circuit according to an embodiment of the present invention;

FIG. 2 is a schematic sectional view taken along A-A' of FIG. 1;

FIG. 3 is a schematic structural view of a first GaN-based field effect transistor in accordance with an embodiment of the invention;

FIG. 4 is a schematic cross-sectional view taken along line B-B' of FIG. 3;

FIG. 5 is a schematic diagram of a resistor according to an embodiment of the present invention;

FIG. 6 is a flow chart of a method for forming a monolithic optoelectronic integrated circuit in accordance with an embodiment of the present invention.

Detailed Description

The following describes in detail a specific embodiment of the monolithic optoelectronic integrated circuit and the method for forming the same according to the present invention with reference to the drawings.

The present embodiment provides a monolithic optoelectronic integrated circuit, wherein fig. 1 is a schematic structural diagram of the monolithic optoelectronic integrated circuit in the embodiment of the present invention, fig. 2 is a schematic sectional diagram of fig. 1 along a direction a-a ', fig. 3 is a schematic structural diagram of a first GaN-based field effect transistor in the embodiment of the present invention, and fig. 4 is a schematic sectional diagram of fig. 3 along a direction B-B'. As shown in fig. 1 to 4, the monolithic optoelectronic integrated circuit provided in the present embodiment includes:

a substrate 10 including a photonic integrated device region 1 and a peripheral circuit region 2;

the first GaN-based multiple quantum well photoelectric PN junction device 11 is positioned in the photonic integrated device region 1 on the surface of the substrate 10 and used as a light emitting diode in a monolithic photoelectric integrated circuit, and comprises a first P-type ohmic contact electrode 111 and a first N-type ohmic contact electrode 112;

the first GaN-based field effect transistor 21 is positioned in the peripheral circuit region 2 on the surface of the substrate 10, and the first GaN-based field effect transistor 21 comprises a first gate dielectric layer 31 which is positioned on the surface of the substrate 10 and is provided with a first groove, a first gate 211 filled in the first groove, and a first source electrode 212 and a first drain electrode 213 which are positioned on two opposite sides of the first gate 211;

the first source electrode 212 is electrically connected to the first P-type ohmic contact electrode 111, and the first drain electrode 213 is connected to a first potential V_DD1Electrically connected to the first N-type ohmic contact electrode 112 at a potential lower than the first potential V_DD1Second potential V of_SS1And the first grid 211 is electrically connected with the control port 24 to control the on and off of the light emitting diode.

Specifically, the substrate 10 may be a silicon substrate or a sapphire substrate. The first GaN-based multiple quantum well photoelectric PN junction device and the first GaN-based field effect transistor 21 are epitaxially grown on the surface of the substrate 10. The first GaN-based multiple quantum well photoelectric PN junction device 11 is used as a light emitting diode in the monolithic photoelectric integrated circuit, and is used for transmitting a visible light signal with multimedia information to the outside. The first source electrode 212 is electrically connected to the first P-type ohmic contact electrode 111, and the first drain electrode 213 is connected to a first potential V_DD1(i.e., high potential) electrical connection, the first N-type ohmic contact electrode 112 for connecting with a second potential V lower than the first potential_SS1The first gate 211 is electrically connected to the control port 24 (i.e., a low potential) to control the on/off of the led. The first isThe material of the first gate electrode 211 in the GaN-based field effect transistor 21 may be the same as that of the first P-type ohmic contact electrode 111, for example, both Ni and/or Au. The material of the first source electrode 212 and the first drain electrode 213 may be the same as the material of the first N-type ohmic contact electrode 112, for example, both Ti and/or Al.

Optionally, the monolithic optoelectronic integrated circuit further includes:

a second GaN-based multiple quantum well photovoltaic PN junction device 12 located in the photonic integrated device region 1 on the surface of the substrate 10, serving as a photodetector in the monolithic optoelectronic integrated circuit, and including a second P-type ohmic contact electrode 121 and a second N-type ohmic contact electrode 122, wherein the second GaN-based multiple quantum well photovoltaic PN junction device 12 and the first GaN-based multiple quantum well photovoltaic PN junction device 11 are connected by an optical waveguide 13;

a resistor 23 located in the peripheral circuit region 2 on the surface of the substrate 10;

the second GaN-based field effect transistor 22 is positioned in the peripheral circuit region 2 on the surface of the substrate 10, and the second GaN-based field effect transistor 22 comprises a second gate dielectric layer which is positioned on the surface of the substrate 10 and is provided with a second groove, a second gate 221 which is filled in the second groove, and a second source 222 and a second drain 223 which are positioned on two opposite sides of the second gate 221;

one end of the resistor 23 is electrically connected to the second N-type ohmic contact electrode 122, and the other end is used for connecting with a third potential V_DD2Electrically connected to the second P-type ohmic contact electrode 121 for being lower than the third potential V_DD2Fourth potential V of_SS2And the potential between the second N-type ohmic contact electrode 122 and the resistor 23 is electrically connected to the second gate electrode 221 to control the conduction or non-conduction of the second GaN-based field effect transistor 22.

Specifically, the second GaN-based multiple quantum well PN junction device 12 is used as a photodetector in the monolithic optoelectronic integrated circuit, so that light can be transmitted between the first GaN-based multiple quantum well PN junction device 11 and the second GaN-based multiple quantum well PN junction device 12 through the optical waveguide 13And connecting the circuits to perform visible light communication. One end of the resistor 23 is electrically connected to the second N-type ohmic contact electrode 122, and the other end is connected to a third potential V_DD2(i.e., high potential), the second P-type ohmic contact electrode 121 is connected to a fourth potential V_SS2(i.e., low potential). The potential between the second N-type ohmic contact electrode 122 and the resistor 23 is electrically connected to the second gate 221 to control the second GaN-based field effect transistor 22 to be turned on and off to further realize the output of the signal. The second drain 223 is connected to a fifth potential V_DD3(i.e., high potential), the second source 222 is lower than the fifth potential V_DD3A sixth potential V of_SS3(i.e., low potential).

Optionally, the surface of the substrate 10 further includes an AlGaN buffer layer 14, and an undoped GaN layer 15 located on the surface of the AlGaN buffer layer 14;

the monolithic optoelectronic integrated circuit further comprises a cavity 16 which penetrates through the AlGaN buffer layer 14 and the undoped GaN layer 15 from the substrate 10, the optical waveguide 13 is a GaN clamped beam structure suspended above the cavity 16, and the first GaN-based multiple quantum well photoelectric PN junction device 11 and the second GaN-based multiple quantum well photoelectric PN junction device 12 are formed on the surface of the undoped GaN layer 15 and suspended above the cavity 16.

Optionally, the first GaN-based multiple quantum well photovoltaic PN junction device 11 further includes a first N-type GaN epitaxial layer 113, a first InGaN/GaN multiple quantum well layer 115, and a first P-type GaN epitaxial layer 114, which are sequentially stacked in a direction perpendicular to the substrate 10, and the second GaN-based multiple quantum well photovoltaic PN junction device 12 further includes a second N-type GaN epitaxial layer 123, a second InGaN/GaN multiple quantum well layer 125, and a second P-type GaN epitaxial layer 124, which are sequentially stacked in a direction perpendicular to the substrate 10;

in the peripheral circuit region 2, a third N-type GaN epitaxial layer 32 is further included, the third N-type GaN epitaxial layer 32 is disposed on the surface of the undoped GaN layer 15, and the first source electrode 212, the first drain electrode 213, the second source electrode 222 and the second drain electrode 223 are disposed on the surface of the third N-type GaN epitaxial layer 32;

the third N-type GaN epitaxial layer 32 has a first through hole and a second through hole exposing the undoped GaN layer 15, the first gate dielectric layer 31 covers the inner wall of the first through hole and a part of the surface of the third N-type GaN epitaxial layer 32, and the second gate dielectric layer covers the inner wall of the second through hole and a part of the surface of the third N-type GaN epitaxial layer 32.

Specifically, the first GaN-based multiple quantum well PN junction device 11 and the second GaN-based multiple quantum well PN junction device 12 are symmetrically arranged, that is, the first GaN-based multiple quantum well PN junction device 11 and the second GaN-based multiple quantum well PN junction device 12 have the same structure, so that the first GaN-based multiple quantum well PN junction device 11 and the second GaN-based multiple quantum well PN junction device 12 can be synchronously formed. The cavity 16 sequentially penetrates through the substrate 10, the AlGaN buffer layer 14 and the undoped GaN layer 15 from the bottom surface of the substrate 10, so that the first GaN-based mqw-well PN junction device 11, the second GaN-based mqw-well PN junction device 12 and the optical waveguide 13 are all suspended above the cavity 16. The work function of the first P-type ohmic contact electrode 111 is greater than that of the first P-type GaN epitaxial layer 114, and the work function of the second P-type ohmic contact electrode 121 is greater than that of the second P-type GaN epitaxial layer 124, so that a hole accumulation layer can be formed on one semiconductor side respectively. The work function of the first N-type ohmic contact electrode 112 is smaller than that of the first N-type GaN epitaxial layer 113, and the work function of the second N-type ohmic contact electrode 122 is smaller than that of the second N-type GaN epitaxial layer 124, so that an electron accumulation layer can be formed on one semiconductor side, respectively.

The first GaN-based field effect transistor 21 and the second GaN-based field effect transistor 22 may also have the same structure. The first GaN-based field effect transistor 21 will be described below as an example. The first gate 211 is located between the first source 212 and the first drain 213. The third N-type GaN epitaxial layer 32 in the peripheral circuit region 2 has a first through hole exposing the undoped GaN layer 15, and a dielectric material completely covers the sidewall and the bottom wall of the first through hole to form the first gate dielectric layer 31 having a groove structure, so that the first gate 211 is electrically insulated from the GaN material therebelow, and a carrier channel therebelow can be controlled by a voltage applied to the gate 211. In this embodiment, the first GaN-based field effect transistor 21 may adopt a combination structure of one or more of a cascode, a common source, or a common drain, so as to further improve the output performance of the first GaN-based field effect transistor and further reduce the device size. The third N-type GaN epitaxial layer 32 may be formed simultaneously with the first N-type GaN epitaxial layer 113 and the second N-type GaN epitaxial layer 123, so as to further simplify the manufacturing process of the monolithic optoelectronic integrated circuit and reduce the manufacturing cost.

In order to avoid mutual interference between the manufacturing process and the electrical performance, optionally, the monolithic optoelectronic integrated circuit further includes:

an isolation groove penetrating the undoped GaN layer 15 and the AlGaN buffer layer 14 and exposing the substrate, the isolation groove for isolating the photonic integrated device region 1 and the peripheral circuit region 2.

Optionally, in a direction parallel to the substrate 10, a cross section of the first P-type ohmic contact electrode 111 is circular, and a cross section of the first N-type ohmic contact electrode 112 is arranged around an outer circumference of the first P-type ohmic contact electrode 111 in an arc shape;

in a direction parallel to the substrate 10, the cross section of the second P-type ohmic contact electrode 121 is circular, and the cross section of the second N-type ohmic contact electrode 122 is disposed around the outer circumference of the second P-type ohmic contact electrode 121 in an arc shape.

Specifically, the first P-type ohmic contact electrode 111 and the second P-type ohmic contact electrode 121 may have the same structure, and the first N-type ohmic contact electrode 112 and the second N-type ohmic contact electrode 122 may have the same structure. Taking the first P-type ohmic contact electrode 111 and the first N-type ohmic contact electrode 112 as an example, the cross section of the first P-type ohmic contact electrode 111 is circular, and the cross section of the first N-type ohmic contact electrode 112 is in the shape of an open-loop ring and is disposed around the periphery of the first P-type ohmic contact electrode 111.

The resistor 23 may be in the form of an N-type GaN thin film resistor, or an active resistor of the second GaN-based field effect transistor 22, and those skilled in the art can select the resistor according to actual needs. Fig. 5 is a schematic diagram of the structure of a resistor according to an embodiment of the present invention. Optionally, as shown in fig. 5, the resistor 23 includes:

two resistance electrodes 232 on the surface of the substrate 10;

and the resistance arms 231 are positioned on the surface of the substrate 10, and two ends of the resistance arms 231 are electrically connected with the two resistance electrodes 232 in a one-to-one correspondence manner.

Specifically, as shown in fig. 5, the resistor 23 is in the form of an N-type GaN thin film resistor, and includes the resistor arm 231 laid flat in a bent shape, and the resistor electrode 232 connected to an end portion of the resistor arm.

Furthermore, the present embodiment provides a method for forming a monolithic optoelectronic integrated circuit as described in any one of the above embodiments. Fig. 6 is a flowchart of a method for forming a monolithic optoelectronic integrated circuit according to an embodiment of the present invention, and the structure of the monolithic optoelectronic integrated circuit formed according to the embodiment can be seen in fig. 1 to 5. As shown in fig. 6, the method for forming a monolithic optoelectronic integrated circuit according to this embodiment includes the following steps:

step S61, providing a substrate 10, and defining a photonic integrated device region 1 and a peripheral circuit region 2 on the surface of the substrate 10;

step S62, forming a first GaN-based multiple quantum well photovoltaic PN junction device 11 on the photonic integrated device region 1 on the surface of the substrate 10, where the first GaN-based multiple quantum well photovoltaic PN junction device 11 is used as a light emitting diode in a monolithic photovoltaic integrated circuit, and the first GaN-based multiple quantum well photovoltaic PN junction device 11 includes a first P-type ohmic contact electrode 111 and a first N-type ohmic contact electrode 112;

forming a first GaN-based field effect transistor 21 in the peripheral circuit region 2 on the surface of the substrate 10, wherein the first GaN-based field effect transistor 21 comprises a first gate dielectric layer 31 located on the surface of the substrate 10 and having a first groove, a first gate 211 filled in the first groove, and a first source 212 and a first drain 213 located on two opposite sides of the first gate 211;

electrically connecting the first source electrode 212 and the first P-type ohmic contact electrode 111, the first drain electrode 213 and a first potential V_DD1The first N-type ohmic contact electrode 112 and a potential V lower than the first potential_DD1Second potential V of_SS1The first gate 211 and the control port 24 are used for controlling the on/off of the light emitting diode.

Optionally, the method for forming the monolithic optoelectronic integrated circuit further includes the following steps:

forming a second GaN-based multiple quantum well photovoltaic PN junction device 12 on said photonic integrated device region 1 on the surface of said substrate 10 for use as a photodetector in said monolithic optoelectronic integrated circuit, said second GaN-based multiple quantum well photovoltaic PN junction device 12 comprising a second P-type ohmic contact electrode 121 and a second N-type ohmic contact electrode 122;

the first GaN-based multiple quantum well photoelectric PN junction device 11 and the second GaN-based multiple quantum well photoelectric PN junction device 12 are connected through an optical waveguide 13;

forming a second GaN-based field effect transistor 22 in the peripheral circuit region 2 on the surface of the substrate 10, wherein the second GaN-based field effect transistor 22 includes a second gate dielectric layer located on the surface of the substrate 10 and having a second groove, a second gate 221 filled in the second groove, and a second source 222 and a second drain 223 located on opposite sides of the second gate 221;

forming a resistor 23 on the peripheral circuit region 2 on the surface of the substrate 10;

one end of the resistor 23 is electrically connected to the second N-type ohmic contact electrode 122, and the other end is connected to a third potential V_DD2And the second P-type ohmic contact electrode 121 is lower than the third potential V_DD2Fourth potential V of_SS2And simultaneously, the electric potential between the second N-type ohmic contact electrode 122 and the resistor 23 is electrically connected to the second gate electrode 221 to control the conduction or non-conduction of the second GaN-based field effect transistor 22.

Optionally, the method for forming the monolithic optoelectronic integrated circuit further includes the following steps:

forming an AlGaN buffer layer 14 and an undoped GaN layer 15 on a surface of the AlGaN buffer layer 14 on a surface of the substrate 10;

depositing an N-type GaN material on the surface of the doped GaN layer 15 to form an N-type GaN material layer;

etching the N-type GaN material layer, and simultaneously forming a first N-type GaN epitaxial layer 113 of the first GaN-based multiple quantum well photoelectric PN junction device 11, a second N-type GaN epitaxial layer 123 of the second GaN-based multiple quantum well photoelectric PN junction device 12 and a third N-type GaN epitaxial layer 32 positioned in the peripheral circuit region 2;

etching the third N-type GaN epitaxial layer 32 to form a first through hole and a second through hole exposing the undoped GaN layer 15;

and forming a first grid dielectric layer 31 covering the inner wall of the first through hole and part of the surface of the third N-type GaN epitaxial layer 32, and simultaneously forming a second grid dielectric layer covering the inner wall of the second through hole and part of the surface of the third N-type GaN epitaxial layer 32.

The method of forming the monolithic optoelectronic integrated circuit is illustrated below. Referring to fig. 1 to 5, the method for forming the monolithic optoelectronic integrated circuit specifically includes the following steps:

1. selecting a silicon-based or sapphire-based gallium nitride epitaxial wafer as a substrate, and forming a substrate 2, and an AlGaN buffer layer 14, an undoped GaN layer 15, an N-type GaN material layer, an InGaN/GaN multi-quantum well material layer and a P-type GaN material layer which are sequentially stacked on the surface of the substrate 10 along a direction vertical to the substrate 10;

2. coating a first photoresist layer on the surface of the P-type GaN material layer and photoetching to form a first etching window in the first photoresist layer, wherein the first etching window corresponds to an interval region between the first GaN-based multiple quantum well photoelectric PN junction device 11 and the first GaN-based multiple quantum well photoelectric PN junction device, etching to the N-type GaN material layer by adopting an ICP (inductively coupled plasma) dry method, and removing the first photoresist layer;

3. coating a second photoresist layer on the surface of the P-type GaN material layer and carrying out photoetching to form a second etching window in the second photoresist layer, carrying out ICP dry etching to the surface of the substrate 10 along the second etching window to form an isolation groove for separating a photonic integrated device region 1 and a peripheral circuit region 2, and removing the second photoresist layer and the InGaN/GaN multi-quantum well material layer and the P-type GaN material layer in the peripheral circuit region 2;

4. coating a third photoresist layer on the surface of the N-type GaN material layer of the peripheral circuit region 2, photoetching to form a third etching window in the third photoresist layer, etching the N-type GaN material layer to the surface of the undoped GaN layer 15 along the third etching window to form a first through hole and a second through hole, and removing the third photoresist layer;

5. coating a fourth photoresist layer on the photonic integrated device region 1 and the peripheral circuit region 2, and removing the fourth photoresist layer above a first source electrode region and a first drain electrode region for forming the first GaN-based field effect transistor, a second source electrode region and a second drain electrode region for forming the second GaN-based field effect transistor, a resistor region, a first N-type ohmic contact electrode region and a second N-type ohmic contact electrode region by photoetching;

6. evaporating the N-type ohmic contact metal by electron beams, and removing the fourth photoresist layer to form a first source electrode 212, a first drain electrode 213, a second source electrode 222, a second drain electrode 223, a resistor 23, a first N-type ohmic contact electrode 112, and a second N-type ohmic contact electrode 122;

7. growing a high-quality first gate dielectric layer 31 on the inner wall of the first through hole and growing a high-quality second gate dielectric layer on the inner wall of the second through hole by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or an atomic layer deposition process (A L D);

8. coating a fifth photoresist layer on the photonic integrated device region 1 and the peripheral circuit region 2, and removing the fifth photoresist layer on the surfaces of the first grid region of the first GaN-based field effect transistor, the second grid region of the second GaN-based field effect transistor, the first P-type ohmic contact electrode region and the second P-type ohmic contact electrode region by photoetching;

9. e-beam evaporating the P-type ohmic contact metal, and removing the fifth photoresist layer to form a first gate 211, a second gate 221, a first P-type ohmic contact electrode 111 and a second P-type ohmic contact electrode 121;

10. and removing the first GaN-based multiple quantum well photoelectric PN junction device 11, the second GaN-based multiple quantum well photoelectric PN junction device 12, and part of the substrate 10, the AlGaN buffer layer 14 and the undoped GaN layer 15 below the optical waveguide 13 to form a cavity 16.

On one hand, the first GaN-based multiple quantum well photoelectric PN junction device and the first GaN-based field effect transistor are integrated on the surface of the same substrate, and the first GaN-based multiple quantum well photoelectric PN junction device and the first GaN-based field effect transistor in the prepared monolithic photoelectric integrated circuit have high performance by utilizing the excellent characteristics of high electron mobility, high thermal conductivity, high temperature resistance, corrosion resistance, radiation resistance and the like of a GaN material; on the other hand, the first GaN-based field effect transistor provided by the invention does not need to introduce the growth of epitaxial materials in the preparation and processing process by using a complex ion implantation technology, and is completely compatible with the preparation process of the first GaN-based multi-quantum-well photoelectric PN junction device, so that the processing difficulty of a single-chip photoelectric integrated circuit is effectively reduced.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.