阅读说明：本技术 图形化结构的soi衬底的制备方法 (Preparation method of SOI substrate with graphical structure ) 是由 刘强 俞文杰 任青华 陈治西 刘晨鹤 赵兰天 陈玲丽 王曦 于 2019-01-11 设计创作，主要内容包括：本发明提供一种图形化结构的SOI衬底的制备方法,包括：在第二半导体衬底中进行离子注入形成剥离界面；于第一绝缘层中形成凹槽,所述凹槽未贯穿所述第一绝缘层；键合第二半导体衬底及第一绝缘层,以形成空腔；进行退火工艺加强键合强度,并使第二半导体衬底从剥离界面处剥离。本发明的SOI衬底的绝缘层中具有图形化空腔,可以有效改善绝缘层局部的介电常数,扩大SOI衬底的应用范围。(The invention provides a preparation method of an SOI substrate with a graphical structure, which comprises the following steps: performing ion implantation in the second semiconductor substrate to form a stripping interface; forming a groove in the first insulating layer, wherein the groove does not penetrate through the first insulating layer; bonding the second semiconductor substrate and the first insulating layer to form a cavity; and carrying out an annealing process to strengthen the bonding strength and peel the second semiconductor substrate from the peeling interface. The insulating layer of the SOI substrate is provided with the graphical cavity, so that the local dielectric constant of the insulating layer can be effectively improved, and the application range of the SOI substrate is expanded.)

1. A method for manufacturing an SOI substrate of a patterned structure, comprising:

step 1), providing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating layer on the surface of the first semiconductor substrate, and forming a second insulating layer on the surface of the second semiconductor substrate;

step 2), carrying out stripping ion implantation on the first semiconductor substrate based on the first insulating layer, and defining a stripping interface in the first semiconductor substrate;

step 3), the first insulating layer is etched in a patterned mode, and a groove penetrating through the first semiconductor substrate is formed;

step 4), bonding the first insulating layer and the second insulating layer, wherein the second insulating layer closes the groove to form a cavity;

and 5) carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second insulating layer, and stripping the first semiconductor substrate from a stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate.

2. The method for producing an SOI substrate of a patterned structure according to claim 1, characterized in that: the material of the first semiconductor substrate comprises one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide.

3. The method for producing an SOI substrate of a patterned structure according to claim 2, characterized in that: the annealing process comprises annealing at a first temperature to peel the first semiconductor substrate from a peeling interface and annealing at a second temperature to strengthen the bonding strength between the first insulating layer and the second insulating layer, wherein the first temperature is within a range of 200-900 ℃, and the second temperature is within a range of 400-1200 ℃.

4. The method for manufacturing an SOI substrate having a patterned structure according to claim 3, wherein the first semiconductor substrate is silicon, and a hydrogen ion implantation dose is 4 to 10 × 10¹⁶/cm²The stripping annealing temperature is 400-600 ℃, the stripping time length is 30-60 min, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is germanium silicon or germanium, and the hydrogen ion implantation dosage is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 300-600 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 700-850 ℃, or the first semiconductor substrate is gallium nitride, aluminum nitride, gallium oxide or zinc oxide, and the hydrogen ion implantation dosage is 2-4 × 10¹⁷/cm²The stripping annealing temperature is 300-500 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is silicon carbide, and the implantation dosage of hydrogen ions is 6-15 × 10¹⁶/cm²The stripping annealing temperature is 700-900 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is gallium arsenide, the hydrogen ion implantation dosage is 5-10 × 10¹⁶/cm²The stripping annealing temperature is 200-300 ℃, the stripping time is 30-60 min, the bonding enhancing annealing temperature is 400-550 ℃, or the first semiconductor substrate is indium phosphide, and the hydrogen ion implantation dosage is 7-10 × 10¹⁶/cm²The stripping annealing temperature is 300-400 ℃, the stripping time is 30-60 min, and the annealing temperature for reinforcing bonding is 600-850 ℃.

5. The method for producing an SOI substrate of a patterned structure according to claim 1, characterized in that: step 5) further comprises the step of performing CMP polishing on the surface of the top semiconductor layer.

6. The method for producing an SOI substrate of a patterned structure according to claim 1, characterized in that: the thickness of the top semiconductor layer is no greater than 50 nm.

7. A method for manufacturing an SOI substrate of a patterned structure, comprising:

step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming a first insulating layer on the surface of the first semiconductor substrate;

step 2), carrying out stripping ion implantation on the second semiconductor substrate, and defining a stripping interface in the second semiconductor substrate;

step 3), the first insulating layer is etched in a patterning mode, so that a groove is formed in the first insulating layer, and the groove does not penetrate through the first insulating layer;

step 4), bonding the second semiconductor substrate and the first insulating layer, wherein the second semiconductor substrate seals the groove to form a cavity;

and 5) carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second semiconductor substrate, and peeling the second semiconductor substrate from a peeling interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate.

8. The method for producing an SOI substrate of a patterned structure according to claim 7, characterized in that: the material of the first semiconductor substrate comprises one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide.

9. The method for producing an SOI substrate of a patterned structure according to claim 8, characterized in that: the annealing process comprises annealing at a first temperature to peel the second semiconductor substrate from a peeling interface and annealing at a second temperature to strengthen the bonding strength between the first insulating layer and the second semiconductor substrate, wherein the first temperature is within a range of 200-900 ℃, and the second temperature is within a range of 400-1200 ℃.

10. The method for manufacturing an SOI substrate having a patterned structure according to claim 9, wherein the second semiconductor substrate is silicon, and the hydrogen ion implantation dose is 4 to 10 × 10¹⁶/cm²The stripping annealing temperature is 400-600 ℃, the stripping time length is 30-60 min, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is germanium silicon or germanium, and the hydrogen ion implantation dosage is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 300-600 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 700-850 ℃, or the second semiconductor substrate is gallium nitride, aluminum nitride, gallium oxide or zinc oxide, and the hydrogen ion implantation dosage is 2-4 × 10¹⁷/cm²The stripping annealing temperature is 300-500 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is silicon carbide, and the implantation dosage of hydrogen ions is 6-15 × 10¹⁶/cm²The stripping annealing temperature is 700-900 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is gallium arsenide, the hydrogen ion implantation dosage is 5-10 × 10¹⁶/cm²The stripping annealing temperature is 200-300 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 400-550 ℃, or the second semiconductor substrate is indium phosphide, and the hydrogen ion implantation dosage is 7-10 × 10¹⁶/cm²The stripping annealing temperature is 300-400 ℃, the stripping time is 30-60 min, and the annealing temperature for reinforcing bonding is 600-850 ℃.

11. The method for producing an SOI substrate of a patterned structure according to claim 7, characterized in that: step 5) further comprises the step of performing CMP polishing on the surface of the top semiconductor layer.

12. The method for producing an SOI substrate of a patterned structure according to claim 7, characterized in that: the thickness of the top semiconductor layer is no greater than 50 nm.

Technical Field

The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a preparation method of an SOI substrate with a graphical structure.

Background

With the continuous scaling of microelectronic devices, it is expected that the existing FinFET technology will face a larger technical bottleneck at the 5nm and 3nm nodes, and the device performance is no longer greatly improved with the continuous reduction of the device size. There is a need for new device technologies, such as new device materials (e.g., strained silicon, silicon germanium, iii-v semiconductors, etc.), and new device structures (e.g., nanowire ring-gate transistors, etc.).

The nanowire gate-all-around transistor can limit a conducting channel to the center of the nanowire instead of the interface of the nanowire and the gate oxide layer, so that scattering of current carriers is greatly reduced, and the nanowire gate-all-around transistor is expected to be an important future development direction and further continues the development of the Mole's law.

The nanowire ring gate transistor has various preparation schemes, and one simple preparation method is to etch a hollow nanowire structure based on an SOI substrate and prepare a corresponding ring gate transistor. Fig. 1 to 12 show a method for manufacturing a representative nanowire gate-all-around transistor, in which fig. 2 shows a schematic cross-sectional structure at a-a 'of fig. 1, fig. 3 shows a schematic cross-sectional structure at B-B' of fig. 1, and fig. 4 to 12 have the same correspondence. The method mainly comprises the following steps:

as shown in fig. 1 to fig. 3, step 1) is performed to provide an SOI substrate, where the SOI substrate includes a silicon substrate 101, an oxide layer 102, and a top silicon layer 103, and a silicon nanowire 104 is etched in the top silicon layer 103 and the oxide layer 102 through a photolithography process and an etching process;

as shown in fig. 4 to 6, step 2) is performed, and the oxide layer 102 under the silicon nanowire is removed by wet etching to form a hollow hole 105;

as shown in fig. 7 to 9, step 3) is performed to thin the silicon nanowire;

as shown in fig. 10 to 12, step 4) is performed to sequentially deposit a gate dielectric layer 106 and a gate electrode 107 to form a gate-all-around transistor.

The above solution has the following disadvantages:

firstly, when the nanowire structure is etched in step 1), the top silicon of the adjacent region of the nanowire and a part of the silicon oxide under the top silicon need to be etched away. As shown in fig. 2, during the etching process, it is necessary to keep the oxide layer 102 from being etched through, and the remaining silicon oxide layer can still keep a certain thickness to prevent a large parasitic capacitance or breakdown between the gate electrode and the substrate electrode (as shown by 108 in fig. 11) as shown in fig. 11, which brings a certain requirement to the accuracy of the etching process.

Secondly, in order to prepare the silicon nanowire with the suspended structure, the oxide layer under the nanowire needs to be etched, and a wet etching is usually adopted, but since the wet etching is an isotropic etching, a part of the silicon oxide in the exposed region except under the silicon nanowire is also etched, and an unnecessary concave cavity 109 is formed, as shown in fig. 8.

This concave cavity can have the following adverse effects:

as shown in fig. 13 and 14, wherein fig. 13 is a top view of the cross section at C-C' of fig. 11, and fig. 14 is an enlarged schematic view of the dashed frame of fig. 13, the concave cavity is finally filled with the gate dielectric layer 106 and the gate electrode 107, in order to ensure good step coverage, the gate dielectric layer 106 and the gate electrode 107 are generally prepared by using a L D process, but even in the a L D process, when a semi-closed structure with concavity is filled, the film-to-film contact interconnection is easily advanced during the process of filling the plating film, and finally a closed cavity in the gate metal is formed in the concave structure, instead of being completely filled.

As shown in fig. 8, 13 and 14, the corresponding concave cavity 109 in fig. 8 is also filled with the gate dielectric layer 106 and the gate electrode 107, so that the gate electrode under the nanowire is longer than the gate electrode above the nanowire. This results in: an unnecessary overlapping area is arranged between the bottom layer gate and the source drain, a silicon channel in the area is influenced by asymmetric gate potential, and current carriers in the silicon channel are scattered to a certain extent; the resistance between the gate electrode and the source-drain electrode becomes large; the source-drain parasitic capacitance becomes large, and the high-frequency characteristic of the device becomes poor; when the silicon channel of the overlapping region is heavily doped, hot electrons are easily generated between the bottom gate and the silicon channel of the overlapping region, the gate leakage current is increased, and the gate oxide is broken down.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing an SOI substrate with a patterned structure, which is used to solve the problem of relatively single performance of the SOI substrate with the patterned structure manufactured by the conventional process in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing an SOI substrate of a patterned structure, the method comprising: step 1), providing a first semiconductor substrate and a second semiconductor substrate, forming a first insulating layer on the surface of the first semiconductor substrate, and forming a second insulating layer on the surface of the second semiconductor substrate; step 2), carrying out stripping ion implantation on the first semiconductor substrate based on the first insulating layer, and defining a stripping interface in the first semiconductor substrate; step 3), the first insulating layer is etched in a patterned mode, and a groove penetrating through the first semiconductor substrate is formed; step 4), bonding the first insulating layer and the second insulating layer, wherein the second insulating layer closes the groove to form a cavity; and 5) carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second insulating layer, and stripping the first semiconductor substrate from a stripping interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate.

Optionally, the stripping ions include one of H ions and He ions.

Optionally, the annealing process includes annealing at a first temperature to peel the first semiconductor substrate from the peeling interface, and annealing at a second temperature to strengthen the bonding strength between the first insulating layer and the second insulating layer, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃.

Optionally, the first semiconductor substrate is silicon, and the implantation dosage of hydrogen ions is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 400-600 ℃, the stripping time length is 30-60 min, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is germanium silicon or germanium, and the hydrogen ion implantation dosage is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 300-600 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 700-850 ℃, or the first semiconductor substrate is gallium nitride, aluminum nitride, gallium oxide or zinc oxide, and the hydrogen ion implantation dosage is 2-4 × 10¹⁷/cm²The stripping annealing temperature is 300-500 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is silicon carbide, and the implantation dosage of hydrogen ions is 6-15 × 10¹⁶/cm²The stripping annealing temperature is 700-900 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the first semiconductor substrate is gallium arsenide, the hydrogen ion implantation dosage is 5-10 × 10¹⁶/cm²The stripping annealing temperature is 200-300 ℃, the stripping time is 30-60 min, the bonding enhancing annealing temperature is 400-550 ℃, or the first semiconductor substrate is indium phosphide, and the hydrogen ion implantation dosage is 7-10 × 10¹⁶/cm²The stripping annealing temperature is 300-400 ℃, the stripping time is 30-60 min, and the annealing temperature for reinforcing bonding is 600-850 ℃.

Optionally, step 5) further comprises the step of CMP polishing the top semiconductor surface.

Optionally, the top semiconductor layer has a thickness of no greater than 50 nm.

The invention also provides a preparation method of the SOI substrate with the graphical structure, which comprises the following steps: step 1), providing a first semiconductor substrate and a second semiconductor substrate, and forming a first insulating layer on the surface of the first semiconductor substrate; step 2), carrying out stripping ion implantation on the second semiconductor substrate, and defining a stripping interface in the second semiconductor substrate; step 3), the first insulating layer is etched in a patterning mode, so that a groove is formed in the first insulating layer, and the groove does not penetrate through the first insulating layer; step 4), bonding the second semiconductor substrate and the first insulating layer, wherein the second semiconductor substrate seals the groove to form a cavity; and 5) carrying out an annealing process to strengthen the bonding strength of the first insulating layer and the second semiconductor substrate, and peeling the second semiconductor substrate from a peeling interface, wherein the part combined with the first insulating layer is used as a top semiconductor layer of the SOI substrate.

Optionally, the second semiconductor substrate is silicon, and the implantation dosage of hydrogen ions is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 400-600 ℃, the stripping time length is 30-60 min, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is germanium silicon or germanium, and the hydrogen ion implantation dosage is 4-10 × 10¹⁶/cm²The stripping annealing temperature is 300-600 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 700-850 ℃, or the second semiconductor substrate is gallium nitride, aluminum nitride, gallium oxide or zinc oxide, and the hydrogen ion implantation dosage is 2-4 × 10¹⁷/cm²The stripping annealing temperature is 300-500 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is silicon carbide, and the implantation dosage of hydrogen ions is 6-15 × 10¹⁶/cm²The stripping annealing temperature is 700-900 ℃, the stripping time is 2-5 hours, the annealing temperature for reinforcing bonding is 900-1200 ℃, or the second semiconductor substrate is gallium arsenide, the hydrogen ion implantation dosage is 5-10 × 10¹⁶/cm²The stripping annealing temperature is 200-300 ℃, the stripping time is 30-60 min, the annealing temperature for reinforcing bonding is 400-550 ℃, or the second semiconductor substrate is indium phosphide, and the hydrogen ion implantation dosage is 7-10 × 10¹⁶/cm²The stripping annealing temperature is 300-400 DEG CThe stripping time is 30-60 min, and the annealing temperature for bonding reinforcement is 600-850 ℃.

Optionally, the stripping ions include one of H ions and He ions.

Optionally, the annealing process includes annealing at a first temperature to peel the second semiconductor substrate from the peeling interface, and annealing at a second temperature to strengthen the bonding strength between the first insulating layer and the second semiconductor substrate, wherein the first temperature is in a range of 200-900 ℃, and the second temperature is in a range of 400-1200 ℃.

Optionally, step 5) further comprises the step of CMP polishing the top semiconductor surface.

Optionally, the top semiconductor layer has a thickness of no greater than 50 nm.

As described above, the method for manufacturing an SOI substrate having a patterned structure according to the present invention has the following advantageous effects:

1) the invention provides a preparation method of an SOI substrate with good process stability, the SOI substrate can directly prepare hollow semiconductor nanowires through dry etching, isotropic wet etching is not needed when the semiconductor nanowires are prepared, and the generation of concave cavities can be effectively avoided.

2) The insulating layer of the SOI substrate is provided with the graphical cavity, so that the local dielectric constant of the insulating layer can be effectively improved, and the application range of the SOI substrate is expanded.

Drawings

Fig. 1 to 14 are schematic structural diagrams showing steps of a method for manufacturing a nanowire wrap-around transistor in the prior art.

Fig. 15 to 21 are schematic structural views showing steps of a method for manufacturing an SOI substrate having a patterned structure in embodiment 1 of the present invention.

Fig. 22 to 28 are schematic structural views showing steps of a method for manufacturing an SOI substrate having a patterned structure in embodiment 2 of the present invention.

Description of the element reference numerals

201 first silicon substrate

202 first insulating layer

203 groove

204 cavity

301 second silicon substrate

302 second insulating layer

401 top silicon layer

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 15-28. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.