阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 张庆 金懿 蒋莉 纪登峰 刘璐 于 2018-12-26 设计创作，主要内容包括：一种半导体结构及其形成方法,形成方法包括：提供基底,基底上形成有伪栅结构,伪栅结构露出的基底上形成有层间介质层,层间介质层露出伪栅结构顶部；在相邻伪栅结构之间的层间介质层中形成隔离结构,隔离结构还延伸至基底中；形成隔离结构后,去除伪栅结构,在层间介质层内形成栅极开口；向栅极开口内填充栅电极材料,栅电极材料还覆盖层间介质层顶部；进行至少一次研磨处理,去除高于层间介质层顶部的栅电极材料,保留栅极开口内的栅电极材料作为栅电极层,研磨处理步骤包括：采用金属用研磨液进行第一研磨处理；采用去离子水进行第二研磨处理。通过第二研磨处理,降低层间介质层顶面形成有栅电极材料的残留物的概率,改善了器件性能。(A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a pseudo gate structure is formed on the substrate, an interlayer dielectric layer is formed on the substrate exposed out of the pseudo gate structure, and the interlayer dielectric layer is exposed out of the top of the pseudo gate structure; forming an isolation structure in the interlayer dielectric layer between the adjacent pseudo gate structures, wherein the isolation structure also extends into the substrate; after the isolation structure is formed, removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, wherein the gate electrode material also covers the top of the interlayer dielectric layer; performing at least one grinding treatment to remove the gate electrode material higher than the top of the interlayer dielectric layer and reserve the gate electrode material in the gate opening as a gate electrode layer, wherein the grinding treatment comprises the following steps: performing first grinding treatment by using a metal grinding fluid; and carrying out second grinding treatment by using deionized water. Through the second grinding treatment, the probability of forming residues of the gate electrode material on the top surface of the interlayer dielectric layer is reduced, and the performance of the device is improved.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a dummy gate structure is formed on the substrate, an interlayer dielectric layer is formed on the substrate exposed out of the dummy gate structure, and the interlayer dielectric layer covers the side wall of the dummy gate structure and exposes out of the top of the dummy gate structure;

forming an isolation structure in the interlayer dielectric layer between the adjacent pseudo gate structures, wherein the isolation structure also extends into the substrate;

after the isolation structure is formed, removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer;

filling a gate electrode material into the gate opening, wherein the gate electrode material also covers the top of the interlayer dielectric layer;

performing at least one grinding treatment, removing the gate electrode material higher than the top of the interlayer dielectric layer, and reserving the gate electrode material in the gate opening as a gate electrode layer, wherein the grinding treatment comprises the following steps: performing first grinding treatment on the gate electrode material by using metal grinding fluid; and after the first grinding treatment, carrying out second grinding treatment on the isolation structure by using deionized water.

2. The method of forming a semiconductor structure according to claim 1, wherein after filling the gate electrode material into the gate opening and before performing the polishing process, the method further comprises: and preprocessing the gate electrode material, removing part of the gate electrode material with a certain thickness, and exposing the top of the isolation structure.

3. The method of claim 2, wherein the pre-treatment is performed using one or both of a Chemical Mechanical Polishing (CMP) process and an etch-back process.

4. The method of claim 1, wherein the number of polishing processes is from 3 to 12.

5. The method of claim 1, wherein the second polishing process has a process time of 5 seconds to 15 seconds per polishing process.

6. The method of claim 1, wherein a process time of the second polishing process is 10 seconds to 15 seconds per polishing process.

7. The method for forming a semiconductor structure according to claim 1, wherein in the step of the first polishing treatment, the metal-polishing slurry has a PH of 2 to 6.

8. The method of forming a semiconductor structure of claim 1, wherein the parameters of the second polishing process comprise: the down force is 1.0psi to 3.0psi, the susceptor speed is 30rpm to 100rpm, and the flow rate of deionized water is 100ml/min to 300 ml/min.

9. The method of claim 1, wherein the isolation structure is made of silicon nitride, polysilicon, or a metal nitride.

10. The method of claim 1, wherein a hardness of the isolation structure is higher than a hardness of the interlevel dielectric layer.

11. The method of claim 1, wherein the interlayer dielectric layer is made of silicon oxide, and the isolation structure is made of silicon nitride.

12. The method of forming a semiconductor structure of claim 1, wherein forming the isolation structure comprises: sequentially etching the interlayer dielectric layer and a part of thickness substrate between the adjacent pseudo gate structures to form grooves in the interlayer dielectric layer and the substrate;

filling an isolation material into the groove, wherein the isolation material also covers the top of the interlayer dielectric layer;

and removing the isolation material higher than the top of the interlayer dielectric layer by adopting a planarization process, and reserving the isolation material in the groove as the isolation structure.

13. The method of claim 12, wherein the planarization process is one or both of a chemical mechanical polishing process and an etch-back process.

14. The method of forming a semiconductor structure of claim 1, wherein in the step of filling the gate opening with a gate electrode material, the gate electrode material is W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

15. A semiconductor structure formed by the method of any of claims 1-14.

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

The principal semiconductor devices of integrated circuits, particularly very large scale integrated circuits, are metal-oxide-semiconductor field effect transistors (MOS transistors). With the development trend of very large scale integrated circuits, the integrated circuits are more and more complex, and the technical nodes of semiconductor devices are continuously reduced. As the size of semiconductor devices is reduced to a certain extent, various secondary effects due to the physical limitations of semiconductor devices are occurring in succession, for example: the problem of large leakage current of the semiconductor device. In order to improve the problem of leakage current, a high-k gate dielectric material is mainly adopted to replace the traditional silicon dioxide gate dielectric material, and metal is used as a gate electrode so as to avoid the Fermi level pinning effect and the boron penetration effect of the high-k material and the traditional gate electrode material.

Moreover, as the size of the semiconductor device is continuously reduced, the distance between adjacent transistors is also reduced, and the source-drain doped layers of the adjacent transistors are easy to be connected (merge), so that bridging between the source region and the drain region of the adjacent transistors is caused. In order to prevent a source-drain bridge between source and drain regions of adjacent transistors, the prior art introduces a Single Diffusion Break (SDB) isolation structure manufacturing technique.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve device performance.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a dummy gate structure is formed on the substrate, an interlayer dielectric layer is formed on the substrate exposed out of the dummy gate structure, and the interlayer dielectric layer covers the side wall of the dummy gate structure and exposes out of the top of the dummy gate structure; forming an isolation structure in the interlayer dielectric layer between the adjacent pseudo gate structures, wherein the isolation structure also extends into the substrate; after the isolation structure is formed, removing the pseudo gate structure, and forming a gate opening in the interlayer dielectric layer; filling a gate electrode material into the gate opening, wherein the gate electrode material also covers the top of the interlayer dielectric layer; performing at least one grinding treatment, removing the gate electrode material higher than the top of the interlayer dielectric layer, and reserving the gate electrode material in the gate opening as a gate electrode layer, wherein the grinding treatment comprises the following steps: carrying out first grinding treatment on the gate electrode material by using metal grinding fluid; and after the first grinding treatment, carrying out second grinding treatment on the isolation structure by using deionized water.

Optionally, after filling the gate electrode material into the gate opening and before performing the polishing process, the method further includes: and preprocessing the gate electrode material, removing part of the gate electrode material with a certain thickness, and exposing the top of the isolation structure.

Optionally, the pretreatment is performed by using one or both of a chemical mechanical polishing method and a back etching method.

Optionally, the number of the grinding treatments is 3 to 12.

Optionally, in each grinding process, the process time of the second grinding process is 5 seconds to 15 seconds.

Optionally, in each grinding process, the process time of the second grinding process is 10 seconds to 15 seconds.

Optionally, in the first polishing treatment step, the PH of the metal polishing slurry is 2 to 6.

Optionally, the parameters of the second grinding treatment include: the down force is 1.0psi to 3.0psi, the susceptor speed is 30rpm to 100rpm, and the flow rate of deionized water is 100ml/min to 300 ml/min.

Optionally, the isolation structure is made of silicon nitride, polysilicon, or metal nitride.

Optionally, the hardness of the isolation structure is higher than that of the interlayer dielectric layer.

Optionally, the interlayer dielectric layer is made of silicon oxide, and the isolation structure is made of silicon nitride.

Optionally, the step of forming the isolation structure includes: sequentially etching the interlayer dielectric layer and a part of thickness substrate between the adjacent pseudo gate structures to form grooves in the interlayer dielectric layer and the substrate; filling an isolation material into the groove, wherein the isolation material also covers the top of the interlayer dielectric layer; and removing the isolation material higher than the top of the interlayer dielectric layer by adopting a planarization process, and reserving the isolation material in the groove as the isolation structure.

Optionally, the planarization process is one or both of a chemical mechanical polishing process and an etching back process.

Optionally, in the step of filling the gate electrode material into the gate opening, the gate electrode material is W, Al, Cu, Ag, Au, Pt, Ni, or Ti.

Correspondingly, the embodiment of the invention also provides a semiconductor structure formed by adopting the forming method.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, after filling the gate electrode material into the gate opening, at least one grinding treatment is carried out to remove the gate electrode material higher than the top of the interlayer dielectric layer, the gate electrode material in the gate opening is reserved as the gate electrode layer, the grinding treatment comprises a first grinding treatment and a second grinding treatment which are sequentially carried out, the first grinding treatment adopts metal grinding fluid, the second grinding adopts deionized water, wherein the first grinding treatment is used for removing the gate electrode material, the metal grinding fluid is usually acidic grinding fluid, and after each first grinding treatment, the acid solution remains on the surface of the wafer (wafer), so that in the process of the second grinding treatment which is sequentially carried out, the isolation structure is in an acid environment, the isolation structure is subjected to hydration reaction, and the hardness and the strength of the isolation structure influenced by the second grinding treatment are reduced, facilitating the thinning of the isolation structure by the second grinding process; therefore, even if the top of the isolation structure protrudes out of the top of the interlayer dielectric layer after the isolation structures are formed in the interlayer dielectric layer and the substrate, the isolation structure protruding out of the interlayer dielectric layer can be removed in the step of removing the gate electrode material higher than the top of the interlayer dielectric layer, so that the gate electrode material on the top of the interlayer dielectric layer can be exposed in the process environment of first grinding treatment, the difficulty of removing the gate electrode material on the top of the interlayer dielectric layer is correspondingly reduced, the probability of forming residues of the gate electrode material on the top of the interlayer dielectric layer is remarkably reduced, and the performance of the device is improved.

Drawings

Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIGS. 7-14 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 15 is a bar graph of the total removal of gate electrode material and isolation structures and a line graph of the removal selectivity for different milling conditions in the embodiments shown in fig. 7-14.

Detailed Description

At present, after an SDB isolation structure is introduced into a semiconductor structure, the performance of the device is easily reduced. The cause of the performance degradation is now analyzed in conjunction with a method of forming a semiconductor structure.

Referring to fig. 1 to 6, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.

Referring to fig. 1, a substrate 10 is provided, a dummy gate structure 20 is formed on the substrate 10, an interlayer dielectric layer 30 is formed on the substrate 10 exposed from the dummy gate structure 20, and the interlayer dielectric layer 30 covers a side wall of the dummy gate structure 20 and exposes the top of the dummy gate structure 20.

Referring to fig. 2, the interlayer dielectric layer 30 and the substrate 10 with a partial thickness between adjacent dummy gate structures 20 are sequentially etched to form a trench 35.

Referring to fig. 3, SDB isolation structures 40 are formed in the trenches 35 (shown in fig. 2).

In order to improve the isolation effect of the SDB isolation structure 40, the material of the SDB isolation structure 40 is usually silicon nitride.

Referring to fig. 4, after the SDB isolation structure 40 is formed, the dummy gate structure 20 (shown in fig. 3) is removed, and a gate opening 32 is formed in the interlayer dielectric layer 30.

Referring to fig. 5, the gate opening 32 (shown in fig. 4) is filled with a gate electrode material 55, and the gate electrode material 55 also covers the top of the interlayer dielectric layer 30.

Referring to fig. 6, the gate electrode material 55 (shown in fig. 5) is planarized using a chemical mechanical polishing process, leaving the gate electrode material 55 within the gate opening 32 (shown in fig. 4) as the gate electrode layer 50.

The process of forming the SDB isolation structure 40 in the trench 35 generally includes a step of filling an isolation material and a step of performing planarization (e.g., chemical mechanical polishing) on the isolation material, since the material of the interlayer dielectric layer 30 is generally silicon oxide, the interlayer dielectric layer 30 is softer, and during the planarization process of forming the SDB isolation structure 40, the dishing problem is likely to occur on the top surface of the interlayer dielectric layer 30, so that the top of the SDB isolation structure 40 protrudes from the top of the interlayer dielectric layer 30, and the dishing problem of the interlayer dielectric layer 30 is more serious the lower the pattern density (pattern density) of the SDB isolation structure 40.

The gate electrode material 55 is typically a metal material (e.g., W), and for this purpose, when the gate electrode material 55 (as shown in fig. 4) is planarized by a chemical mechanical polishing process, the polishing solution used for removing the gate electrode material 55 is typically an acidic polishing solution.

However, the Removal Rate (RR) of the SDB isolation structure 40 by the polishing slurry is low, so that the SDB isolation structure 40 protruding from the interlayer dielectric layer 30 blocks the polishing of the gate electrode material 55, and after the gate electrode material 55 is polished, the metal residue 51 is easily formed on the top of the interlayer dielectric layer 30, thereby adversely affecting the performance of the device.

In order to solve the technical problem, in the embodiment of the present invention, after filling a gate electrode material into a gate opening, at least one grinding process is performed to remove the gate electrode material higher than the top of an interlayer dielectric layer, and the gate electrode material in the gate opening is retained as a gate electrode layer, the grinding process includes a first grinding process and a second grinding process which are sequentially performed, and the first grinding process uses a metal grinding fluid and the second grinding uses deionized water, wherein the first grinding process is used to remove the gate electrode material, the metal grinding fluid is usually an acidic grinding fluid, and after each first grinding process, an acidic solution still remains on a wafer surface, so that in a second grinding process which is performed sequentially, the isolation structure is in an acidic environment, the isolation structure undergoes a hydration reaction, so that the hardness and strength of the isolation structure affected by the second grinding process are reduced, facilitating the thinning of the isolation structure by the second grinding process; therefore, even if the isolation structure protrudes out of the interlayer dielectric layer, the isolation structure protruding out of the interlayer dielectric layer can be removed in the step of removing the gate electrode material higher than the top of the interlayer dielectric layer, so that the gate electrode material on the top surface of the interlayer dielectric layer can be exposed in the first grinding process environment, the difficulty of removing the gate electrode material on the top surface of the interlayer dielectric layer is correspondingly reduced, the probability of forming residues of the gate electrode material on the top surface of the interlayer dielectric layer is remarkably reduced, and the performance of the device is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 7 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to fig. 7, a substrate 100 is provided, a dummy gate structure 200 is formed on the substrate 100, an interlayer dielectric layer 300 is formed on the substrate 100 exposed by the dummy gate structure 200, and the interlayer dielectric layer 300 covers the sidewall of the dummy gate structure 200 and exposes the top of the dummy gate structure 200.

The substrate 100 is used to provide a process platform for subsequent processes.

In this embodiment, taking the formed device as a fin field effect transistor as an example, the substrate 100 includes a substrate 101 and a fin 102 protruding from the substrate 101.

Specifically, the material of the substrate 101 is silicon. In other embodiments, the material of the substrate 101 may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the fin 102 and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of accurately controlling the height of the fin.

Therefore, in this embodiment, the material of the fin portion 102 is the same as the material of the substrate 101, and the material of the fin portion 102 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.

The dummy gate structure 200 is used to occupy a spatial location for the formation of a subsequent metal gate structure.

In this embodiment, the dummy gate structure 200 crosses over the fin 102 and covers a portion of the top and a portion of the sidewall of the fin 102.

In this embodiment, taking the pseudo gate structure 200 as a single-layer structure as an example, the material of the pseudo gate structure 200 is polysilicon.

In other embodiments, in the case that the dummy gate structure is a single-layer structure, the material of the dummy gate structure may also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials.

In other embodiments, the dummy gate structure may also be a stacked structure, including a dummy gate oxide layer and a dummy gate layer on the dummy gate oxide layer; the dummy gate layer may be made of polysilicon or amorphous carbon, and the dummy oxide layer may be made of silicon oxide or silicon oxynitride.

In this embodiment, a sidewall 250 is formed on the sidewall of the dummy gate structure 200.

The sidewall spacers 250 are used to define a formation region of a subsequent source-drain doping layer, and also used to protect the sidewalls of the dummy gate structure 200 in a subsequent process.

The sidewall 250 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 250 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 250 has a single-layer structure, and the material of the sidewall spacer 250 is silicon nitride.

In this embodiment, after the sidewall spacers 250 are formed, the interlayer dielectric layer 300 is formed on the substrate 100 exposed by the dummy gate structure 200 and the sidewall spacers 250.

The interlayer dielectric layer 300 is used to electrically isolate adjacent devices and to define the size and position of a metal gate structure to be formed subsequently.

The interlayer dielectric layer 300 is made of an insulating material. In this embodiment, the interlayer dielectric layer 300 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

In this embodiment, the top of the interlayer dielectric layer 300 is flush with the top of the sidewall spacer 250.

Referring to fig. 8 to 10, an isolation structure 400 (as shown in fig. 10) is formed in the interlayer dielectric layer 300 between adjacent dummy gate structures 200, and the isolation structure 400 further extends into the substrate 100.

The isolation structure 400 acts as an SDB isolation structure to isolate adjacent devices.

As the size of the device decreases, along the extending direction of the fin 110, the distance (HTH) between the ends of adjacent fins 110 decreases, and the distance between adjacent metal gate structures decreases, and the isolation structures 400 are distributed in the extending direction of the fin 102, so that isolation between adjacent devices can be achieved through the isolation structures 400, the probability of bridging between the source region and the drain region of adjacent devices is reduced, and the performance and yield of the device are improved.

For this reason, in this embodiment, the isolation structure 400 is formed between the adjacent dummy gate structures 200 in a direction perpendicular to the sidewalls of the dummy gate structures 200.

In this embodiment, the isolation structure 400 is made of silicon nitride. Silicon nitride is a common isolation material, and has a good isolation effect and process compatibility. In other embodiments, the material of the isolation structure may also be polysilicon or metal nitride (e.g., titanium nitride or tantalum nitride).

For this, the isolation structure 400 has a hardness higher than that of the interlayer dielectric layer 300.

Specifically, the step of forming the isolation structure 400 includes:

referring to fig. 8, the interlayer dielectric layer 300 and a portion of the thickness of the substrate 100 between adjacent dummy gate structures 200 are sequentially etched to form a trench 350 in the interlayer dielectric layer 300 and the substrate 100.

The trenches 350 are used to provide spatial locations for the formation of subsequent isolation structures.

In this embodiment, the interlayer dielectric layer 300 and the fin portion 102 with a partial thickness are sequentially etched, so that the interlayer dielectric layer 300 and the fin portion 102 enclose the trench 350, that is, the bottom of the trench 350 is located in the fin portion 102. In other embodiments, the interlayer dielectric layer, the fin portion and the substrate with a partial thickness may be sequentially etched, so that the interlayer dielectric layer, the fin portion and the substrate enclose the trench, and the bottom of the trench is correspondingly located in the substrate.

Referring to fig. 9, the trench 350 (shown in fig. 8) is filled with an isolation material 450, and the isolation material 450 also covers the top of the ild layer 300.

In the present embodiment, the isolation material 450 is silicon nitride, and the isolation material 450 is filled in the trench 350 by chemical vapor deposition.

Referring to fig. 10, a planarization process is used to remove the isolation material 450 (shown in fig. 9) above the top of the ild layer 300, and the isolation material 450 in the trench 350 (shown in fig. 8) is remained as the isolation structure 400.

In this embodiment, the planarization process is a chemical mechanical polishing process.

In other embodiments, other planarization processes may also be employed. For example, the isolation material is etched back to remove the isolation material above the top of the interlayer dielectric layer, or a process combining chemical mechanical polishing and etching back is used to remove the isolation material above the top of the interlayer dielectric layer.

It should be noted that, since the hardness of the interlayer dielectric layer 300 is less than the hardness of the isolation structure 400, after the isolation material 450 higher than the top of the interlayer dielectric layer 300 is removed, the top surface of the interlayer dielectric layer 300 around the isolation structure 400 is prone to have a dishing problem, that is, the top of the isolation structure 400 is prone to protrude from the top of the interlayer dielectric layer 300, which may also cause the sidewall 250 to protrude from the interlayer dielectric layer 300.

Referring to fig. 11, after the isolation structure 400 is formed, the dummy gate structure 200 is removed (as shown in fig. 10), and a gate opening 320 is formed in the interlayer dielectric layer 300.

The gate opening 320 is used to provide a spatial location for the subsequent formation of a metal gate structure.

In this embodiment, after the dummy gate structure 200 is removed, the gate opening 320 is surrounded by the sidewall 250 and the substrate 100.

Referring to fig. 12, the gate opening 320 (shown in fig. 11) is filled with a gate electrode material 550, and the gate electrode material 550 also covers the top of the interlayer dielectric layer 300.

The gate electrode material 550 is used to provide a process basis for the formation of a subsequent gate electrode layer, which is used as part of the metal gate structure.

In this embodiment, the gate electrode material 550 is W. In other embodiments, the gate electrode material may also be Al, Cu, Ag, Au, Pt, Ni, or Ti.

In order to provide a sufficient process window for the subsequent grinding process to improve the surface flatness of the subsequently formed gate electrode layer, the gate electrode material 550 not only fills the gate opening 320, but also covers at least the top of the interlayer dielectric layer 300.

In this embodiment, the gate electrode material 550 also covers the top of the isolation structure 400 and the top of the sidewall spacers 250.

Referring to fig. 13 and 14 in combination, at least one grinding process is performed to remove the gate electrode material 550 (shown in fig. 12) above the top of the interlayer dielectric layer 300 and leave the gate electrode material 550 in the gate opening 320 (shown in fig. 11) as the gate electrode layer 500, and the grinding process includes the steps of: performing a first polishing process on the gate electrode material 550 with a metal polishing slurry; after the first grinding process, a second grinding process is performed on the isolation structure 400 using deionized water.

The first polishing process is used to remove the gate electrode material 550, so the metal polishing slurry is usually an acidic polishing slurry, and after each first polishing process, an acidic solution remains on the wafer surface, so that during a second polishing process which is performed subsequently, the isolation structure 400 is in an acidic environment, and a hydration reaction occurs in the isolation structure 400, so that the hardness and strength of the isolation structure 400 affected by the second polishing process are reduced, and the isolation structure 400 is easily thinned by the second polishing process under the mechanical force of the second polishing process.

Therefore, after the isolation structure 400 is formed, even if the top of the isolation structure 400 protrudes out of the top of the interlayer dielectric layer 300, the isolation structure 400 protruding out of the interlayer dielectric layer 300 can be removed in the step of removing the gate electrode material 550 higher than the top of the interlayer dielectric layer 300 through the grinding treatment, so that the gate electrode material 550 on the top surface of the interlayer dielectric layer 300 can be exposed in the process environment of the first grinding treatment, the difficulty of removing the gate electrode material 550 on the top surface of the interlayer dielectric layer 300 is correspondingly reduced, the residue of the gate electrode material 550 on the top surface of the interlayer dielectric layer 300 is avoided, and the device performance is improved.

The deionized water is also used as the grinding fluid of the second grinding treatment and plays a role in lubrication, so that the normal operation of the second grinding treatment is guaranteed, the process cost can be reduced, and the generation of side effects is obviously reduced.

Moreover, the deionized water is used as the polishing liquid for the second polishing treatment, so that the PH of the polishing liquid for the second polishing treatment is relatively high, and under the action of the deionized water, the polishing particles in the polishing liquid for the metal are removed, thereby reducing the influence of the second polishing treatment on the gate electrode material 550 and the interlayer dielectric layer 300.

Correspondingly, even if the side walls 250 protrude out of the interlayer dielectric layer 300, the side walls 250 protruding out of the interlayer dielectric layer 300 can also be removed in the grinding treatment, so that the effect of removing the gate electrode material 550 on the top surface of the interlayer dielectric layer 300 is further ensured, and the improvement of the uniformity of the height of each gate electrode layer 500 is facilitated, so that the uniformity of the device performance is improved.

The gate electrode material 550 is a metal material, and therefore, the polishing liquid for metal is an acidic polishing liquid to ensure a high removal rate. The acidic polishing slurry contains a large amount of oxidizing agent, and in the first polishing treatment, the gate electrode material 550 is oxidized by the metal polishing slurry and converted into a metal oxide, which is softer than the metal and is easily removed mechanically.

According to the material selected for the gate electrode layer 500, a metal polishing solution with a corresponding PH value is selected to ensure the polishing effect on the gate electrode material 550, and the metal polishing solution is an acidic polishing solution.

Wherein the pH of the metal polishing slurry is not excessively high. If the PH is too high, the acidic environment of the isolation structure 400 is easily weakened under the action of deionized water during the subsequent second polishing process, so that the removal effect of the second polishing process to remove the isolation structure 400 is reduced. For this reason, in the present embodiment, the PH of the metal polishing slurry is 2 to 6, for example, 4 or 5.

It should be noted that increasing the number of times of the polishing process is beneficial to increasing the removal effect of the second polishing process on the isolation structure 400, and accordingly, after the polishing process is completed, the probability that the top surface of the interlayer dielectric layer 300 has the residue of the gate electrode material 550 is significantly reduced; however, if the number of times is too large, the total time of the multiple second polishing processes is increased accordingly, thereby reducing the manufacturing efficiency, and in order to ensure that the thickness of the gate electrode layer 500 to be formed can meet the process requirements, the increased number of times results in a reduced time for the single first polishing process, which easily reduces the process stability of the first polishing process, thereby adversely affecting the polishing effect of the gate electrode material 550. For this reason, in this embodiment, in order to ensure a good process effect, the number of times of the grinding treatment is 3 to 12.

Referring collectively to fig. 15, fig. 15 shows a bar graph of the total removal of gate electrode material and isolation structures, and a line graph of the removal selectivity for different milling conditions.

The abscissa represents the number of times of the grinding treatment, the primary ordinate represents the total removal amount of the gate electrode material and the isolation structure, and the secondary ordinate represents the removal selectivity; wherein, the column diagram filled by oblique lines represents the total removal amount of the gate electrode material, and the column diagram filled by white lines represents the total removal amount of the isolation structure; the removal selection ratio refers to: the ratio of the total removal of gate electrode material to the total removal of isolation structures.

The broken line block 601 indicates a case where the second polishing process is not performed (that is, a case where only one polishing process is performed using the metal polishing liquid), and for comparison, the broken line block 602 indicates a case where the polishing process is performed three times in a cycle, the broken line block 603 indicates a case where the polishing process is performed four times in a cycle, the broken line block 604 indicates a case where the polishing process is performed six times in a cycle, and the broken line block 605 indicates a case where the polishing process is performed ten times in a cycle.

As can be seen from the figure, when the total time of the polishing treatment using the metal polishing slurry is the same, the first polishing treatment and the second polishing treatment are performed successively, which is advantageous for reducing the difference in the total removal amount between the gate electrode material and the isolation structure; the cycle number of grinding treatment is increased, and the difference of the total removal amount of the gate electrode material and the isolation structure can also be reduced, so that the isolation structure protruding out of the interlayer dielectric layer can be removed while the gate electrode material is ground and removed.

It should be noted that, in each grinding process, the process time of the second grinding process is not short, nor long. If the process time is too short, the removal effect of the second grinding treatment on the isolation structure 400 is correspondingly reduced, and correspondingly, after the grinding treatment is completed, the probability that residues of the gate electrode material 550 still exist on the top surface of the interlayer dielectric layer 300 is higher; with the increase of the processing time of the second grinding processing, the acidic environment on the wafer surface is gradually weakened, the influence of the second grinding processing on the isolation structure 400 is gradually reduced, and even when the processing time of the second grinding processing exceeds a certain value, the second grinding processing does not influence the isolation structure 400 any more, so that the cost and the time are wasted due to the overlong processing time. For this reason, in this embodiment, the process time of the second polishing process is 5 seconds to 15 seconds in each polishing process.

Specifically, in order to further enhance the removal effect of the second grinding process on the isolation structure 400, the process time of the second grinding process is 10 seconds to 15 seconds in each grinding process.

During the second grinding process, the Down Force (Down Force) should not be too small, nor too large. If the downward pressure is too low, the removal effect of the second grinding process on the isolation structure 400 is easily reduced; if the down pressure is too large, damage to the gate electrode material 550 is likely to occur. For this reason, in this embodiment, the down force of the second grinding process is 1.0psi to 3.0 psi. Where psi refers to Pounds Per Square inch (pound Per Square inch).

During the second grinding process, the susceptor rotation Speed (Platen Speed) should not be too low, nor too high. If the rotation speed is too low, in order to ensure the removal effect of the second grinding treatment on the isolation structure 400, the grinding efficiency is reduced correspondingly; if the rotation speed is too high, the uniformity of the treatment effect of the second polishing treatment is liable to deteriorate. For this reason, in the present embodiment, the base rotation speed is 30rpm to 100 rpm. Wherein rpm refers to revolutions Per Minute (Roung Per Minute).

In the second grinding process, the flow rate of the deionized water should not be too small, and should not be too large. If the flow rate is too low, the friction between the wafer surface and the polishing pad is increased, which may increase the roughness of the isolation structure 400 and the gate electrode material 550; if the flow rate is too high, the residual acidic solution on the wafer surface is diluted rapidly, and the isolation structure 400 cannot be ensured to have enough time in the desired acidic environment, so that the removal effect of the isolation structure 400 by the second polishing process is deteriorated. For this reason, in the present embodiment, the flow rate of deionized water is 100ml/min to 300 ml/min.

As shown in fig. 13, in this embodiment, since the gate electrode material 550 further covers the top of the isolation structure 400 and the top of the sidewall spacers 250, before performing the multiple grinding processes, the method further includes: the gate electrode material 550 is pre-processed to remove a portion of the thickness of the gate electrode material 550, exposing the top of the isolation structure 400.

By exposing the remaining gate electrode material 550 to the top of the isolation structure 400, process preparation is provided for subsequent polishing, and subsequent process difficulty is reduced.

In this embodiment, the pretreatment is performed by chemical mechanical polishing. By adopting the mode of chemical mechanical polishing, after the pretreatment is finished, the subsequent first polishing treatment can be carried out under the condition of the same equipment, so that the manufacturing efficiency is favorably improved, and the process risk is favorably reduced.

In other embodiments, the pretreatment may be performed by etching back, or by a combination of etching back and chemical mechanical polishing.

In other embodiments, the pretreatment may not be performed according to the distance from the top of the gate electrode material to the top of the isolation structure after the gate electrode material is formed.

Accordingly, with continued reference to fig. 14, embodiments of the present invention further provide a semiconductor structure formed by the foregoing forming method.

The semiconductor structure includes: a substrate 100; a gate electrode layer 500 on the substrate 100; the interlayer dielectric layer 400 is positioned on the substrate 100 where the gate electrode layer 500 is exposed, and the interlayer dielectric layer 400 covers the side wall of the gate electrode layer 500 and exposes the top of the gate electrode layer 500; and the isolation structure 400 is positioned in the interlayer dielectric layer 300 between the adjacent gate electrode layers 500 and extends into the substrate 100 with partial thickness.

In the semiconductor structure, the probability that a metal residue (i.e., a material residue of the gate electrode layer 500) is formed on the top of the interlayer dielectric layer 300 is low, thereby improving the performance of the semiconductor device.

For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.