阅读说明：本技术 多通道环栅晶体管 (Multi-channel gate-all-around transistor ) 是由 刘强 俞文杰 任青华 陈治西 刘晨鹤 赵兰天 陈玲丽 王曦 于 2019-01-11 设计创作，主要内容包括：本发明提供一种多通道环栅晶体管,包括：半导体衬底；绝缘层,其具有未贯穿所述绝缘层的凹槽；半导体纳米线结构,悬空并横跨于凹槽上,包括位于凹槽两侧的半导体凸台以及连接于凸台上的多根半导体纳米线；栅介质层及栅电极层,包围于半导体纳米线；源区及漏区,形成于半导体纳米线的端部以及半导体凸台,凸台之间的多根半导体纳米线共同形成多通道的沟道区；以及源电极及漏电极。本发明的多通道环栅晶体管下方的凹槽宽度小于半导体纳米线的宽度,可有效避免底层栅与源漏之间不必要的交叠区,降低沟道中的载流子的散射,降低源漏寄生电容,提高器件高频特性。本发明的环栅晶体管具有多个通道,可大大提高晶体管的驱动功率,提高器件的集成度。(The invention provides a multi-channel gate-all-around transistor, comprising: a semiconductor substrate; an insulating layer having a groove that does not penetrate the insulating layer; the semiconductor nanowire structure is suspended and stretches across the groove and comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the bosses; the gate dielectric layer and the gate electrode layer are wrapped around the semiconductor nanowire; the source region and the drain region are formed at the end parts of the semiconductor nanowires and the semiconductor bosses, and a plurality of semiconductor nanowires among the bosses form a multi-channel region together; and a source electrode and a drain electrode. The width of the groove below the multi-channel ring gate transistor is smaller than that of the semiconductor nanowire, so that an unnecessary overlapping region between a bottom gate and a source drain can be effectively avoided, the scattering of current carriers in a channel is reduced, the parasitic capacitance of the source drain is reduced, and the high-frequency characteristic of a device is improved. The gate-all-around transistor provided by the invention has a plurality of channels, so that the driving power of the transistor can be greatly improved, and the integration level of the device is improved.)

1. A multi-channel gate-all-around transistor, comprising:

a semiconductor substrate;

the insulating layer is provided with a groove, and the groove does not penetrate through the insulating layer;

the semiconductor nanowire structure is suspended and stretches across the groove, and comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses;

the gate dielectric layer surrounds the surfaces of the plurality of semiconductor nanowires and exposes two end parts of the semiconductor nanowires;

the gate electrode layer surrounds the surface of the gate dielectric layer;

the source region and the drain region are formed at two end parts of the plurality of semiconductor nanowires and the semiconductor bosses, and the plurality of semiconductor nanowires between the source region and the drain region jointly form a multi-channel region;

and source and drain electrodes formed on the source and drain regions.

2. The multi-channel gate-all-around transistor of claim 1, wherein: the thickness of the insulating layer is not more than 150 nanometers, and the depth of the groove is not more than 50 nanometers.

3. The multi-channel gate-all-around transistor of claim 1, wherein: the width of the groove is less than the length of the semiconductor nanowire.

4. The multi-channel gate-all-around transistor of claim 1, wherein: the multichannel ring grid transistor comprises a junction field effect transistor, wherein a source region and a drain region are doped with a first conduction type, a channel region of the multichannel ring grid transistor is doped with a second conduction type, and the first conduction type is opposite to the second conduction type.

5. The multi-channel gate-all-around transistor of claim 4, wherein: the first conductive type is a P type, the second conductive type is an N type, or the first conductive type is an N type, and the second conductive type is a P type.

6. The multi-channel gate-all-around transistor of claim 1, wherein: the multichannel gate-all-around transistor comprises a junction-free field effect transistor, wherein the source region, the drain region and the multichannel channel region have the same conductive type doping.

7. The multi-channel gate-all-around transistor of claim 6, wherein: the source region, the drain region and the multichannel channel region are all doped in an N type mode or the source region, the drain region and the multichannel channel region are all doped in a P type mode.

8. The multi-channel gate-all-around transistor of claim 1, wherein: the semiconductor nanowire structure comprises a plurality of semiconductor nanowire structures stacked upwards, the nanowire structures comprise semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses, and the two adjacent semiconductor bosses are spaced by the sacrificial layer bosses, so that the two adjacent semiconductor nanowires are spaced.

9. The multi-channel gate-all-around transistor of claim 8, wherein: the distance between the two adjacent semiconductor nanowires is larger than 2 times of the thickness of the gate dielectric layers, so that a gap is formed between the two adjacent gate dielectric layers, and the gate electrode layers are filled in the gap.

10. The multi-channel gate-all-around transistor of claim 8, wherein: the distance between two adjacent semiconductor nanowires is smaller than or equal to 2 times of the thickness of the gate dielectric layer, so that the two adjacent gate dielectric layers are connected, and the gate electrode layer surrounds the outer side of the gate dielectric layer.

11. The multi-channel gate-all-around transistor of claim 1, wherein: the number of the semiconductor nanowires connected to each semiconductor boss is not less than 3.

12. The multi-channel gate-all-around transistor of claim 1, wherein: the material of the semiconductor nanowire comprises one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide and indium phosphide.

Technical Field

The invention belongs to the field of semiconductor integrated circuit design and manufacture, and particularly relates to a multi-channel gate-all-around transistor and a preparation method thereof.

Background

With the continuous scaling of microelectronic devices, it is expected that the existing FinFET technology will face a larger technical bottleneck at the 5 nm and 3 nm nodes, and the device performance is no longer greatly improved with the continuous reduction of the device size. There is a need for new device technologies, such as new device materials (e.g., strained silicon, silicon germanium, iii-v semiconductors, etc.), and new device structures (e.g., nanowire ring-gate transistors, etc.).

The nanowire gate-all-around transistor can limit a conducting channel to the center of the nanowire instead of the interface of the nanowire and the gate oxide layer, so that scattering of current carriers is greatly reduced, and the nanowire gate-all-around transistor is expected to be an important future development direction and further continues the development of the Mole's law.

The nanowire ring gate transistor has various preparation schemes, and one simple preparation method is to etch a hollow nanowire structure based on an SOI substrate and prepare a corresponding ring gate transistor. Fig. 1 to 12 show a method for manufacturing a representative nanowire gate-all-around transistor, in which fig. 2 shows a schematic cross-sectional structure at a-a 'of fig. 1, fig. 3 shows a schematic cross-sectional structure at B-B' of fig. 1, and fig. 4 to 12 have the same correspondence. The method mainly comprises the following steps:

as shown in fig. 1 to fig. 3, step 1) is performed to provide an SOI substrate, where the SOI substrate includes a silicon substrate 101, an oxide layer 102, and a top silicon layer 103, and a silicon nanowire 104 is etched in the top silicon layer 103 and the oxide layer 102 through a photolithography process and an etching process;

as shown in fig. 4 to 6, step 2) is performed, and the oxide layer 102 under the silicon nanowire is removed by wet etching to form a hollow hole 105;

as shown in fig. 7 to 9, step 3) is performed to thin the silicon nanowire;

as shown in fig. 10 to 12, step 4) is performed to sequentially deposit a gate dielectric layer 106 and a gate electrode 107 to form a gate-all-around transistor.

The above solution has the following disadvantages:

firstly, when the nanowire structure is etched in step 1), the top silicon of the adjacent region of the nanowire and a part of the silicon oxide under the top silicon need to be etched away. As shown in fig. 2, during the etching process, it is necessary to keep the oxide layer 102 from being etched through, and the remaining silicon oxide layer can still keep a certain thickness to prevent a large parasitic capacitance or breakdown between the gate electrode and the substrate electrode (as shown by 108 in fig. 11) as shown in fig. 11, which brings a certain requirement to the accuracy of the etching process.

Secondly, in order to prepare the silicon nanowire with the suspended structure, the oxide layer under the nanowire needs to be etched, and a wet etching is usually adopted, but since the wet etching is an isotropic etching, a part of the silicon oxide in the exposed region except under the silicon nanowire is also etched, and an unnecessary concave cavity 109 is formed, as shown in fig. 8.

This concave cavity can have the following adverse effects:

as shown in fig. 13 and 14, wherein fig. 13 is a top view of the cross section at C-C' of fig. 11, and fig. 14 is an enlarged schematic view of the dashed frame of fig. 13, the concave cavity is finally filled with the gate dielectric layer 106 and the gate electrode 107, in order to ensure good step coverage, the gate dielectric layer 106 and the gate electrode 107 are generally prepared by using a L D process, but even in the a L D process, when a semi-closed structure with concavity is filled, the film-to-film contact interconnection is easily advanced during the process of filling the plating film, and finally a closed cavity in the gate metal is formed in the concave structure, instead of being completely filled.

As shown in fig. 8, 13 and 14, the corresponding concave cavity 109 in fig. 8 is also filled with the gate dielectric layer 106 and the gate electrode 107, so that the gate electrode under the nanowire is longer than the gate electrode above the nanowire. This results in: an unnecessary overlapping area is arranged between the bottom layer gate and the source drain, a silicon channel in the area is influenced by asymmetric gate potential, and current carriers in the silicon channel are scattered to a certain extent; the resistance between the gate electrode and the source-drain electrode becomes large; the source-drain parasitic capacitance becomes large, and the high-frequency characteristic of the device becomes poor; when the silicon channel of the overlapping region is heavily doped, hot electrons are easily generated between the bottom gate and the silicon channel of the overlapping region, the gate leakage current is increased, and the gate oxide is broken down.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a multi-channel gate-all-around transistor, which is used to solve the problems of the prior art that the gate-all-around transistor has large parasitic capacitance, is easy to break down, and has low driving power.

To achieve the above and other related objects, the present invention provides a multi-channel gate-all-around transistor, comprising: a semiconductor substrate; the insulating layer is provided with a groove, and the groove does not penetrate through the insulating layer; the semiconductor nanowire structure is suspended and stretches across the groove, and comprises semiconductor bosses positioned on two sides of the groove and a plurality of semiconductor nanowires connected to the semiconductor bosses; the gate dielectric layer surrounds the surfaces of the plurality of semiconductor nanowires and exposes two end parts of the semiconductor nanowires; the gate electrode layer surrounds the surface of the gate dielectric layer; the source region and the drain region are formed at two end parts of the plurality of semiconductor nanowires and the semiconductor bosses, and the plurality of semiconductor nanowires between the source region and the drain region jointly form a multi-channel region; and source and drain electrodes formed on the source and drain regions.

Optionally, the thickness of the insulating layer is not greater than 150 nm, and the depth of the groove is not greater than 50 nm.

Optionally, a width of the groove is less than a length of the semiconductor nanowire.

Optionally, the multichannel ring-gate transistor includes a junction field effect transistor, wherein the source region and the drain region are doped with a first conductivity type, the channel region of the multichannel is doped with a second conductivity type, and the first conductivity type is opposite to the second conductivity type.

Optionally, the first conductivity type is a P type, the second conductivity type is an N type, or the first conductivity type is an N type, and the second conductivity type is a P type.

Optionally, the multichannel gate-all-around transistor includes a junction-less field effect transistor, wherein the source region, the drain region and the channel region of the multichannel have the same conductivity type doping.

Optionally, the source region, the drain region, and the multichannel channel region are all doped in an N-type manner or the source region, the drain region, and the multichannel channel region are all doped in a P-type manner.

Optionally, the semiconductor nanowire structure comprises a plurality of semiconductor nanowire structures stacked upwards, each nanowire structure comprises semiconductor bosses located on two sides of the corresponding groove and a plurality of semiconductor nanowires connected to the corresponding semiconductor bosses, and two adjacent semiconductor bosses are spaced by a sacrificial layer boss, so that two adjacent semiconductor nanowires are spaced.

Optionally, the distance between two adjacent semiconductor nanowires is greater than 2 times the thickness of the gate dielectric layer, so that a gap is formed between the two adjacent gate dielectric layers, and the gate electrode layer is filled in the gap.

Optionally, the distance between two adjacent semiconductor nanowires is less than or equal to 2 times the thickness of the gate dielectric layer, so that the two adjacent gate dielectric layers are connected, and the gate electrode layer surrounds the outer side of the gate dielectric layer.

Optionally, the number of the semiconductor nanowires to which each of the semiconductor mesas is connected is not less than 3.

Optionally, the material of the semiconductor nanowire comprises one of silicon, germanium, silicon germanium, gallium nitride, aluminum nitride, gallium arsenide, silicon carbide, zinc oxide, gallium oxide, and indium phosphide.

As described above, the multi-channel gate-all-around transistor of the present invention has the following beneficial effects:

1) the width of the groove below the multi-channel ring gate transistor is smaller than that of the semiconductor nanowire, so that an unnecessary overlapping region between a bottom gate and a source drain can be effectively avoided, the scattering of current carriers in a channel is reduced, the parasitic capacitance of the source drain is reduced, and the high-frequency characteristic of a device is improved.

2) The gate-all-around transistor provided by the invention has a plurality of channels, so that the driving power of the transistor can be greatly improved, and the integration level of the device is improved.

3) The multi-channel gate-all-around transistor can form a three-dimensional stacked structure, and can further improve the integration level of devices.

4) The gate-all-around transistor has the advantages of smaller subthreshold slope, smaller off-state current density, larger on-state current density, good high-frequency characteristic and good radiation resistance, and is particularly suitable for integrated circuits, sensors, memories and the like with low power consumption, high frequency and high reliability. Because the channel region is completely surrounded by the gate structure, the transistor has good single event effect resistance and total dose effect resistance at the same time, and is suitable for aerospace electronic chips.

Drawings

Fig. 1 to 14 are schematic structural diagrams showing steps of a method for manufacturing a nanowire wrap-around transistor in the prior art.

Fig. 15 to 17 are schematic structural diagrams of a multi-channel gate-all-around transistor in embodiment 1 of the present invention.

Fig. 18 to fig. 22 are schematic structural diagrams of a multi-channel gate-all-around transistor in embodiment 2 of the present invention.

Description of the element reference numerals

201 semiconductor substrate

202 insulating layer

600 channel region

601 gate dielectric layer

602 gate electrode layer

603 source region

604 drain region

605 source electrode

606 drain electrode

607 passivation layer

608 sacrificial layer boss

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 15-22. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.