阅读说明：本技术 高压元件及其制造方法 (High voltage device and method for manufacturing the same ) 是由 黄宗义 于 2019-01-11 设计创作，主要内容包括：本发明提出一种高压元件及其制造方法。高压元件用于切换式电源供应电路的功率级中,用以作为下桥开关。高压元件包含至少一横向扩散金属氧化物半导体元件以及至少一肖特基势垒二极管。其中横向扩散金属氧化物半导体包括阱区、本体区、栅极、源极以及漏极；肖特基势垒二极管包括肖特基金属层以及肖特基半导体层。其中,肖特基金属层与源极电连接,且肖特基半导体层与阱区邻接。(The invention provides a high-voltage element and a manufacturing method thereof. The high-voltage element is used in a power stage of a switching power supply circuit and is used as a lower bridge switch. The high voltage device includes at least one LDMOS device and at least one Schottky barrier diode. The transverse diffusion metal oxide semiconductor comprises a well region, a body region, a grid electrode, a source electrode and a drain electrode; the Schottky barrier diode includes a Schottky metal layer and a Schottky semiconductor layer. The Schottky metal layer is electrically connected with the source electrode, and the Schottky semiconductor layer is adjacent to the well region.)

1. A high voltage device used in a power stage of a switching power supply circuit as a lower bridge switch, comprising:

at least one LDMOS device, comprising:

a well region of a first conductivity type formed in a semiconductor layer;

a body region of a second conductivity type formed in the well region;

a gate formed above the well region and connected to the well region; and

a source and a drain of the first conductivity type in the body region and the well region respectively under different sides of the gate; and

at least one schottky barrier diode, comprising:

a Schottky metal layer formed on the semiconductor layer and electrically connected with the source electrode; and

a Schottky semiconductor layer formed in the semiconductor layer, wherein the Schottky semiconductor layer forms a Schottky contact with the Schottky metal layer, and the Schottky semiconductor layer is adjacent to the well region;

wherein a portion of the body region directly below the gate between the source and a boundary of the body region defines an inversion region for serving as an inversion current channel of the LDMOS device in a turn-on operation;

wherein a drift region is defined by a portion of the well region between the body region and the drain to serve as a drift current channel of the LDMOS device during the turn-on operation.

2. The high voltage device of claim 1, wherein the high voltage device is formed by a basic unit having a mirror layout, wherein the basic unit comprises:

at least part of the Schottky barrier diode; and

at least part of the LDMOS devices are arranged in series in a way of mutual mirror image arrangement in a channel direction to form a power device string when the plurality of LDMOS devices are multiple;

the Schottky barrier diode is adjacent to the power element string in the channel direction.

3. The high voltage device of claim 1, wherein the high voltage device is formed by a basic unit having a mirror layout, wherein the basic unit comprises:

at least one of the Schottky barrier diodes; and

at least part of the LDMOS devices are arranged in series in a way of mutual mirror image arrangement in a channel direction when the plurality of LDMOS devices are multiple;

the number of the Schottky barrier diodes is not more than that of the LDMOS elements, each Schottky barrier diode is located between the body region and the drain electrode of the corresponding LDMOS element, and the Schottky semiconductor layer is connected with the drift region.

4. The high-voltage device as claimed in claim 1, wherein the at least one Schottky barrier diode is located in an isolation region of the high-voltage device, and the isolation region is located outside the at least one laterally diffused metal oxide semiconductor.

5. The high voltage device as claimed in any one of claims 1 to 4, wherein the Schottky barrier diode further comprises two insulating structures respectively located outside both sides of the Schottky metal layer, connected to the Schottky semiconductor layer, and separated by a Schottky channel.

6. The high voltage device as claimed in claim 5, wherein said Schottky barrier diode further comprises two channel side well regions of said second conductivity type respectively located in said Schottky semiconductor layer under both sides of said Schottky metal layer and separated by said Schottky channel.

7. The high voltage device as claimed in claim 5, wherein the Schottky barrier diode further comprises two channel-side body regions of the second conductivity type in the Schottky semiconductor layer under both sides of the Schottky metal layer, respectively, separated by the Schottky channel, wherein the channel-side body regions and the body regions are formed by the same process steps.

8. The high voltage device as claimed in claim 7, wherein the Schottky barrier diode further comprises two channel side body electrodes of the second conductivity type respectively located in the two channel side body regions and separated by the Schottky channel.

9. The high voltage device as claimed in claim 7, wherein the Schottky barrier diode further comprises two polysilicon layers respectively disposed on the two channel-side body regions, and the polysilicon layers are separated from the corresponding channel-side body regions by the corresponding insulating structures.

10. The high voltage device of claim 1, wherein the LDMOS further comprises a drift oxide region formed over the drift region, the drift oxide region comprising a local oxide structure, a shallow trench isolation structure, or a CVD oxide region.

11. The high voltage device of claim 1, wherein the gate comprises:

a dielectric layer formed on the body region and the well region and connected to the body region and the well region;

a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and

a spacer layer formed on both sides of the conductive layer as an electrical insulation layer on both sides of the gate.

12. A method for manufacturing a high voltage device used in a power stage of a switching power supply circuit as a bottom bridge switch, the method comprising:

forming at least one LDMOS device, the LDMOS device being formed by:

forming a well region in a semiconductor layer, the well region having a first conductivity type;

forming a body region in the well region, the body region having a second conductivity type;

forming a gate over and connected to the well region; and

forming a source and a drain in the body region and the well region respectively under different sides of the gate, the source and the drain having the first conductivity type; and

forming at least one schottky barrier diode element, the step of forming the schottky barrier diode comprising:

forming a Schottky metal layer on the semiconductor layer, wherein the Schottky metal layer is electrically connected with the source electrode; and

forming a Schottky semiconductor layer in the semiconductor layer, wherein the Schottky semiconductor layer and the Schottky metal layer form a Schottky contact, and the Schottky semiconductor layer is adjacent to the well region;

wherein a portion of the body region directly below the gate between the source and a boundary of the body region defines an inversion region for serving as an inversion current channel of the LDMOS device in a turn-on operation;

wherein a drift region is defined by a portion of the well region between the body region and the drain to serve as a drift current channel of the LDMOS device during the turn-on operation.

13. The method of claim 12, wherein the high voltage device is formed by a basic unit having a mirror layout, wherein the basic unit comprises:

at least part of the Schottky barrier diode; and

at least part of the LDMOS devices are arranged in series in a way of mutual mirror image arrangement in a channel direction to form a power device string when the plurality of LDMOS devices are multiple;

the Schottky barrier diode is adjacent to the power element string in the channel direction.

14. The method of claim 12, wherein the high voltage device is formed by a basic unit having a mirror layout, wherein the basic unit comprises:

at least one of the Schottky barrier diodes; and

at least part of the LDMOS devices are arranged in series in a way of mutual mirror image arrangement in a channel direction when the plurality of LDMOS devices are multiple;

the number of the Schottky barrier diodes is not more than that of the LDMOS elements, each Schottky barrier diode is located between the body region and the drain electrode of the corresponding LDMOS element, and the Schottky semiconductor layer is connected with the drift region.

15. The method according to claim 12, wherein said at least one schottky barrier diode is located in an isolation region of said high voltage device, said isolation region being located outside said at least one ldmos.

16. The method for manufacturing a high-voltage device according to any one of claims 12 to 15, wherein the step of forming the schottky barrier diode further comprises: and forming two insulation structures which are respectively positioned outside two sides of the Schottky metal layer, connected to the Schottky semiconductor layer and separated by a Schottky channel.

17. The method of claim 16, wherein the step of forming the schottky barrier diode further comprises: and forming two channel side well regions with the second conductivity type, which are respectively positioned in the Schottky semiconductor layer below two sides of the Schottky metal layer and are separated by the Schottky channel.

18. The method of claim 16, wherein the step of forming the schottky barrier diode further comprises: and forming two channel-side body regions of the second conductivity type in the Schottky semiconductor layer respectively below the two sides of the Schottky metal layer and separated by the Schottky channel, wherein the channel-side body regions and the body regions are formed by the same process steps.

19. The method of claim 18, wherein the step of forming the schottky barrier diode further comprises: two channel side body electrodes of the second conductivity type are formed in the two channel side body regions, respectively, and separated by the schottky channel.

20. The method of claim 18, wherein the step of forming the schottky barrier diode further comprises: and forming two polysilicon layers respectively located on the two channel side body regions, wherein the polysilicon layers are separated from the corresponding channel side body regions by the corresponding insulation structures.

21. The method of claim 12, further comprising forming a drift oxide region over the drift region, the drift oxide region comprising a local oxide structure, a shallow trench isolation structure, or a chemical vapor deposition oxide region.

22. The method of claim 12, wherein the step of forming the gate comprises:

forming a dielectric layer on the body region and the well region and connecting the body region and the well region;

forming a conductive layer on all the dielectric layers and connected to the dielectric layers to serve as an electrical contact of the gate; and

forming a spacer layer on two sides of the conductive layer as the electrical insulation layer on two sides of the gate.

Technical Field

The present invention relates to a high voltage device and a method for manufacturing the same, and more particularly, to a high voltage device and a method for manufacturing the same, which can improve an operation speed and a safe operation area.

Background

Fig. 1A shows a circuit diagram of a typical switching power supply circuit, which includes a control circuit 1 and a power stage circuit 2. as shown in the figure, the power stage circuit 2 includes a high voltage device 11 as an upper bridge switch and a high voltage device 12 as a lower bridge switch, which are respectively operated according to an upper bridge signal UG and a lower bridge signal L G to convert an input voltage Vin into an output voltage Vout, and generate an inductor current I L on an inductor 13 of the power stage circuit 2.

Fig. 1B shows a schematic cross-sectional view of a high voltage element 12 used as a lower bridge switch. The high voltage element 12 is shown as acting as a down bridge switch. The high voltage device 12 means that the voltage applied to the drain electrode 129 is higher than 5V during normal operation. Generally, the drain 129 and the body 125 of the high voltage device 12 have a drift region 122a (indicated by the dashed line in fig. 1B) separating the drain 129 from the body 125, and the length of the drift region in the channel direction (indicated by the dashed line arrow in fig. 1B) is adjusted according to the operating voltage applied to the high voltage device 12 during operation. As shown in fig. 1B, the high voltage element 12 includes: well region 122, drift oxide region 124, body region 125, body electrode 126, gate 127, source 128, and drain 129. The well 122, which has an N-type conductivity, is formed on the substrate 121, and the gate 127 covers a portion of the drift oxide 124.

When the high-voltage device 12 operates, the parasitic diode formed by the body region 125 and the well region 122 (as indicated by the dashed diode circuit symbol in the figure) is not turned on during the idle period before the lower bridge switch is turned on due to the continuity of the inductor current I L flowing through the inductor 13, but the parasitic diode L D is turned on, and the phase node voltage L X of the phase node PH is lower than the forward voltage (forward voltage) of the parasitic diode L D at the ground potential GND, so that the parasitic diode L D is formed by the body region 125 and the well region 122, and the reverse recovery time (trr) thereof limits the operating speed of the high-voltage device 12 and also limits the safe operating area (safe operating area, SOA), wherein the definition of the safe operating area is well known by those skilled in the art and is not repeated herein.

Accordingly, the present invention is directed to a high voltage device and a method for manufacturing the same, which can improve the operation speed and the safe operation area, and thus improve the application range.

Disclosure of Invention

In one aspect, the present invention provides a high voltage device for use in a power stage of a switching power supply circuit as a bottom bridge switch, comprising at least one laterally diffused Metal Oxide Semiconductor (L DMOS) device including a well region of a first conductivity type formed in a Semiconductor layer, a body region of a second conductivity type formed in the well region, a gate formed over and connected to the well region, and a source and a drain of the first conductivity type formed in the body region and in the well region respectively under different sides of the gate, and at least one Schottky Barrier Diode (SBD) comprising a Schottky Metal layer formed on the Semiconductor layer, the Schottky Metal layer electrically connected to the source, and a Schottky Semiconductor layer formed in the Semiconductor layer, the Schottky barrier diode layer contacting the Semiconductor layer and the Schottky barrier diode layer, wherein a lateral diffusion Metal Oxide Semiconductor layer is formed in the well region, wherein a lateral diffusion Metal Oxide Semiconductor layer is in contact with the Semiconductor layer, a lateral diffusion Metal Oxide Semiconductor layer is in contact with the well region, and a lateral diffusion Metal Oxide Semiconductor layer is in contact with the Schottky barrier diode, wherein a lateral diffusion Metal Oxide layer is used to define a lateral diffusion Metal Oxide layer, and a lateral diffusion Metal Oxide layer is used to conduct a drift region between the Schottky barrier diode and a lateral diffusion Metal Oxide layer.

From another aspect, the present invention provides a method of forming a high voltage device for use in a power stage of a switching power supply circuit as a bottom bridge switch, the method comprising forming at least one laterally Diffused Metal Oxide Semiconductor (L DMOS) element including forming a well region of a first conductivity type in a Semiconductor layer, forming a body region of a second conductivity type in the well region, forming a gate over and connected to the well region, and forming a source and a drain in the body region and in the well region on different sides of the gate, respectively, the source and drain having the first conductivity type, and forming at least one Schottky diode (SBD) element, the forming of the Schottky diode including forming a Schottky barrier Metal layer on the Schottky barrier Metal layer, the Schottky barrier Metal layer being electrically connected to the Semiconductor layer, the source and drain being electrically connected to the Schottky barrier Metal layer, the Schottky barrier Metal layer being electrically connected to the Semiconductor layer, the Schottky barrier Metal layer being formed in the well region, and the Schottky barrier Metal layer, wherein the Schottky barrier Metal layer is electrically connected to the Schottky barrier Metal layer, and the Schottky barrier Metal layer is formed in the Schottky barrier Metal layer, wherein the Schottky barrier Metal layer is electrically connected to the Schottky barrier Metal layer, and the Schottky barrier Metal layer is formed in the lateral channel region, wherein the Schottky barrier element is formed in the lateral channel region and the lateral channel region.

In a preferred embodiment, the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises: at least part of the Schottky barrier diode; and at least part of the LDMOS devices, wherein when the plurality of LDMOS devices are provided, the plurality of LDMOS devices are alternately arranged in a mirror image manner in series in a channel direction to form a power device string; the Schottky barrier diode is adjacent to the power element string in the channel direction.

In a preferred embodiment, the high voltage device is formed by a basic unit after mirror image layout, wherein the basic unit comprises: at least one of the Schottky barrier diodes; and at least part of the LDMOS devices, wherein when the plurality of LDMOS devices are provided, the plurality of LDMOS devices are alternately arranged in a mirror-image manner in series in a channel direction; the number of the Schottky barrier diodes is not more than that of the LDMOS elements, each Schottky barrier diode is located between the body region and the drain electrode of the corresponding LDMOS element, and the Schottky semiconductor layer is connected with the drift region.

In a preferred embodiment, the at least one schottky barrier diode is located in an isolation region of the high voltage device, and the isolation region is located outside the at least one ldmos.

In a preferred embodiment, the schottky barrier diode further includes two insulating structures respectively located outside of two sides of the schottky metal layer, connected to the schottky semiconductor layer, and separated by a schottky channel.

In a preferred embodiment, the schottky barrier diode further comprises two channel-side well regions of the second conductivity type respectively located in the schottky semiconductor layer under both sides of the schottky metal layer and separated by the schottky channel.

In a preferred embodiment, the schottky barrier diode further comprises two channel-side body regions of the second conductivity type respectively located in the schottky semiconductor layer under both sides of the schottky metal layer and separated by the schottky channel, wherein the channel-side body regions and the body regions are formed by the same process step.

In the aforementioned embodiments, the schottky barrier diode preferably further comprises two channel-side body electrodes of the second conductivity type respectively located in the two channel-side body regions and separated by the schottky channel.

In the aforementioned embodiments, the schottky barrier diode preferably further includes two polysilicon layers respectively located on the two channel-side body regions, and the polysilicon layers and the corresponding channel-side body regions are separated by the corresponding insulating structures.

In a preferred embodiment, the laterally diffused metal oxide semiconductor further includes a drift oxide region formed on the drift region, the drift oxide region including a local oxidation of silicon (L OCOS) structure, a Shallow Trench Isolation (STI) structure, or a Chemical Vapor Deposition (CVD) oxide region.

In a preferred embodiment, the gate includes: a dielectric layer formed on the body region and the well region and connected to the body region and the well region; a conductive layer, which is used as an electrical contact of the grid electrode, is formed on all the dielectric layers and is connected with the dielectric layers; and a spacer layer formed on both sides of the conductive layer as electrical insulation layers on both sides of the gate.

The purpose, technical content, features and effects of the invention will be more easily understood through the following detailed description of specific embodiments.

Drawings

Fig. 1A shows a circuit diagram of a typical switching power supply circuit.

Fig. 1B shows a schematic cross-sectional view of a prior art high voltage component 12 used as a lower bridge switch.

Fig. 2 shows a first embodiment of the invention.

Fig. 3 shows a second embodiment of the invention.

Fig. 4A-4C show a third embodiment of the invention.

Fig. 5A-5B show a fourth embodiment of the present invention.

Fig. 6A-6B show a fifth embodiment of the present invention.

Fig. 7 shows a sixth embodiment of the invention.

Fig. 8 shows a seventh embodiment of the invention.

Fig. 9 shows an eighth embodiment of the present invention.

Fig. 10A-10G show a ninth embodiment of the invention.

Description of the symbols in the drawings

1 control circuit

2 power stage circuit

11, 12, 22, 32, 42, 52, 62 high voltage element

13 inductor

121, 221, 321, 421, 521, 621, 721, 821, 921 substrate

122, 222, 322, 422, 522, 622 well regions

122a, 222a, 322a, 422a, 522a, 622a drift region

124, 224, 324, 424, 524, 624 drift oxide regions

125, 225, 325, 425, 525, 625 body regions

126, 226, 326, 426, 526, 626 body pole

127, 227, 327, 427, 527, 627, 935 gate

128, 228, 328, 428, 528, 628 source

129, 229, 329, 429, 529, 629 drain

221 ', 321', 421 ', 521', 621 ', 721', 821 ', 921' semiconductor layer

221a, 321a, 421a, 521a, 621a

221b, 321b, 421b, 521b, 621b lower surface

223, 323, 423, 523, 623 silicide layers

223a, 623a inversion region

231, 331, 431, 531, 631, 731, 831, 931 schottky metal layer

232, 332, 432, 532, 632, 732, 832, 932 Schottky semiconductor layer

233, 333, 633, 733, 833 insulation structure

234, 334, 434, 534, 634, 735, 836, 937 schottky channels

734 channel side well region

834, 934 channel-side body region

835 polycrystalline silicon layer

2251, 2261, 2281 photoresist layer

2271, 3271, 4271, 5271, 6271, 9351 dielectric layer

2272, 3272, 4272, 5272, 6272, 9352 conductive layer

2273, 3273, 4273, 5273, 6273, 9353 spacer layer

2281 lightly doped region

AA ', BB', CC ', FF', Axis

CE LL L DMOS component region

Tangent line DD ', EE' GG

GND ground potential

I L inductive current

IMP1, IMP2, IMP3 and IMP4 ion implantation process steps

ISO isolation region

L D parasitic diode

L G lower bridge signal

L T, L T', L0T 1, L1T 2, L T3, L T4, L T5, L T6, L T7, L T8, L T9L DMOS cell

L X phase node voltage

Basic units of M1, M1 ', M2, M2 ', M3, M3 ', M4 and M4

M L, M L', M L1, M L2, M L3 metal wire

PDS power element string

PH phase node

SD, SD', SD1, SD2, SD3, SD4, SD5, SD6, SD7 Schottky barrier diode

UG upper bridge signal

Vin input voltage

Vout output voltage

Detailed Description

The foregoing and other technical and scientific aspects, features and advantages of the present invention will be apparent from the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings. The drawings in the present invention are schematic and are intended to show the process steps and the up-down order of the layers, and the shapes, thicknesses and widths are not drawn to scale.

Referring to fig. 2, a cross-sectional view of a high voltage device 22 used as a bottom bridge switch in a power stage of a switching power supply circuit is shown in fig. 2. as shown in fig. 2, the high voltage device 22 includes L laterally Diffused Metal Oxide Semiconductor (L DMOS) devices L T and L T 'and Schottky Barrier Diode (SBD) SD and SD' L DMOS devices L T including a well 222, a drift Oxide 224, a body 225, a body 226, a gate 227, a source 228 and a drain 229.

The semiconductor layer 221 'is formed on the substrate 221, and the semiconductor layer 221' has an upper surface 221a and a lower surface 221b opposite to each other in a vertical direction (as indicated by a solid arrow in fig. 2, the same applies below). The substrate 221 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 221 'is formed on the substrate 221, for example, by an epitaxial process, or a portion of the substrate 221 is used as the semiconductor layer 221'. The manner of forming the semiconductor layer 221' is well known to those skilled in the art and will not be described herein.

Continuing with fig. 2, a drift oxide region 224 is formed on the top surface 221a and connected to the top surface 221a, and is located right above a portion of the drift region 222a (as indicated by the dashed box in L DMOS L T in fig. 2) and connected to the drift region 222 a. the drift oxide region 224 is, for example, but not limited to, a local oxidation of silicon (L OCOS) structure as shown in the figure, and may also be a Shallow Trench Isolation (STI) structure.

The well 222 of the first conductivity type is formed in the semiconductor layer 221', and the well 222 is located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. The well region 222 is formed by at least one ion implantation process step, for example. The body region 225 of the second conductivity type is formed in the well 222, and the body region 225 is located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. Body electrode 226 has a second conductivity type for serving as an electrical contact for body region 225. in the vertical direction, body electrode 226 is formed below upper surface 221a and is connected to body region 225 at upper surface 221 a. The gate 227 is formed on the upper surface 221a of the semiconductor layer 221', and a portion of the body region 225 is located directly below the gate 227 and connected to the gate 227 in the vertical direction to provide an inversion region 223a of the high voltage device 22 during the turn-on operation, and the inversion region 223a is located directly below a portion of the gate 227 and connected to the gate 227.

Referring to fig. 2, the source 228 and the drain 229 have a first conductivity type, and in the vertical direction, the source 228 and the drain 229 are formed under the upper surface 221a and connected to the upper surface 221a, and the source 228 and the drain 229 are respectively located in the body region 225 under the gate 227 in the channel direction (as indicated by the dashed arrow in the figure, the same below), and in the well region 222 away from the body region 225, and in the channel direction, the drift region 222a is located between the drain 229 and the body region 225 and in the well region 222 close to the upper surface 221a, so as to serve as a drift current channel of the L DMOS L T in the turn-on operation.

It should be noted that the inversion region 223a refers to a region where an inversion layer (inversion layer) is formed below the gate 227 so that an on-current passes through the region between the source 228 and the drift region 222a due to a voltage applied to the gate 227 in the on operation of the L DMOS device L T, which is well known to those skilled in the art and is not described herein, and so on for other embodiments of the present invention.

It should be noted that the first conductivity type and the second conductivity type can be P-type or N-type, and when the first conductivity type is P-type, the second conductivity type is N-type; when the first conductive type is N type, the second conductive type is P type.

It should be noted that the drift current path refers to a region through which the on current passes in a drift manner during the on operation of the high voltage device 200, which is well known to those skilled in the art and will not be described herein.

Note that the upper surface 221a does not mean a completely flat plane, but means a surface of the semiconductor layer 221'. In the present embodiment, for example, the upper surface 221a of the portion of the drift oxide region 224 in contact with the semiconductor layer 221' has a depressed portion.

In a preferred embodiment, the gate 227 includes a dielectric layer 2271 connected to the upper surface, a conductive layer 2272 with conductivity, and a spacer 2273 with electrical insulation properties. The dielectric layer 2271 is formed on the body region 225 and the well region 222, and is connected to the body region 225 and the well region 222. The conductive layer 2272 is used as an electrical contact for the gate 227, and is formed on all of the dielectric layers 2271 and connected to the dielectric layers 2271. Spacer 2273 is formed on both sides of conductive layer 2272 to serve as an electrical insulation layer on both sides of gate 227.

In addition, it should be noted that the high voltage device means that the voltage applied to the drain is higher than a specific voltage, for example, 5V, during normal operation, and the channel direction distance (the length of the drift region 222 a) between the body region 225 and the drain 229 is adjusted according to the operation voltage applied during normal operation, so that the high voltage device can operate at the higher specific voltage. This is well known to those skilled in the art and will not be described in detail herein.

As shown in fig. 2, the schottky barrier diode SD includes a schottky metal layer 231 and a schottky semiconductor layer 232, the schottky metal layer 231 is formed on the semiconductor layer 221 'and vertically, the schottky metal layer 231 is located on the upper surface 221a and connected to the upper surface 221a, the schottky metal layer 231 is electrically connected to the source 228 via a metal wire M L, the schottky semiconductor layer 232 is formed in the semiconductor layer 221', the schottky semiconductor layer 232 and the schottky metal layer 231 form a schottky contact, the schottky semiconductor layer 232 is adjacent to the well region 222, and vertically, the schottky semiconductor layer 232 is located under the upper surface 221a and connected to the upper surface 221 a.

The schottky barrier diode SD further comprises two insulation structures 233, which are respectively located outside two sides of the schottky metal layer 231, connected to the schottky semiconductor layer 232, and separated by a schottky channel 234, wherein the schottky channel 234 is a path for reverse current to flow through the schottky barrier diode SD when the schottky barrier diode SD is turned on, the insulation structures 233 are, for example, but not limited to, a Shallow Trench Isolation (STI) structure as shown in the figure, and also can be a local oxidation of silicon (L OCOS) structure, the insulation structures 233 can be formed by the same process steps as the drift oxide region 224.

With continued reference to fig. 2, the high voltage device 22 is formed by a basic cell M1 centered on the AA' axis through a mirror (layout) layout (layout), wherein the basic cell M1 includes at least a portion of a schottky barrier diode SD and at least a portion of a laterally diffused metal oxide semiconductor device L T, wherein in this embodiment, the schottky barrier diode SD is laterally divided into left and right halves as shown, and the right half of the schottky barrier diode SD is used as a portion of the basic cell M1, and the left half of the schottky barrier diode SD is formed through the mirror layout, in this embodiment, the basic cell M1 includes a complete drift oxide region 224, gate 227, source 228 and drain 229 as shown, as well as a portion 222, body region 225 and body electrode 226, wherein the left half of the body region 225 and the left half of the body electrode 226 are used as a portion of the basic cell M1, and the body region 225 and the right half of the body electrode 226 are formed after the mirror layout, the basic cell M1 is used to form a mirror layout, and the basic cell M L, and the basic DMOS layout may be formed according to the basic cell layout, and the basic cell layout may be described as a basic DMOS layout, wherein the basic cell M1, and the basic cell layout may include at least a basic cell layout 14, a basic cell layout, a basic DMOS 8521, and a basic cell layout 14, and a basic cell layout, and a basic DMOS 29, and a basic cell layout may be formed according to the invention.

It should be noted that in this embodiment, in all L DMOS devices, e.g., L DMOS devices L T and L T ', all well regions 222 are electrically connected to each other, all body regions 225 are electrically connected to each other, all body electrodes 226 are electrically connected to each other, all gates 227 are electrically connected to each other, all sources 228 are electrically connected to each other, and all drains 229 are electrically connected to each other in all schottky barrier diodes, e.g., schottky barrier diodes SD and SD', all schottky metal layers 231 are electrically connected to each other, and all schottky semiconductor layers 232 are electrically connected to each other, in a preferred embodiment, L DMOS L T, sources 228 and body electrodes 226 are electrically connected by silicide layers 223 as shown.

It is noted that one of the technical features of the present invention is superior to the prior art in that, according to the present invention, the high-voltage device 22 includes schottky barrier diodes SD and SD 'in addition to L DMOS devices L T and L T', since the reverse recovery time of the schottky barrier diodes SD and SD 'is shorter than that of the parasitic diode L D, the operation speed of the high-voltage device 22 according to the present invention can be significantly increased, and in addition, since the current can flow through the schottky barrier diodes SD and SD' during the idle period before the lower bridge switch is turned on, the current flowing through the parasitic diode L D can be greatly reduced, so that the high-voltage device 22 can be prevented from being damaged due to the reverse current mainly flowing through the parasitic diode L D, thereby increasing the safe operation area and further increasing the application range.

Referring to fig. 3, which shows a second embodiment of the present invention, fig. 3 is a schematic cross-sectional view of a high voltage device 32 used as a bottom bridge switch in a power stage of a switching power supply circuit, as shown in fig. 3, the high voltage device 32 is formed by a basic cell M2 centered on the BB' axis through a mirror (mirror) layout (layout), wherein the basic cell M2 includes at least a portion of a schottky barrier diode SD1, and L DMOS devices L T1 and L T2 and a portion of L DMOS L T3.

In the present embodiment, the DMOS device T includes a well region 322, a drift oxide region 324, a body region 325, a body electrode 326, a gate 327, a source 328, and a drain 329, wherein 0DMOS devices 1T and 2T are arranged in a mirror image with each other, and share the body region 325 and the body electrode 326, wherein 3DMOS devices 4T and 5T are arranged in a mirror image with each other, and share the drain 329, the basic cell M forms a basic cell M' after the mirror image layout, and can continue to repeat the mirror image layout to form the high voltage device 32.

The semiconductor layer 321 'is formed on the substrate 321, and the semiconductor layer 321' has an upper surface 321a and a lower surface 321b opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 3, the same applies below). The substrate 321 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 321 'is formed on the substrate 321, for example, by an epitaxial process, or a portion of the substrate 321 is used as the semiconductor layer 321'. The manner of forming the semiconductor layer 321' is well known to those skilled in the art and will not be described herein.

Continuing with fig. 3, a drift oxide region 324 is formed on the upper surface 321a and connected to the upper surface 321a, and is located right above a portion of the drift region 322a (as indicated by the dashed box in L DMOS L T1 in fig. 3) and connected to the drift region 322 a. the drift oxide region 324 is, for example, but not limited to, a local oxidation on silicon (L OCOS) structure as shown in the figure, and may also be a Shallow Trench Isolation (STI) structure.

The well 322 of the first conductivity type is formed in the semiconductor layer 321', and the well 322 is located under the upper surface 321a and connected to the upper surface 321a in the vertical direction. The well 322 is formed by at least one ion implantation process step, for example. The body region 325 of the second conductivity type is formed in the well region 322, and the body region 325 is located under the upper surface 321a and connected to the upper surface 321a in the vertical direction. The body electrode 326 has a second conductivity type for serving as an electrical contact for the body region 325. in the vertical direction, the body electrode 326 is formed under the upper surface 321a and connected to the body region 325 of the upper surface 321 a. The gate 327 is formed on the upper surface 321a of the semiconductor layer 321', and in the vertical direction, a portion of the body region 325 is located right under the gate 327 and connected to the gate 327 to provide an inversion region of the high voltage device 32 in the turn-on operation, and the inversion region is located right under a portion of the gate 327 and connected to the gate 327.

As shown in fig. 3, the source 328 and the drain 329 have the first conductivity type, and the source 328 and the drain 329 are formed below the upper surface 321a and connected to the upper surface 321a in the vertical direction, and the source 328 and the drain 329 are respectively located in the body region 325 below the gate 327 in the channel direction (as indicated by the dashed arrow in the figure, the bottom is the same) and in the well region 322 at the side far from the body region 325, and in the channel direction, the drift region 322a is located between the drain 329 and the body region 325 and in the well region 322 near the upper surface 321a, so as to serve as a drift current channel of the L DMOS L T1 in the turn-on operation.

In a preferred embodiment, the gate 327 includes a dielectric layer 3271 connected to the top surface, a conductive layer 3272 with conductivity, and a spacer layer 3273 with electrical insulation property. The dielectric layer 3271 is formed on the body region 325 and the well region 322, and is connected to the body region 325 and the well region 322. The conductive layer 3272 serves as an electrical contact for the gate 327, and is formed over all of the dielectric layer 3271 and connected to the dielectric layer 3271. Spacer layers 3273 are formed on both sides of conductive layer 3272 to serve as electrical insulation layers on both sides of gate 327.

As shown in fig. 3, the schottky barrier diode SD1 includes a schottky metal layer 331, a schottky semiconductor layer 332 and two insulating structures 333, the schottky metal layer 331 is formed on the semiconductor layer 321 'and vertically, the schottky metal layer 331 is on the upper surface 321a and connected to the upper surface 321a, the schottky metal layer 331 is electrically connected to the source 328 via a metal wire M L1, the schottky semiconductor layer 332 is formed in the semiconductor layer 321', the schottky semiconductor layer 332 is in schottky contact with the schottky metal layer 331, the schottky semiconductor layer 332 is adjacent to the well region 322, and vertically, the schottky semiconductor layer 332 is under the upper surface 321a and connected to the upper surface 321 a.

Two insulation structures 333, which are respectively located outside the two sides of the schottky metal layer 331, are connected to the schottky semiconductor layer 332, and are separated by a schottky channel 334, wherein the schottky channel 334 is a path for reverse current to flow through the schottky barrier diode SD1 when the schottky barrier diode SD1 is turned on, the insulation structures 333 are, for example, but not limited to, a local oxidation of silicon (L OCOS) structure as shown in the figure, and also can be a Shallow Trench Isolation (STI) structure, the insulation structures 333 can be formed by the same process steps as the drift oxide region 324 and completed simultaneously.

It should be noted that, in the present embodiment, in all L DMOS devices, such as L DMOS devices L T1, L T2 and L T3, all well regions 322 are electrically connected to each other, all body regions 325 are electrically connected to each other, all body poles 326 are electrically connected to each other, all gates 327 are electrically connected to each other, all sources 328 are electrically connected to each other, and all drains 329 are electrically connected to each other, in a preferred embodiment, L DMOS devices L T1, the sources 328 and the body poles 326 are electrically connected by a silicide layer 323 as shown.

Referring to fig. 4A-4C, which show a third embodiment of the present invention, fig. 4A shows a top view of a high voltage device 42 used as a bottom bridge switch in a power stage of a switching power supply circuit, fig. 4B and 4C show cross-sectional views of the high voltage device 42 of the DD ' tangent and the EE ' tangent of fig. 4A, respectively, as shown in fig. 4A-4C, the high voltage device 42 is formed by a basic cell M3 centered on the CC ' axis through a mirror (layout), wherein the basic cell M3 includes a schottky barrier diode SD2 and a portion L DMOS device L T4.

4A-4C, L DMOS element L T4 includes well region 422, drift oxide region 424, body region 425, body electrode 426, gate 427, source 428 and drain 429, wherein L DMOS elements L T4 and L T5 mirror each other and share body region 425 and body electrode 426. basic cell M3 forms basic cell M3' after mirror layout and can continue to repeat mirror layout to form high voltage element 42. in this embodiment, basic cell M3 includes part L DMOS element L T4 and Schottky barrier diode SD2, wherein Schottky barrier diode SD2 is located between body region 425 and drain 429 in corresponding L DMOS element L T4, and Schottky semiconductor layer 432 is connected to drift region 422 a.

The semiconductor layer 421 'is formed on the substrate 421, and the semiconductor layer 421' has an upper surface 421a and a lower surface 421B opposite to each other in a vertical direction (as indicated by solid arrows in fig. 4B and 4C, the same applies below). The substrate 421 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 421 'is formed on the substrate 421 by, for example, an epitaxial process, or a portion of the substrate 421 is used as the semiconductor layer 421'. The manner of forming the semiconductor layer 421' is well known to those skilled in the art and will not be described herein.

With continued reference to fig. 4A-4C, a drift oxide region 424 is formed on the top surface 421a, connected to the top surface 421a, and located directly above a portion of the drift region 422a (as indicated by the thick dashed line box in L DMOS L T4 in fig. 4B and 4C), and connected to the drift region 422a, the drift oxide region 424 is, for example, but not limited to, a local oxidation of silicon (L OCOS) structure as shown in the figures, and may also be a Shallow Trench Isolation (STI) structure.

The well 422 has the first conductivity type, is formed in the semiconductor layer 421', and in the vertical direction, the well 422 is located under the upper surface 421a and connected to the upper surface 421 a. The well region 422 is formed by at least one ion implantation process step, for example. The body region 425 of the second conductivity type is formed in the well region 422, and the body region 425 is located under the upper surface 421a and connected to the upper surface 421a in the vertical direction. The body electrode 426 has a second conductivity type for serving as an electrical contact to the body region 425. in the vertical direction, the body electrode 426 is formed below the top surface 421a and is connected to the body region 425 at the top surface 421 a. A gate electrode 427 is formed on the upper surface 421a of the semiconductor layer 421', and a portion of the body region 425 is located right below the gate electrode 427 and connected to the gate electrode 427 in the vertical direction to provide an inversion region of the high voltage device 42 in the turn-on operation, the inversion region being located right below a portion of the gate electrode 427 and connected to the gate electrode 427.

With continued reference to fig. 4A-4C, the source 428 and the drain 429 of the first conductivity type are vertically formed under the top surface 421a and connected to the top surface 421a, and the source 428 and the drain 429 are respectively located in the body region 425 and the well region 422 away from the body region 425 of the gate 427 outside the channel direction (as indicated by the dashed arrow in the figure, the same applies below), and the drift region 422a is located between the drain 429 and the body region 425 and in the well region 422 near the top surface 421a in the channel direction, so as to serve as a drift current channel of the L DMOS L T4 during the turn-on operation.

In a preferred embodiment, as shown in fig. 4B, the gate 427 includes a dielectric layer 4271 connected to the upper surface, a conductive layer 4272 having conductivity, and a spacer layer 4273 having electrical insulation property. Dielectric layer 4271 is formed on body region 425 and well region 422, and is connected to body region 425 and well region 422. The conductive layer 4272 serves as an electrical contact for the gate 427 and is formed on all of the dielectric layer 4271 and connected to the dielectric layer 4271. Spacer layers 4273 are formed on both sides of the conductive layer 4272 to serve as electrical insulation layers on both sides of the gate 427.

Referring to fig. 4A-4C, the schottky barrier diode SD2 includes a schottky metal layer 431 and a schottky semiconductor layer 432, the schottky metal layer 431 is formed on the semiconductor layer 421 ', and in the vertical direction, the schottky metal layer 431 is located on the upper surface 421a and connected to the upper surface 421a, the schottky metal layer 431 is electrically connected to the source 428 via a metal wire M L2, a schottky semiconductor layer 432 is formed in the semiconductor layer 421', as indicated by the thin frame line in fig. 4C, the schottky semiconductor layer 432 is in schottky contact with the schottky metal layer 431, and the schottky semiconductor layer 432 is connected to the drift region 422a in the well region 422, and in the vertical direction, the schottky semiconductor layer 432 is located under the upper surface 421a and connected to the upper surface 421 a.

This embodiment is different from the first embodiment in that, in this embodiment, as shown in fig. 4A and 4C, a schottky barrier diode SD2 is formed directly above the drift region 422a, a hole is formed downward from the gate 427 to pass through the drift region 422a, and a schottky barrier diode SD2 is arranged therein, so that L DMOS device L T4 corresponds to schottky barrier diode SD 2.

It should be noted that in the present embodiment, in all L DMOS devices, such as L DMOS devices L T4 and L T5, all well regions 422 are electrically connected to each other, all body regions 425 are electrically connected to each other, all body electrodes 426 are electrically connected to each other, all gates 427 are electrically connected to each other, all sources 428 are electrically connected to each other, and all drains 429 are electrically connected to each other, in a preferred embodiment, L DMOS devices L T4, sources 428 and body electrodes 426 are electrically connected by a silicide layer 423 as shown.

Referring to fig. 5A-5B, which show a fourth embodiment of the present invention, fig. 5A is a schematic top view of a high voltage device 52 used as a bottom bridge switch in a power stage of a switching power supply circuit, fig. 5B is a schematic cross-sectional view of the high voltage device 52 of fig. 5A, wherein the high voltage device 52 is formed by a basic cell M4 centered on FF' axis through a mirror (mirror) layout (layout), as shown in fig. 5A-5B, wherein the basic cell M4 includes a schottky barrier diode SD3, and a portion L DMOS L T6, a L DMOS L T7 and a portion L DMOS L T8.

In this embodiment, as shown in fig. 5A-5B, DMOS cells T include well regions 522, drift oxide regions 524, body regions 525, body electrodes 526, gates 527, sources 528, and drains 529, wherein 0DMOS cells 1T and 2T are mirror-image arranged with each other and share the body regions 525 and the body electrodes 526, and 3DMOS cells 4T and 5T are adjacent in the channel direction and share the drains 529, wherein schottky barrier diodes SD are located between the body regions 525 and the drains 529 of the corresponding 6DMOS cells 7T, in this embodiment, the basic cells M include 8DMOS 9T, partial DMOS cells T, and in addition to the schottky barrier diodes SD, they are mirror-image arranged with each other in the channel direction to form a power cell string, the schottky barrier diodes SD are located between the body regions 525 and the drains 529 of the corresponding 6DMOS cells T, that is located in the power cell string, the basic cells M form basic cells M' after the mirror-image layout, and the mirror-image layout can be repeated to form high voltage cells 52, in this embodiment, the schottky barrier diodes 522a are connected between the body regions 525 and the drains 532 a of the schottky barrier diodes.

The semiconductor layer 521 'is formed on the substrate 521, and the semiconductor layer 521' has an upper surface 521a and a lower surface 521B facing each other in a vertical direction (as indicated by solid arrows in fig. 4B and 4C, the same applies below). The substrate 521 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 521 'is formed on the substrate 521, for example, by an epitaxial process, or a portion of the substrate 521 is used as the semiconductor layer 521'. The manner of forming the semiconductor layer 521' is well known to those skilled in the art and will not be described herein.

With continued reference to fig. 5A-5B, a drift oxide region 524 is formed on the top surface 521a, connected to the top surface 521a, and located directly above a portion of the drift region 522a (as indicated by the thick dashed line box in L DMOS L T7 in fig. 5B), and connected to the drift region 522 a. the drift oxide region 524 is, for example, but not limited to, a local oxidation of silicon (L OCOS) structure as shown in the figure, and may also be a Shallow Trench Isolation (STI) structure.

The well region 522 of the first conductivity type is formed in the semiconductor layer 521', and the well region 522 is located under the upper surface 521a and connected to the upper surface 521a in the vertical direction. The well region 522 is formed, for example, by at least one ion implantation process step. The body region 525 of the second conductivity type is formed in the well 522, and the body region 525 is located under the upper surface 521a and connected to the upper surface 521a in the vertical direction. Body pole 526 of the second conductivity type is formed below top surface 521a and is electrically connected to body region 525 at top surface 521a in the vertical direction as an electrical contact to body region 525. The gate 527 is formed on the upper surface 521a of the semiconductor layer 521', and in the vertical direction, a portion of the body region 525 is located right below the gate 527 and connected to the gate 527 to provide an inversion region of the high voltage device 52 in the turn-on operation, and the inversion region is located right below a portion of the gate 527 and connected to the gate 527.

With reference to fig. 5A-5B, the source 528 and the drain 529 of the first conductivity type are vertically formed under the upper surface 521a and connected to the upper surface 521a, and the source 528 and the drain 529 are respectively located in the body region 525 outside the gate 527 in the channel direction (as indicated by the dashed arrow in the figure, the same applies below) and in the well region 522 away from the body region 525, and in the channel direction, the drift region 522a is located between the drain 529 and the body region 525 and in the well region 522 near the upper surface 521a, so as to serve as a drift current channel of the L DMOS L T7 during the turn-on operation.

In a preferred embodiment, as shown in fig. 5B, the gate 527 includes a dielectric layer 5271 connected to the upper surface, a conductive layer 5272 having conductivity, and a spacer layer 5273 having electrical insulation properties. The dielectric layer 5271 is formed on the body region 525 and the well region 522, and is connected to the body region 525 and the well region 522. The conductive layer 5272 is used as an electrical contact for the gate 527, and is formed on all of the dielectric layer 5271 and connected to the dielectric layer 5271. Spacer layers 5273 are formed on both sides of conductive layer 5272 to serve as electrical insulation layers on both sides of gate 527.

With continued reference to fig. 5A-5B, the schottky barrier diode SD3 includes a schottky metal layer 531 and a schottky semiconductor layer 532. The schottky metal layer 531 is formed on the semiconductor layer 521', and in the vertical direction, the schottky metal layer 531 is located on the upper surface 521a and connected to the upper surface 521 a; the schottky metal layer 531 and the source 528 are electrically connected via a metal wire. The schottky semiconductor layer 532 is formed in the semiconductor layer 521', as illustrated by the thin line in fig. 5B, the schottky semiconductor layer 532 forms a schottky contact with the schottky metal layer 531, and the schottky semiconductor layer 532 is connected to the drift region 522a in the well region 522, and in the vertical direction, the schottky semiconductor layer 532 is located under the upper surface 521a and connected to the upper surface 521 a. In the present embodiment, the schottky semiconductor layer 532 and the well 522 are formed in the same process step and are adjacent to each other in the channel direction and the vertical direction as shown in the figure.

The difference between this embodiment and the third embodiment is that, in this embodiment, as shown in fig. 5A and 5B, a schottky barrier diode SD3 is located in L DMOS elements L T6, and L DMOS elements L T6 are connected in series with a plurality of L DMOS elements to form a basic unit M4.

It should be noted that in the present embodiment, in all L DMOS devices, such as L DMOS devices L T6, L T7 and L T8, all well regions 522 are electrically connected to each other, all body regions 525 are electrically connected to each other, all body electrodes 526 are electrically connected to each other, all gates 527 are electrically connected to each other, all sources 528 are electrically connected to each other, and all drains 529 are electrically connected to each other, in a preferred embodiment, L DMOS devices L T7, the sources 528 and the body electrodes 526 are electrically connected by a silicide layer 523 as shown.

Fig. 6A is a schematic top view of a high voltage device 62 used as a bottom bridge switch in a power stage of a switching power supply circuit, and fig. 6B is a schematic cross-sectional view of a schottky barrier diode SD4 and its connected L DMOS L T9 in fig. 6A.

As shown in fig. 6A, the high voltage device 62 includes L DMOS device regions CE LL and an isolation region ISO, wherein L DMOS device regions CE LL include a plurality of power device strings PDS, each having a plurality of L DMOS devices L T9, which are connected in a staggered mirror arrangement to form the power device strings PDS, the isolation region ISO is located outside the L DMOS device regions CE LL and includes at least one schottky barrier diode SD4, wherein the schottky barrier diode SD4 is connected to the L DMOS devices L T9, wherein the isolation region ISO is used to isolate the high voltage device 62 from other devices on the same substrate.

As shown in fig. 6B, the high voltage device 62 includes lateral diffused metal Oxide Semiconductor (L lateral diffused metal Oxide Semiconductor, L DMOS) devices L T and L T 'and Schottky Barrier Diode (SBD) SD and SD'. L DMOS device L T9 including a well 622, a drift Oxide 624, a body 625, a body 626, a gate 627, a source 628 and a drain 629.

The semiconductor layer 621 'is formed on the substrate 621, and the semiconductor layer 621' has an upper surface 621a and a lower surface 621B opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 6B, the same applies below). The substrate 621 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 621 'is formed on the substrate 621, for example, by an epitaxial process, or a portion of the substrate 621 is used as the semiconductor layer 621'. The manner of forming the semiconductor layer 621' is well known to those skilled in the art and will not be described herein.

Continuing with fig. 6B, a drift oxide region 624 is formed on the top surface 621a and connected to the top surface 621a, and is located right above a portion of the drift region 622a (as indicated by the dashed box in L DMOS L T9 in fig. 6B) and connected to the drift region 622 a. the drift oxide region 624 may be, for example, but not limited to, a local oxidation on silicon (L OCOS) structure as shown in the figure, or may be a Shallow Trench Isolation (STI) structure.

The well 622 of the first conductivity type is formed in the semiconductor layer 621', and the well 622 is located under the upper surface 621a and connected to the upper surface 621a in the vertical direction. The well 622 is formed by at least one ion implantation process step, for example. The body region 625 of the second conductivity type is formed in the well 622, and the body region 625 is located under the upper surface 621a and connected to the upper surface 621a in the vertical direction. Body electrode 626 is of a second conductivity type for making electrical contact to body region 625. in the vertical direction, body electrode 626 is formed below top surface 621a and is connected to body region 625 on top surface 621 a. A gate electrode 627 is formed on the upper surface 621a of the semiconductor layer 621', and a portion of the body region 625 is located directly below the gate electrode 627 and connected to the gate electrode 627 in a vertical direction, so as to provide an inversion region 623a of the high voltage device 62 in a turn-on operation, the inversion region 623a being located directly below the portion of the gate electrode 627 and connected to the gate electrode 627.

With reference to fig. 6B, the source 628 and the drain 629 have the first conductivity type, in the vertical direction, the source 628 and the drain 629 are formed below the upper surface 621a and connected to the upper surface 621a, and the source 628 and the drain 629 are respectively located in the body region 625 below the gate 627 in the channel direction (as indicated by the dashed arrow, the same below), and in the well 622 away from the body region 625, and in the channel direction, the drift region 622a is located between the drain 629 and the body region 625 and in the well 622 near the upper surface 621a, so as to serve as a drift current channel of the L DMOS L T in the on operation.

In a preferred embodiment, the gate 627 comprises a dielectric layer 6271 connected to the upper surface, a conductive layer 6272 having conductivity, and a spacer layer 6273 having electrical insulating properties. The dielectric layer 6271 is formed on the body region 625 and the well 622, and is connected to the body region 625 and the well 622. The conductive layer 6272 serves as an electrical contact for the gate 627, formed over all of the dielectric layer 6271 and connected to the dielectric layer 6271. Spacer layers 6273 are formed on either side of conductive layer 6272 to act as electrical insulation layers on either side of gate 627.

Still referring to fig. 6B, the schottky barrier diode SD4 includes a schottky metal layer 631 and a schottky semiconductor layer 632, the schottky metal layer 631 is formed on the semiconductor layer 621 'and vertically, the schottky metal layer 631 is located on the upper surface 621a and connected to the upper surface 621a, the schottky metal layer 631 is electrically connected to the source 628 via a metal wire M L3, the schottky semiconductor layer 632 is formed in the semiconductor layer 621', the schottky semiconductor layer 632 is in schottky contact with the schottky metal layer 631, the schottky semiconductor layer 632 is adjacent to the well region 622, and vertically, the schottky semiconductor layer 632 is located below the upper surface 621a and connected to the upper surface 621 a.

The schottky barrier diode SD further comprises two insulating structures 633 respectively located outside of the schottky metal layer 631 on both sides thereof, connected to the schottky semiconductor layer 632, and separated by a schottky via 634, wherein the schottky via 634 is a path for a reverse current to flow through the schottky barrier diode SD4 when the schottky barrier diode SD is turned on, the insulating structures 633 are not limited to a local oxidation of silicon (L OCOS) structure as shown in the figure, and may also be a Shallow Trench Isolation (STI) structure, and the insulating structures 633 may be formed by the same process steps as the drift oxide region 624.

It should be noted that in the present embodiment, in all L DMOS L T9, all the wells 622 are electrically connected to each other, all the body regions 625 are electrically connected to each other, all the body poles 626 are electrically connected to each other, all the gates 627 are electrically connected to each other, all the sources 628 are electrically connected to each other, and all the drains 629 are electrically connected to each other, in a preferred embodiment, in L DMOS L T9, the sources 628 and the body poles 626 are electrically connected by the silicide layer 623 as shown.

Referring to fig. 7, a sixth embodiment of the invention is shown, fig. 7 shows a schematic cross-sectional view of a schottky barrier diode SD5, as shown in fig. 7, a schottky barrier diode SD5 includes a schottky metal layer 731, a schottky semiconductor layer 732, two insulating structures 733 and two channel-side well regions 734, wherein the schottky metal layer 731 is formed on the semiconductor layer 721 ', the schottky semiconductor layer 732 is formed in the semiconductor layer 721', the schottky semiconductor layer 732 is in schottky contact with the schottky metal layer 731, and the schottky semiconductor layer 732 is adjacent to the first conductive well region 722 of the L DMOS, in this embodiment, the schottky semiconductor layer 732 and the first conductive well region 722 of the schottky barrier diode SD L are formed by the same process step and are adjacent to each other in the channel direction.

Two insulation structures 733 are located outside of the schottky metal layer 731 and connected to the schottky semiconductor layer 732 and separated by a schottky via 735, wherein the schottky via 735 is a path for reverse current to flow through the schottky barrier diode SD5 when the schottky barrier diode SD5 is turned on, the insulation structures 733 are formed simultaneously by, but not limited to, a local oxidation of silicon (L OCOS) structure as shown in the figure, and also a Shallow Trench Isolation (STI) structure, the insulation structures 733 can be formed by the same process steps as the drift oxide region of the L DMOS elements, the two channel side 734 well regions have the second conductivity type, are located in the semiconductor layer 721' below the schottky metal layer 731 on both sides, and are separated by the schottky via 735, and the channel side well regions 734 are formed by the same process steps as the second conductivity type well regions of other elements on the substrate 721, for example.

Referring to fig. 8, which shows a seventh embodiment of the present invention, fig. 8 shows a schematic cross-sectional view of a schottky barrier diode SD6, as shown in fig. 8, a schottky barrier diode SD6 includes a schottky metal layer 831, a schottky semiconductor layer 832, two insulating structures 833, two polysilicon layers 835 and two channel-side body regions 834, wherein the schottky metal layer 831 is formed on the semiconductor layer 821 ', the schottky semiconductor layer 832 is formed in the semiconductor layer 821', the schottky semiconductor layer 832 forms a schottky contact with the schottky metal layer 831, and the schottky semiconductor layer 832 is adjacent to the first conductive well region 822 of the DMOS L, in this embodiment, the schottky semiconductor layer 832 and the first conductive well region 822 of the DMOS L are formed by the same process step and are adjacent to each other in the channel direction.

Two insulation structures 833 are located under the outside of the schottky metal layer 831 and connected to the schottky semiconductor layer 832, and are separated by a schottky channel 836, wherein the schottky channel 836 is a path for reverse current to flow through the schottky barrier diode SD6 when the schottky barrier diode SD6 is turned on, the insulation structures 833 are, for example, but not limited to, a Shallow Trench Isolation (STI) structure as shown in the figure, and may also be a local oxidation of silicon (L OCOS) structure, and the insulation structures 833 can be formed by the same process steps as the drift oxide region of the L DMOS device.

The two channel-side body regions 834 of the second conductivity type are formed in the semiconductor layer 821' under both sides of the schottky metal layer and separated by the schottky channel 836, and the two channel-side body regions 834 are formed by the same process steps as the second conductivity type body regions of other devices on the substrate 821, for example. The two polysilicon layers 835 are respectively located on the two channel-side body regions 834, and the polysilicon layers 835 are separated from the corresponding channel-side body regions 834 by corresponding insulating structures 833. The two polysilicon layers 835 are formed, for example, by the same process steps as the conductive layers of the gates of the other elements on the substrate 821.

Referring to fig. 9, an eighth embodiment of the invention is shown, fig. 9 shows a schematic cross-sectional view of a schottky barrier diode SD7, as shown in fig. 9, a schottky barrier diode SD7 includes a schottky metal layer 931, a schottky semiconductor layer 932, a two-channel side body region 934, two gates 935, and two-channel side body poles 936, wherein the schottky metal layer 931 is formed on a semiconductor layer 921 ', the schottky semiconductor layer 932 is formed in the semiconductor layer 921', the schottky semiconductor layer 932 forms a schottky contact with the schottky metal layer 931, and the schottky semiconductor layer 932 is adjacent to the first conductive well region 922 of the L DMOS, in this embodiment, the schottky semiconductor layer 932 and the first conductive well region 922 of the L DMOS are formed by the same process step and are adjacent to each other in the channel direction.

Two channel-side body regions 934 of the second conductivity type are formed in the semiconductor layer 921' below the schottky metal layer 931 on both sides, separated by schottky channels 937. The schottky channel 937 is a path for reverse current to flow through the schottky barrier diode SD6 when the schottky barrier diode SD6 is turned on. The channel-side body region 934 is formed, for example, by the same process step of the second conductivity-type body region of the other elements on the substrate 921. Two channel-side body poles 936 of the second conductivity type are in the two channel-side body regions 934, respectively, separated by the schottky channel 937. The channel side body pole 936 is formed by, for example, the same process steps as the second conductivity type body poles of the other elements on the substrate 921.

Two gate electrodes 935 are respectively disposed on the channel side body regions 934, and the gate electrodes 935 include a dielectric layer 9351 connected to the upper surface, a conductive layer 9352 having conductivity, and a spacer layer 9353 having electrical insulating properties. The conductive layers 9352 are separated from the corresponding channel-side body regions 934 by the corresponding dielectric layers 9351 or spacer layers 9353. The two gates 935 are formed, for example, by the same process steps as the gates of other elements on the substrate 921.

Referring to fig. 10A-10G in conjunction with fig. 2, fig. 10A-10G illustrate a ninth embodiment of the present invention. Fig. 10A-10G show schematic cross-sectional views of a method of manufacturing the high voltage component 22. As shown in fig. 10A, a semiconductor layer 221 'is first formed on a substrate 221, and the semiconductor layer 221' has an upper surface 221a and a lower surface 221b opposite to each other in a vertical direction (as indicated by the solid arrow in fig. 10A, the same applies below). At this time, the drift oxide region 224 and the insulating structure 233 are not yet formed, and the upper surface 221a is not yet completely defined. After the high voltage element 22 is formed, the upper surface 221a is shown by a thick broken line in the figure. The substrate 221 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 221 'is formed on the substrate 221, for example, by an epitaxial process, or a portion of the substrate 221 is used as the semiconductor layer 221'. The manner of forming the semiconductor layer 221' is well known to those skilled in the art and will not be described herein.

Continuing with fig. 10A, a first impurity is then doped into the semiconductor layer 221' to form the well region 222, for example, but not limited to, by a plurality of ion implantation process steps. The well region 222 is formed in the semiconductor layer 221', and the well region 222 is located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. The well region 222 is formed by a plurality of ion implantation process steps, for example.

Next, referring to fig. 10B, a drift oxide region 224 and two insulating structures 233 are formed on the top surface 221a and connected to the top surface 221 a. the drift oxide region 224 is not limited to a local oxidation of silicon (L OCOS) structure as shown in the figure, and may be a Shallow Trench Isolation (STI) structure, the insulating structures 233 are not limited to a Shallow Trench Isolation (STI) structure as shown in the figure, and may be a local oxidation of silicon (L OCOS) structure, the drift oxide region 224 is formed on the top surface 221a and connected to the top surface 221a, and is located directly above a portion of the drift region 222a (as indicated by the dashed line box in L DMOS L T in fig. 2), and is connected to the drift region 222a, the two insulating structures 233 are located outside the schottky metal layer 231 on both sides, are connected to the schottky semiconductor layer 232, and are separated by schottky channel 234, wherein the schottky channel 234 indicates that the reverse barrier current flows through the schottky diode when the SD is turned on.

Next, referring to fig. 10C, a dielectric layer 2271 and a conductive layer 2272 of the gate 227 are formed on the upper surface 221a of the semiconductor layer 221', and in a vertical direction (as indicated by the solid arrow in fig. 10C, the same applies below), a portion of the body region 226 is located right below the dielectric layer 2271 and the conductive layer 2272 of the gate 227 and connected to the dielectric layer 2271 of the gate 227, so as to provide L an inversion region 223a of the DMOS device L T during a turn-on operation.

Next, referring to fig. 10D, a body region 225 is formed in the well region 222, and the body region 225 is located under the upper surface 221a and connected to the upper surface 221a in the vertical direction. Body region 225 of the second conductivity type is formed by forming body region 225, for example, but not limited to, by using a photolithography process to form photoresist layer 2251 as a mask, and doping impurities of the second conductivity type into well region 222 to form body region 225. For example, but not limited to, the body region 225 may be formed by implanting impurities of the second conductivity type into the well region 222 in the form of accelerated ions by performing ion implantation processes including, but not limited to, IMP11 and IMP12 with tilted angles.

Continuing with fig. 10D, after forming the dielectric layer 2271 and the conductive layer 2272 of the gate 227, for example, a lightly doped region 2281 is formed to prevent the body region 225 under the spacer 2273 from forming an inversion current channel when the L DMOS device L T is turned on, a method of forming the lightly doped region 2281, for example, doping a first conductive type impurity into the body region 225 to form the lightly doped region 2281, wherein, for example, but not limited to, the ion implantation process step IMP2 may be used to implant the first conductive type impurity into the body region 225 in the form of accelerated ions to form the lightly doped region 2281. it should be noted that the first conductive type impurity concentration of the lightly doped region 2281 is lower than the first conductive type impurity concentration of the source 228 and the drain 229, and therefore, the overlapping portion of the lightly doped region 2281 and the source 228 and the drain 229 is relatively negligible.

Next, referring to fig. 10E, a spacer 2273 is formed outside the side of the conductive layer 2272 to form a gate 227, then, a source 28 and a drain 229 are formed under the upper surface 221a and connected to the upper surface 221a, and the source 228 and the drain 229 are respectively located in the body region 226 below the gate 227 outside the channel direction and in the well region 222 away from the body region 226, and in the channel direction, the drift region 222a is located between the drain 229 and the body region 225 and in the well region 222 near the upper surface 221a for serving as a drift current channel of the L DMOS device L T in the turn-on operation, and in the vertical direction, the source 228 and the drain 229 are located under the upper surface 221a and connected to the upper surface 221a, the source 228 and the drain 229 have the first conductivity type, and the steps of forming the source 228 and the drain 229, such as, but not limited to, using the photoresist layer 2281 formed by the photolithography process step as a mask, such as, but not limited to the ion implantation process step IMP3, the first conductivity type impurity is implanted into the drain region 225 and the well region 222, respectively, so as to form the source.

Next, referring to fig. 10F, as shown in fig. 10F, a body pole 226 is formed in the body region 225. The body electrode 226 has a second conductivity type for serving as an electrical contact for the body region 226. in the vertical direction, the body electrode 226 is formed under the upper surface 221a and is connected to the body region 225 of the upper surface 221 a. The body electrode 226 is formed by doping impurities of the second conductivity type into the body region 225 using, for example, but not limited to, a photoresist layer 2261 formed by a photolithography process as a mask to form the body electrode 226. In this embodiment, second conductive type impurities may be implanted into body region 225 in the form of accelerated ions to form body pole 226, for example, but not limited to, ion implantation process step IMP 4.

Next, referring to fig. 10G, as shown in fig. 10G, a schottky barrier diode SD is formed, which includes a schottky metal layer 231 and a schottky semiconductor layer 232, the schottky metal layer 231 is formed on the semiconductor layer 221 'and is in a vertical direction, the schottky metal layer 231 is located on the upper surface 221a and is connected to the upper surface 221a, the schottky metal layer 231 is electrically connected to the source 228 via a metal wire M L, the schottky semiconductor layer 232 is formed in the semiconductor layer 221', the schottky semiconductor layer 232 and the schottky metal layer 231 form a schottky contact, the schottky semiconductor layer 232 is adjacent to the well region 222, and in the vertical direction, the schottky semiconductor layer 232 is located under the upper surface 221a and is connected to the upper surface 221 a.

The two insulation structures 233 of the schottky barrier diode SD are respectively located outside the schottky metal layer 231 on both sides, connected to the schottky semiconductor layer 232, and separated by the schottky channel 234, wherein the schottky channel 234 is a path for a reverse current to flow through the schottky barrier diode SD when the schottky barrier diode SD is turned on, the insulation structures 233 are, for example, but not limited to, a Shallow Trench Isolation (STI) structure as shown in the figure, and also a local oxidation of silicon (L OCOS) structure, and the insulation structures 233 can be formed by the same process steps as the drift oxide region 224.

The high voltage device 22 is formed by a basic cell M1 centered on the AA ' axis through a mirror (mirror) layout (layout), wherein the basic cell M1 includes at least a part of a schottky barrier diode SD, and at least a part of a laterally diffused metal oxide semiconductor device L T, wherein in the present embodiment, the basic cell M1 is formed by a mirror layout in each step in comparison with the basic cell M1 ', further, as shown, the schottky barrier diode SD is laterally divided into a left half and a right half, the right half of the schottky barrier diode SD is used as a part of the basic cell M1, and the left half of the schottky barrier diode SD is formed through a mirror layout, and in the present embodiment, the basic cell M1 includes a complete drift oxide region 224, a gate 227, a source 228, and a drain 229, and a part of the drift oxide region 224, the body region 225, and the body region 226, and the body region 225 is used as a part of the drift oxide region 224, the gate 227, the source 228, and the drain region 222, the body region 225 and the body region 226, and the body region 225 and the body region may be formed through a mirror layout after the basic cell M6328 ' layout, the basic cell M6328, the basic cell layout is repeated, the basic cell layout, the basic cell M layout may be formed through a basic cell layout, a lateral layout, a basic cell M layout, a basic cell M8526, a basic cell layout, a basic.

It should be noted that in this embodiment, in all L DMOS devices, e.g., L DMOS devices L T and L T ', all well regions 222 are electrically connected to each other, all body regions 225 are electrically connected to each other, all body electrodes 226 are electrically connected to each other, all gates 227 are electrically connected to each other, all sources 228 are electrically connected to each other, and all drains 229 are electrically connected to each other in all schottky barrier diodes, e.g., schottky barrier diodes SD and SD', all schottky metal layers 231 are electrically connected to each other, and all schottky semiconductor layers 232 are electrically connected to each other, in a preferred embodiment, L DMOS L T, sources 228 and body electrodes 226 are electrically connected by silicide layers 223 as shown.

The present invention has been described with respect to the preferred embodiments, but the above description is only for the purpose of making the content of the present invention easy to understand for those skilled in the art, and is not intended to limit the scope of the present invention. Equivalent variations will occur to those skilled in the art, within the same spirit of the invention. For example, other process steps or structures, such as deep well regions, may be added without affecting the primary characteristics of the device; for example, the lithography technique is not limited to the mask technique, but may include electron beam lithography. All of which can be analogized to the teachings of the present invention. In addition, the embodiments described are not limited to a single application, and may be combined, for example, but not limited to, a combination of both embodiments. For example, the schottky barrier diodes SD5, SD6 and SD7 shown in fig. 7, 8 and 9 can be applied to the first to fifth and ninth embodiments. Accordingly, the scope of the present invention should be determined to encompass all such equivalent variations as described above. Furthermore, it is not necessary for any embodiment of the invention to achieve all of the objects or advantages, and thus, any one of the claims should not be limited thereby.