阅读说明：本技术 具有应变通道的晶体管及其制作方法 (Transistor with strained channel and method of making the same ) 是由 杨柏宇 于 2019-01-14 设计创作，主要内容包括：本发明公开一种具有应变通道的晶体管及其制作方法,该半导体元件包含：一基底,具有一上表面；一源极区域,设于该基底中；一漏极区域,设于该基底中；一凹槽,介于该源极区域与该漏极区域之间,从该基底的该上表面延伸进入该基底中,其中该凹槽具有一六角形剖面轮廓；一应力诱发材料层,设于该凹槽内；一通道层,设于该应力诱发材料层上；以及一栅极结构,设于该通道层上。(The invention discloses a transistor with a strain channel and a manufacturing method thereof, wherein a semiconductor element comprises: a substrate having an upper surface; a source region disposed in the substrate; a drain region disposed in the substrate; a recess between the source region and the drain region extending into the substrate from the upper surface of the substrate, wherein the recess has a hexagonal cross-sectional profile; a stress inducing material layer disposed in the recess; a channel layer disposed on the stress-inducing material layer; and a gate structure disposed on the channel layer.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate having an upper surface;

forming a first sacrificial gate on the substrate;

forming a spacer on a sidewall of the first sacrificial gate;

forming a source region and a drain region in the substrate adjacent to the first sacrificial gate;

forming a channel region between the source region and the drain region;

forming a stop layer on the substrate, wherein the stop layer conformally covers the spacer, the first sacrificial gate, the source region and the drain region;

removing the first sacrificial gate, and forming a gate trench on the channel region between the spacers;

etching the substrate through the gate trench to form a recess between the source region and the drain region and extending into the substrate from the upper surface of the substrate, wherein the recess has a hexagonal cross-sectional profile;

forming a stress inducing material layer in the recess;

epitaxially growing a channel layer on the stress-inducing material layer; and

a gate structure is formed over the channel layer.

2. The method of claim 1, further comprising:

forming a second sacrificial gate on the substrate; and

forming a recess structure in the substrate adjacent to the second sacrificial gate, wherein the gate trench and the recess structure are formed simultaneously.

3. The method of claim 1, further comprising:

epitaxially growing the channel layer on the stress-inducing material layer, and then depositing an interlayer dielectric layer on the channel layer, wherein the interlayer dielectric layer covers the stop layer and fills the gate trench; and

the interlayer dielectric layer is removed from the gate trench to expose the channel layer.

4. The method of claim 1, wherein the substrate is a P-type substrate, and wherein the source region and the drain region are both N-type doped regions.

5. The method of claim 1, wherein the sacrificial gate comprises a polysilicon gate.

6. The method of claim 1, wherein the stop layer comprises a silicon nitride layer.

7. The method of claim 1, wherein the stress inducing material layer comprises a silicon germanium layer.

8. The method of claim 1, wherein the channel layer comprises a crystalline silicon layer.

9. A semiconductor device, comprising:

a substrate having an upper surface;

a source region disposed in the substrate;

a drain region disposed in the substrate;

a recess between the source region and the drain region extending into the substrate from the upper surface of the substrate, wherein the recess has a hexagonal cross-sectional profile;

a stress inducing material layer disposed in the recess;

a channel layer disposed on the stress-inducing material layer; and

and the grid structure is arranged on the channel layer.

10. The semiconductor device of claim 9, wherein the substrate is a P-type substrate, and wherein the source region and the drain region are both N-type doped regions.

11. The semiconductor device as defined in claim 9, further comprising spacers disposed on sidewalls of the gate structure.

12. The semiconductor device of claim 11, further comprising a stop layer on said substrate, wherein said stop layer conformally covers said spacer, said source region and said drain region.

13. The semiconductor device of claim 12, wherein said stop layer comprises a silicon nitride layer.

14. The semiconductor device of claim 9, wherein the stress inducing material layer comprises a silicon germanium layer.

15. The semiconductor device of claim 9, wherein said channel layer comprises a crystalline silicon layer.

16. The semiconductor device of claim 9, wherein said gate structure comprises a metal gate.

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and more particularly, to a transistor having a strained channel (strained channel) and a method for manufacturing the same.

Background

It is known that providing different types of stress (stress) in the structure of a transistor can increase the mobility of charge carriers in the channel region. For example, providing tensile stress to the channel region can increase electron mobility, thereby increasing conductivity and increasing operating speed. Providing compressive stress to the channel region may increase the mobility of the voids, thereby enhancing the performance of the transistor.

Typically, compressive stress is introduced into the channel region for N-type transistors and tensile stress is introduced into the channel region for P-type transistors. Various structures have been proposed in the prior art to introduce stress in their respective channel regions, however the prior art may suffer from misalignment issues.

Disclosure of Invention

The present invention provides an improved semiconductor structure and method for fabricating the same, which can effectively introduce compressive stress into the channel region of an N-type transistor and tensile stress into the channel region of a P-type transistor without misalignment.

One aspect of the present invention provides a method of forming a semiconductor structure. First, a substrate having an upper surface is provided. A first sacrificial gate is formed on the substrate. Spacers are formed on sidewalls of the first sacrificial gate. A source region and a drain region are formed in the substrate adjacent to the first sacrificial gate. A channel region is formed between the source region and the drain region. A stop layer is formed on the substrate, wherein the stop layer conformally covers the spacer, the first sacrificial gate, the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed in the channel region between the spacers. Etching the substrate through the gate trench to form a recess between the source region and the drain region and extending into the substrate from the upper surface of the substrate, wherein the recess has a hexagonal cross-sectional profile. A stress-inducing material layer is formed in the recess. A channel layer is epitaxially grown on the stress-inducing material layer. A gate structure is formed over the channel layer.

In one aspect, the present invention provides a semiconductor device, comprising: a substrate having an upper surface; a source region disposed in the substrate; a drain region disposed in the substrate; a recess between the source region and the drain region extending into the substrate from the upper surface of the substrate, wherein the recess has a hexagonal cross-sectional profile; a stress inducing material layer disposed in the recess; a channel layer disposed on the stress-inducing material layer; and a gate structure disposed on the channel layer.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below. However, the following preferred embodiments and the accompanying drawings are only for reference and illustration purposes and are not intended to limit the present invention.

Drawings

Fig. 1 to 7 are schematic cross-sectional views illustrating a method of forming a semiconductor structure according to an embodiment of the invention.

Description of the main elements

100 substrate

100a upper surface

101 NMOS region

102 PMOS region

103 isolation region

110N type well

130 trench isolation structure

2 NMOS transistor

21 sacrificial gate

21' metal gate structure

200 channel region

201N type lightly doped drain (N L DD) region

210 polysilicon layer

210' metal layer

212 gate dielectric layer

212' Gate dielectric layer

214 silicon nitride cap layer

216 spacer

220 gate trench

221. 221a groove

3 PMOS transistor

31 sacrificial gate

31' metal gate structure

300 channel region

301P type lightly doped drain (P L DD) region

310 polysilicon layer

310' metal layer

312 Gate dielectric layer

312' gate dielectric layer

314 silicon nitride cap layer

316 spacer

321. 321a concave structure

40 stop layer

416 space wall

50 photoresist pattern

501. 502 opening (not shown)

601. 602 stress inducing material layer

701 epitaxial silicon layer (channel layer)

702 epitaxial silicon layer

NS source region

ND Drain region

PS source region

PD drain region

Detailed Description

In the following, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the embodiments may be practiced. The following examples are described in sufficient detail to enable those skilled in the art to practice them.

Of course, other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments described herein. The following detailed description is, therefore, not to be taken in a limiting sense, and the embodiments included therein are defined by the appended claims.

Fig. 1 to 7 are cross-sectional views illustrating a method for forming a semiconductor structure according to an embodiment of the invention. As shown in fig. 1, first, a substrate 100, such as, but not limited to, a P-type silicon substrate, is provided. The substrate 100 may include an NMOS region 101, a PMOS region 102, and an isolation region 103. A trench isolation structure 130 is formed in the isolation region 103 to isolate the NMOS region 101 and the PMOS region 102 from each other. The substrate 100 includes an upper surface 100 a. An N-well 110 may be formed in the PMOS region 102.

According to the present embodiment, an NMOS transistor 2 is formed in the NMOS region 101, including a sacrificial gate 21, such as a polysilicon gate. For example, the sacrificial gate 21 may include, but is not limited to, a polysilicon layer 210, a gate dielectric layer 212, and a silicon nitride cap layer 214. A spacer 216, such as, but not limited to, a silicon nitride spacer, may be disposed on each sidewall of the sacrificial gate 21. In the substrate 100, a source region NS and a drain region ND are further formed adjacent to the sacrificial gate 21.

In addition, the source region NS and the drain region ND may further include an N-type lightly doped drain (N L DD) region 201 directly under the spacer 216. according to the embodiment of the invention, a channel region 200 is formed between the source region NS and the drain region ND.

In accordance with an embodiment of the present invention, a PMOS transistor 3 is formed in the PMOS region 102, including a sacrificial gate 31, such as a polysilicon gate, for example, the sacrificial gate 31 may include a polysilicon layer 310, a gate dielectric layer 312, and a silicon nitride cap layer 314. a spacer 316, such as, but not limited to, a silicon nitride spacer, may be disposed on each sidewall of the sacrificial gate 31. in the substrate 100, adjacent to the sacrificial gate 31, a P-type lightly doped drain (P L DD) region 301 is formed.A channel region 300 is disposed directly under the sacrificial gate 31 between the P-type lightly doped drain (P L DD) regions 301.

A stop layer 40, such as a silicon nitride layer, is formed on the substrate 100 to serve as an etch stop layer, the stop layer 40 conformally covers the NMOS region 101, the PMOS region 102, and the isolation region 103. for example, in the NMOS region 101, the stop layer 40 conformally covers the spacers 216, the sacrificial gate 21, the source region NS, and the drain region ND. in the PMOS region 102, and the stop layer 40 conformally covers the spacers 316, the sacrificial gate 31, and the P L DD region 301.

As shown in fig. 2, a photolithography process and an etching process may be performed to remove the sacrificial gate 21 and form a gate trench 220 in the channel region 200 between the spacers 216. For example, a photoresist pattern (not shown) is formed on the stop layer 40 and has an opening over the sacrificial gate 21, and then the stop layer 40 and the sacrificial gate 21 are etched through the opening to remove the polysilicon layer 210, the gate dielectric layer 212 and the silicon nitride cap layer 214, thereby forming a gate trench 220 and exposing the channel region 200. Then, the photoresist pattern is removed.

As shown in fig. 3, a photoresist pattern 50 is formed on the substrate 10, covering the NMOS region 101, the PMOS region 102 and the isolation region 103, the photoresist pattern 50 includes an opening 501 in the NMOS region 101 aligned with the gate trench 220, and an opening 502 in the PMOS region 102, exposing the sacrificial gate 31 of the PMOS transistor 3 and at least a portion of the P L DD region 301 adjacent to the sacrificial gate 31.

Next, an anisotropic dry etching process is performed to etch the substrate 100 through the opening 501 and the gate trench 220 to form a recess 221 between the source region NS and the drain region ND, and at the same time, a recess 321 is formed in the substrate 100 adjacent to the sacrificial gate 31 through the opening 502. The recess 221 and the recess 321 extend from the upper surface 100a of the substrate 100 into the substrate 100 to a first predetermined depth. Next, the photoresist pattern 50 is removed. The anisotropic dry etch process etches the stop layer 40 through the opening 502 to form the spacers 416.

Then, as shown in fig. 4, a wet etching process is performed to continuously etch the groove 221 and the recess structure 321, so as to form a widened groove 221a and a widened recess structure 321 a. The wet etching process may include a substance containing a hydroxyl group (OH), including, but not limited to, potassium hydroxide, tetramethylammonium hydroxide (TMAH), or sodium hydroxide. The grooves 221a and the recessed structures 321a extend into the substrate 100 from the upper surface 100a of the substrate 100 to a second predetermined depth. According to an embodiment of the present invention, the second predetermined depth is not deeper than the lowest junction of the source region NS and the drain region ND. According to an embodiment of the present invention, the groove 221a and the recess structure 321a may have a hexagonal cross-sectional profile.

As shown in fig. 5, a stress-inducing material layer 601 is formed in the recess 221a, and a stress-inducing material layer 602 is formed in the recess 321 a. According to an embodiment of the present invention, the stress inducing material layers 601, 602 comprise silicon germanium (SiGe) layers. The stress-inducing material layers 601, 602 may be formed by selective epitaxy, but are not limited thereto.

Then, an epitaxial process is performed to epitaxially grow an epitaxial silicon layer 701 and an epitaxial silicon layer 702 on the stress-inducing material layer 601 and the stress-inducing material layer 602, respectively, wherein the epitaxial silicon layer 701 is a crystalline silicon layer and can be used as a channel layer of the NMOS transistor 2. The epitaxial silicon layer 702 serves as part of the source/drain structure of the PMOS transistor 3.

Subsequently, heavily doped ion implantation of the source and drain may be continued to form a source region PS and a drain region PD in the PMOS region 102. For example, the source region PS and the drain region PD may be P-type heavily doped regions.

As shown in fig. 6, a Chemical Vapor Deposition (CVD) process is then performed to globally deposit an interlayer dielectric layer 80, such as a silicon oxide layer or a low-k material layer. The interlayer dielectric layer 80 covers the stop layer 40 and the sacrificial gate 31 and the epitaxial silicon layer 702 in the PMOS region 102, and the interlayer dielectric layer 80 fills the gate trench 220. The interlayer dielectric layer 80 may be further subjected to a planarization process, such as a Chemical Mechanical Polishing (CMP) process.

Next, a photolithography process and an etching process may be performed to remove the interlayer dielectric layer 80 from the gate trench 220 to expose the epitaxial silicon layer 701 (channel layer), and at the same time, remove the sacrificial gate 31 to form the gate trench 320 to expose the channel region 300.

As shown in fig. 7, a metal gate structure 21 'is formed on the epitaxial silicon layer 701 (channel layer) in the gate trench 220, and a metal gate structure 31' is formed on the channel region 300 in the gate trench 320. According to an embodiment of the present invention, the metal gate structure 21 'may include a metal layer 210' and a gate dielectric layer 212 ', and the metal gate structure 31' may include a metal layer 310 'and a gate dielectric layer 312', but is not limited thereto. It should be understood that the metal gate structures 21 'and 31' in fig. 7 are only illustrative, and in other embodiments, the metal gate structures 21 'and 31' may have different structures.

Structurally, for example, as shown in fig. 7, the NMOS transistor 2 includes: a substrate 100 having an upper surface 100 a; a source region NS disposed in the substrate 100; a drain region ND disposed in the substrate 100; a recess 221a between the source region NS and the drain region ND extending from the upper surface 100a of the substrate 100 into the substrate 100 to a predetermined depth, wherein the recess 221a has a hexagonal cross-sectional profile; a stress-inducing material layer 601 disposed in the recess 221 a; a channel layer 701 disposed on the stress-inducing material layer 601; and a metal gate structure 21' disposed on the channel layer 701. The substrate 100 is a P-type substrate, and the source region NS and the drain region ND are both N-type doped regions.

The NMOS transistor 2 further includes a spacer 216 disposed on the sidewall of the metal gate structure 21'. The NMOS transistor 2 further includes a stop layer 40 disposed on the substrate 100, wherein the stop layer 40 conformally covers the spacer 216, the source region NS and the drain region ND. According to an embodiment of the present invention, the stop layer 40 comprises a silicon nitride layer, the stress inducing material layer 601 comprises a silicon germanium layer, and the channel layer 701 comprises a crystalline silicon layer.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.