阅读说明：本技术 数据传输系统、电路与方法 (Data transmission system, circuit and method ) 是由 韦伯霖 李必明 杨志强 于 2020-04-15 设计创作，主要内容包括：本发明揭露一种数据传输系统、电路与方法,数据传输系统能够加快两系统单芯片之间的数据传输。该数据传输系统包含：一主控系统单芯片,包含一主控传送环形缓冲器(circular buffer)与一主控接收环形缓冲器；以及一从属系统单芯片,包含一从属接收环形缓冲器与一从属传送环形缓冲器。该从属/主控接收环形缓冲器为该主控/从属传送环形缓冲器的复制,因此,该两缓冲器的写入指针实质同步,且该两缓冲器的读取指针实质同步。据上所述,该主控/从属传送环形缓冲器的读写操作可视为该从属/主控接收环形缓冲器的读写操作,从而该数据传输的部分的数据复制程序可被省略,以加快该数据传输。(The invention discloses a data transmission system, a circuit and a method, wherein the data transmission system can accelerate data transmission between two system single chips. The data transmission system includes: a single chip of master control system, which comprises a master transmit ring buffer (circular buffer) and a master receive ring buffer; and a slave system-on-chip including a slave receive ring buffer and a slave transmit ring buffer. The slave/master receive ring buffer is a replica of the master/slave transmit ring buffer, so the write pointers of the two buffers are substantially synchronized and the read pointers of the two buffers are substantially synchronized. As described above, the read/write operations of the master/slave transmit ring buffer can be regarded as the read/write operations of the slave/master receive ring buffer, so that the data copy procedure of the data transfer portion can be omitted to speed up the data transfer.)

1. A data transmission system capable of accelerating data transmission between two system-on-chip chips, the data transmission system comprising:

a single chip of a host system, comprising:

a master transport ring buffer for receiving master data from a master upper layer circuit of the master system single chip and updating a master transport buffer write pointer according to the master data and for updating a master transport buffer read pointer according to an update notification of a slave receive buffer read pointer; and

a master receiving ring buffer for receiving slave data from a slave system single chip and updating a master receiving buffer write pointer, and for updating a master receiving buffer read pointer after the master upper layer circuit reads the slave data; and

the slave system-on-a-chip comprises:

a slave receiving ring buffer for receiving the master data from the master system chip and updating a slave receiving buffer write pointer according to the master data, and for updating the slave receiving buffer read pointer after a slave upper layer circuit of the slave system chip reads the master data; and

a slave transmit ring buffer for receiving the slave data from the slave upper layer circuit and updating a slave transmit buffer write pointer, and updating a slave transmit buffer read pointer according to an update notification of the master receive buffer read pointer.

2. The data transmission system of claim 1, wherein the primary system-on-a-chip further comprises:

a master interface circuit for transmitting the master data to the slave system-on-chip, receiving the update notification of the slave receive buffer read pointer from the slave system-on-chip, receiving the slave data from the slave system-on-chip, and transmitting the update notification of the master receive buffer read pointer to the slave system-on-chip; and

the slave system-on-a-chip further comprises:

a slave interface circuit for receiving the master data from the master chip, transmitting the update notification of the slave receive buffer read pointer to the master chip, transmitting the slave data to the master chip, and receiving the update notification of the master receive buffer read pointer from the master chip.

3. The data transmission system of claim 2, wherein the master interface circuit and the slave interface circuit are both universal serial bus interface circuits or peripheral component interconnect express (PCI express) interface circuits.

4. The data transmission system of claim 2, wherein the slave interface circuit stores the master data in the slave receive ring buffer without using other buffers.

5. The data transmission system of claim 2, wherein the master interface circuit stores the slave data in the master receive ring buffer without using other buffers.

6. The data transmission system of claim 1, wherein the buffer size of the master transmit ring buffer is equal to the buffer size of the slave receive ring buffer; the master receive ring buffer has a buffer size equal to the buffer size of the slave transmit ring buffer.

7. The data transmission system of claim 6, wherein the buffer size of the master transmit ring buffer is larger than the buffer size of the master receive ring buffer; the buffer size of the slave receive ring buffer is larger than the buffer size of the slave transmit ring buffer.

8. The data transmission system of claim 1, wherein the buffer size of the master transmit ring buffer is larger than the buffer size of the master receive ring buffer; the buffer size of the slave receive ring buffer is larger than the buffer size of the slave transmit ring buffer.

9. The data transmission system of claim 1, wherein the master system-on-chip actively requests the slave system-on-chip to provide the update notification of the slave receive buffer read pointer after transmitting the master data to the slave system-on-chip, thereby updating the master transmit buffer read pointer; before receiving the slave data, the master chip actively queries the slave chip to know the existence of the slave data, thereby requesting the slave chip to transmit the slave data to the master chip.

10. The data transmission system of claim 1, wherein the master system chip is a video decoding chip, and the slave system chip is a video playing chip.

Technical Field

The present disclosure relates to data transmission systems, circuits and methods, and more particularly, to a data transmission system, circuit and method suitable for data transmission between two system-on-a-chip chips.

Background

A general USB transfer procedure includes: the transmit end (TX) procedure copies the data to the TX transport layer; the TX transmission layer wraps the data and then sends the data packet to a TX USB driver; the TX USB driver transmits the data packet to a receiving end (RX); after receiving the data packet, the RX USB driver sends the data packet to an RX transmission layer; the RX transport layer unpacks the data packet and routes the data to the target process. During the transmission, the data is copied many times. In some applications (e.g., multimedia playback), each data (e.g., 8K image frame data) must be distributed to the target program (e.g., multimedia playback program) within a certain period of time, or else there is a delay; if the data volume of each data is large, and the transmitting end and the receiving end do not belong to the same System on a Chip (SoC) and cannot share the same memory space, the hysteresis phenomenon is easy to occur. In view of the foregoing, there is a need in the art for an efficient way to implement data transmission between system-on-a-chip.

Disclosure of Invention

One objective of the present disclosure is to disclose a data transmission system, circuit and method for efficiently performing data transmission between system-on-a-chip.

An embodiment of the data transmission system of the present disclosure can accelerate data transmission between a master system single chip and a slave system single chip. In this embodiment, the single chip of the main control system includes: a Master transport ring buffer for receiving Master data from a Master upper layer circuit (e.g., video decoding circuit) of the Master System-on-a-chip and updating a Master transport buffer write pointer by the data, and for updating a Master transport buffer read pointer according to an update notification of a Slave receive buffer read pointer; and a master receive ring buffer for receiving the slave data from a slave system chip and updating a master receive buffer write pointer, and for updating a master receive buffer read pointer after the master upper layer circuit reads the slave data. In addition, in this embodiment, the slave system chip includes: a slave receiving ring buffer for receiving the master data from the master system chip and updating a slave receiving buffer write pointer according to the master data, and for updating the slave receiving buffer read pointer after a slave upper layer circuit (e.g. a video playback circuit) of the slave system chip reads the master data; and a slave transmit ring buffer for receiving the slave data from the slave upper layer circuit and updating a slave transmit buffer write pointer and a slave transmit buffer read pointer according to an update notification of the master receive buffer read pointer.

According to the data transmission circuit, data transmission between two system single chips can be accelerated. The embodiment comprises a first system-on-a-chip (e.g., a video decoding SoC or a video playing SoC) comprising: a first transmit ring buffer for receiving first side data from an upper layer circuit of the first SOC and updating a transmit buffer write pointer accordingly, and for updating a transmit buffer read pointer according to a read pointer update notification of a second SOC; and a first receiving ring buffer for receiving the second end data from the second system-on-chip and updating a receiving buffer write pointer accordingly, and for updating a receiving buffer read pointer after the upper layer circuit reads the second end data.

According to the data transmission method, data transmission between two system single chips can be accelerated. The embodiment is performed by a first system-on-a-chip (e.g., a video decoding SoC or a video playback SoC), comprising the steps of: receiving first end data from an upper layer circuit of the first system-on-chip by using a transmission ring buffer, and updating a transmission buffer write pointer according to the first end data; transmitting the first-side data of the transmit ring buffer to a second system-on-chip; updating a transmission buffer read pointer according to a read pointer update notification of the second system-on-chip; receiving the second end data of the second system-on-chip by using a receiving ring buffer, and updating a receiving buffer write pointer according to the second end data; after the upper layer circuit reads the second end data of the receiving ring buffer, updating a receiving buffer reading pointer; and sending an update notification of the read pointer of the receive buffer to the second SOC. .

The features, practical operation and effects of the present invention will be described in detail with reference to the drawings.

Drawings

Fig. 1 shows an embodiment of a data transmission system of the present disclosure; and

fig. 2 shows an embodiment of a data transmission method according to the present disclosure.

Detailed Description

Fig. 1 shows an embodiment of a data transmission system according to the present disclosure. The data transmission system 10 of fig. 1 can accelerate data transmission between two system-on-a-chip (SoCs), and includes a master system-on-a-chip (master SoC)100 and a slave system-on-a-chip (slave SoC) 200; in this specification, the terms "master" and "slave" are used for convenience of description, and do not mean that there is a required dependency relationship between the two soc 100, 200, which does not depend on the communication protocol between the two soc 100, 200. The master SoC 100 (e.g., video decoding SoC) includes a master transmit ring buffer (circular buffer)110 and a master receive ring buffer 120. The slave SoC200 (e.g., video playback SoC) includes a slave receive ring buffer 210 and a slave transmit ring buffer 220. The write pointers of the slave receive ring buffer 210 and the master transmit ring buffer 110 change substantially synchronously, and the read pointers of the two buffers change substantially synchronously; similarly, the write pointers of the master receive ring buffer 120 and the slave transmit ring buffer 220 change substantially synchronously, and the read pointers of the two buffers change substantially synchronously. As described above, the master/slave SoC 100/200 can consider the read/write operations of the slave/master receive ring buffer 210/120 as the read/write operations of the master/slave transmit ring buffer 110/220, so that a part of the data copy procedure for the data transfer between the master SoC 100 and the slave SoC200 can be omitted to speed up the data transfer. It should be noted that the above synchronous change means: after a first change of a first pointer and before a second change of the first pointer, the first change of a second pointer needs to be completed, and the first change of the second pointer needs to correspond to the first change of the first pointer.

Please refer to fig. 1. The master transport ring buffer 110 is used to receive master data (e.g., decoded image frame data) from a master upper layer circuit 102 (e.g., a conventional video decoding circuit used to generate the master data according to an input signal) of the master SoC 100, and to update a master transport buffer write pointer (M _ tx (wp)); after the host data is sent to the slave SoC200, the master transport ring buffer 110 is used to update a master transport buffer read pointer (M _ tx (rp)) according to an update notification of a slave receive buffer read pointer (S _ rx (rp)), wherein the master transport buffer write pointer and the master transport buffer read pointer are respectively used to indicate the write and read status of the master transport ring buffer 110. The master receive ring buffer 120 receives the slave data (e.g., video playback end notification, video parameter (e.g., brightness, contrast) adjustment notification, video synchronization correction signal, etc.) from the slave SoC200, and updates a master receive buffer write pointer (M _ rx (wp)) accordingly; the master receive ring buffer 120 is further configured to update a master receive buffer read pointer (M _ rx (rp)) after the master upper layer circuit 102 reads the slave data, wherein the master receive buffer write pointer and the master receive buffer read pointer are respectively used for indicating the write status and the read status of the master receive ring buffer 120.

Please refer to fig. 1. The slave receive ring buffer 210 is used to receive the master data from the master SoC 100 and update a slave receive buffer write pointer (S _ rx (wp)); the slave receive ring buffer 210 is further configured to update the slave receive buffer read pointer after a slave upper layer circuit 202 (e.g., a conventional video playback circuit configured to generate an output signal according to the master data) of the slave SoC200 reads the master data, wherein the slave receive buffer write pointer and the slave receive buffer read pointer are respectively configured to indicate a write status and a read status of the slave receive ring buffer 210. Slave transfer ring buffer 220 is used to receive the slave data from slave upper layer circuit 202 and update a slave transfer buffer write pointer (S _ tx (wp)); after the slave data is sent to the master SoC 100, the slave transmit ring buffer 220 is used to update a slave transmit buffer read pointer (S _ tx (rp)) according to an update notification of the master receive buffer read pointer, wherein the slave transmit buffer write pointer and the slave transmit buffer read pointer are used to indicate the write and read status of the slave transmit ring buffer 220, respectively.

Please refer to fig. 1. The master SoC 100 further comprises a master interface circuit 104 for transmitting the master data to the slave SoC200, receiving the update notification of the slave receive buffer read pointer from the slave SoC, receiving the slave data from the slave SoC200, and transmitting the update notification of the master receive buffer read pointer to the slave SoC 200. Similarly, the slave SoC200 further comprises a slave interface circuit 204 for receiving the master-side data from the master SoC 100, transmitting the update notification of the slave receive buffer read pointer to the master SoC 100, transmitting the slave-side data to the master SoC 100, and receiving the update notification of the master receive buffer read pointer from the master SoC. In the embodiment, the master interface circuit 104 and the slave interface circuit 204 are both known Universal Serial Bus (USB) interface circuits, but the implementation of the present invention is not limited thereto, and the two interface circuits 104 and 204 may also be interface circuits conforming to other protocols, such as known peripheral component interconnect Express (PCI Express, PCIe) interface circuits. It is noted that, compared to the prior art, the host interface circuit 104 can store the slave data in the host ring buffer 120 without using other buffers, so that the procedure of copying the slave data by the other buffers can be omitted; similarly, the slave interface circuit 204 can store the master data in the slave receive ring buffer 210 without using other buffers, and thus can omit the procedure for copying the master data from the other buffers.

Please refer to fig. 1. To simplify the read and write synchronization operation between the master transmit ring buffer 110 and the slave receive ring buffer 210, the buffer size of the master transmit ring buffer 110 may be equal to the buffer size of the slave receive ring buffer 210; in other words, the slave receive ring buffer may be a duplicate of the master transmit ring buffer to facilitate synchronization of the read and write pointers of both parties. Similarly, to simplify the read and write synchronization between the slave transmit ring buffer 220 and the master receive ring buffer 120, the buffer size of the slave transmit ring buffer 220 may be equal to the buffer size of the master receive ring buffer 120 to facilitate the synchronization of the read and write pointers of both parties. It should be noted that, as long as the buffer size ratio of the two buffers is known, one skilled in the art can calculate the corresponding relationship of the pointers of the two buffers according to the ratio to synchronize the pointers of the two buffers; in other words, the buffer sizes of the two buffers are not necessarily equal. In addition, if the data amount of the master data is larger than the data amount of the slave data, the buffer size of the master transmit ring buffer 110 may be larger than the buffer size of the master receive ring buffer 120, and the buffer size of the slave receive ring buffer 210 may be larger than the buffer size of the slave transmit ring buffer 220; and vice versa.

Please refer to fig. 1. If the communication protocol (e.g., USB communication protocol) between the master SoC 100 and the slave SoC200 only allows the master SoC 100 to act as the master, the master SoC 100 may actively request the slave SoC200 to provide the update notification of the slave receive buffer read pointer after transmitting the master data to the slave SoC200, so as to update the master transmit buffer read pointer; in addition, the master SoC 100 may periodically or aperiodically actively query the slave SoC200 to learn the existence of the slave data before receiving the slave data, thereby requesting the slave SoC200 to send the slave data to the master SoC 100.

Please refer to fig. 1. Any of the master SoC 100 and the slave SoC200 of fig. 1 may be used as an embodiment of the data transmission circuit of the present disclosure. Since one of ordinary skill in the art can refer to the disclosure of the embodiment of fig. 1 to understand the details and variations of the embodiment of the data transmission circuit of the present disclosure, the repetitive and redundant description is omitted here.

Fig. 2 shows an embodiment of the data transmission method according to the present disclosure, which can accelerate data transmission between two system-on-a-chip (e.g., the master SoC 100 and the slave SoC200 of fig. 1). The embodiment of FIG. 2 is performed by a first system-on-a-chip (e.g., the master SoC 100 or the slave SoC200 of FIG. 1), comprising the steps of:

s22: receiving first end data from an upper layer circuit of the first system-on-chip by using a transmission ring buffer, and updating a transmission buffer write pointer according to the first end data;

s24: transmitting the first-side data of the transmit ring buffer to a second system-on-chip;

s26: updating a transmission buffer read pointer according to a read pointer update notification of the second system-on-chip;

s27: receiving the second end data of the second system-on-chip by using a receiving ring buffer, and updating a receiving buffer write pointer according to the second end data;

s28: after the upper layer circuit reads the second end data of the receiving ring buffer, updating a receiving buffer reading pointer; and

s29: sending an update notification of the read pointer of the receive buffer to the second SOC.

Since those skilled in the art can refer to the disclosure of the embodiment of fig. 1 to understand the details and variations of the embodiment of fig. 2, that is, the technical features of the embodiment of fig. 1 can be reasonably applied to the embodiment of fig. 2, the repeated and redundant descriptions are omitted here.

It should be noted that, when the implementation is possible, a person skilled in the art can selectively implement some or all of the technical features of any of the above embodiments, or selectively implement a combination of some or all of the technical features of the above embodiments, thereby increasing the flexibility in implementing the invention.

In summary, the present invention accelerates the data transmission between the two system-on-chips by synchronizing the read/write operations of the buffers of the two system-on-chips.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make variations on the technical features of the present invention according to the explicit or implicit contents of the present invention, and all such variations may fall within the scope of the patent protection sought by the present invention.

[ notation ] to show

10 data transmission system

100 Single chip of master control system (master control SoC)

102 master control end upper layer circuit

104 main control terminal interface circuit

110 master transmit ring buffer

120 master receive ring buffer

200 slave system single chip (slave SoC)

202 slave side upper layer circuit

204 slave interface circuit

210 slave receive ring buffer

220 slave transfer ring buffer

M _ TX (wp) Master Transmit buffer write pointer

M _ TX (rp) Master Transmit buffer read pointer

M _ RX (wp) Master receive buffer write pointer

M _ RX (rp) Master receive buffer read pointer

S _ RX (wp) Slave receive buffer write pointer

S _ RX (rp) Slave receive buffer read pointer

S _ TX (wp) Slave Transmit buffer write pointer

S _ TX (rp) Slave Transmit buffer read pointer

S22-S29.