阅读说明：本技术 一种片上一次可编程电路 (On-chip one-time programmable circuit ) 是由 万美琳 宋敏 杨柳 段威 游龙 于 2020-04-15 设计创作，主要内容包括：本发明公开一种片上一次可编程电路,由三个NMOS晶体管和两个片上熔丝组成。OTP(One Time Programming,一次可编程)电路的使能开关和烧写熔丝控制开关均由NMOS晶体管构成,NMOS晶体管的控制信号均工作在低压范围内,无须与OTP电路较高的烧写电压处于相同的电压域,避免了低压-高压电平转换器的使用。同时,NMOS晶体管的衬底均接地,所有NMOS晶体管共用相同的衬底,在版图布局过程中更加紧密,避免PMOS晶体管不同电压域所造成的N_well衬底之间间距要求过大的情况。因此,该种片上一次可编程电路优化了传统的OTP电路,大大节约了硬件开销。(The invention discloses an on-chip one-time programmable circuit which consists of three NMOS transistors and two on-chip fuses. The enable switch and the Programming fuse control switch of the OTP (One Time Programming) circuit are both composed of NMOS transistors, control signals of the NMOS transistors work in a low-voltage range, the voltage range is not required to be in the same voltage range as the higher Programming voltage of the OTP circuit, and the use of a low-voltage-high-voltage level converter is avoided. Meanwhile, the substrates of the NMOS transistors are grounded, all the NMOS transistors share the same substrate, the NMOS transistors are tighter in the layout process, and the condition that the distance between the N _ well substrates is too large due to different voltage domains of the PMOS transistors is avoided. Therefore, the on-chip one-time programmable circuit optimizes the traditional OTP circuit and greatly saves hardware cost.)

1. An on-chip one-time programmable circuit, comprising: the circuit comprises: the fuse on the chip comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first fuse on the chip, a second fuse on the chip, a first input end, a second input end, a third input end and an output end.

The circuit starts from a power supply end at the top to the bottom, a drain electrode of the first NMOS transistor is connected with a programming high-voltage power supply of the circuit, a grid electrode of the first NMOS transistor is connected with the first input end of a programming value signal of the circuit, a source electrode of the first NMOS transistor is connected with a drain electrode of the second NMOS transistor, a grid electrode of the second NMOS transistor is connected with the second input end of a reverse signal of the programming value of the circuit, a source electrode of the second NMOS transistor is connected with a drain electrode of the third NMOS transistor, a grid electrode of the third NMOS transistor is connected with the third input end of an enabling signal of the circuit, a source electrode of the third NMOS transistor is connected with a ground end of the circuit, fuses on the first sheet are connected with two source and drain ends of the first NMOS transistor in parallel, fuses on the second sheet are connected with two source and drain ends of the second NMOS transistor in parallel, the output end of the circuit is led out from the right end of the junction point of the source electrode of the first NMOS transistor and the drain electrode of the second NMOS transistor.

2. The circuit of claim 1, wherein: the control switches of the circuit all adopt NMOS transistors, control signals of the NMOS transistors all work in a low-voltage range, and all the NMOS transistors share one substrate; the fuse wire on the first chip and the fuse wire on the second chip adopt a resistor structure with a thin middle part and wide two ends; the resistor structure uses polysilicon in CMOS process devices or any metal layer.

3. A programming method using the programming circuit of any of claims 1-2, characterized by:

when the enable signal of the circuit is '0', the whole OTP circuit does not execute editing operation; when the enable signal is '1', the circuit starts editing, at this time, if the programming value signal is '1', the first NMOS transistor is turned on, the first on-chip fuse is shielded, the second NMOS transistor is turned off, the second on-chip fuse is turned on, the passing large current fuses the second on-chip fuse, and finally the signal of the output end is pulled up to '1' by the first on-chip fuse;

on the contrary, if the programming value signal is "0", the fuse on the first chip is blown, the fuse on the second chip is shielded, and finally the signal on the output end is pulled down to "0" by the fuse on the second chip.

Technical Field

The invention relates to a storage circuit in a system, in particular to an on-chip One Time Programming (OTP) circuit based on an NMOS transistor, belonging to the field of information security of integrated circuits.

Background

At present, an OTP circuit is a nonvolatile memory circuit, which mostly adopts a fuse structure, and only can be programmed and written once, and the programming process is irreversible destruction. Although the memory can be programmed only once, the memory is widely applied to integrated circuit design due to the characteristics of simple process, difficult data loss, strong anti-interference capability, small memory cell area, easy large-scale integration, low cost and the like.

In recent years, OTP circuits have been studied more and more, and these are of an efuse (fuse) type and an anti-use (anti-fuse) type. The structure of the fuse structure is generally formed by two conductive electrodes and a fuse layer sandwiched between the conductive electrodes, wherein the fuse layer can be made of polysilicon or metal and the like. The fuse type OTP circuit is normally in a permanent conducting state by utilizing the characteristics of a composition structure of the fuse type OTP circuit, and when the fuse is electrified and conducted, current flows through the fuse to cause the fuse to be fused, the fuse is in an open circuit state, so that the resistance value of the fuse is changed from dozens of ohms to thousands of ohms, the open circuit state is kept all the time, and finally the purpose of one-time programming is realized. On the contrary, the antifuse-type OTP memory circuit has a very high resistance value, which can reach several hundred mega ohms, is in an open circuit state and does not provide a current path when not programmed; once programmed, the resistance value decreases to tens of ohms or even lower, remaining permanently in the short-circuit condition, allowing current to pass. Both OTP circuits use "breakdown of dielectric" to determine the "fuse or antifuse programmed" condition. This breakdown phenomenon does not occur when not programmed, and thus the programmed state is very definite and unrecoverable, and the open state of the fuse-type OTP circuit or the short state of the antifuse-type OTP circuit is not affected no matter how many times the subsequent reading process is repeated. It is this simplicity and certainty that both OTP circuits become indispensable.

A typical OTP circuit is shown in fig. 1 and includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a first on-chip fuse, and a second on-chip fuse having two input terminals and an output terminal. The circuit is from a top power supply end to a bottom power supply end, a source electrode of a first PMOS transistor is connected with a programming high-voltage power supply of the circuit, a grid electrode of the first PMOS transistor is connected with an enabling signal of the circuit, a drain electrode of the first PMOS transistor is connected with a source electrode of a second PMOS transistor, a grid electrode of the second PMOS transistor is connected with a grid electrode of a first NMOS transistor, a drain electrode of the second PMOS transistor is connected with a drain electrode of the first NMOS transistor, a source electrode of the first NMOS transistor is connected with a ground end of the circuit, an upper fuse wire of a first chip is connected in parallel with two source-drain ends of the second PMOS transistor, an upper fuse wire of a second chip is connected in parallel with two source-drain ends of the first NMOS transistor, an input end of the circuit is led out from the left end of a grid electrode node of the second PMOS transistor and a grid electrode of the first NMOS transistor, and an output end of the circuit is led out. The enable signal of the circuit determines whether the entire OTP circuit can be edited. When the enable signal is "1", the OTP circuit does not operate. When the enable signal is '0', the OTP circuit starts normal editing, at the moment, if the programming value is '0', the second PMOS transistor is conducted, the fuse wire on the first chip is shielded, the first NMOS transistor is cut off, the fuse wire on the second chip is conducted, the passing large current enables the fuse wire on the second chip to be fused, and the output value of the OTP circuit is pulled up to '1' by the fuse wire on the first chip; on the contrary, if the programming value is "1", the fuse on the first chip is blown, the fuse on the second chip is shielded, and the output value of the OTP circuit is pulled down to "0" by the fuse on the second chip. As shown in fig. 2, in the layout process, all NMOS transistors share the same substrate, PMOS transistors must be separately fabricated in N _ well with a certain potential, and N _ well layers with different potentials are different and need to satisfy a certain distance limitation, so that each memory cell has a relatively large area, and the design cost is increased.

Disclosure of Invention

In view of the problems in the prior art, the present invention provides an on-chip one-time programmable circuit, which is characterized in that: the circuit comprises: the fuse on the chip comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first fuse on the chip, a second fuse on the chip, a first input end, a second input end, a third input end and an output end.

The circuit starts from a power supply end at the top to the bottom, a drain electrode of the first NMOS transistor is connected with a programming high-voltage power supply of the circuit, a grid electrode of the first NMOS transistor is connected with the first input end of a programming value signal of the circuit, a source electrode of the first NMOS transistor is connected with a drain electrode of the second NMOS transistor, a grid electrode of the second NMOS transistor is connected with the second input end of a reverse signal of the programming value of the circuit, a source electrode of the second NMOS transistor is connected with a drain electrode of the third NMOS transistor, a grid electrode of the third NMOS transistor is connected with the third input end of an enabling signal of the circuit, a source electrode of the third NMOS transistor is connected with a ground end of the circuit, fuses on the first sheet are connected with two source and drain ends of the first NMOS transistor in parallel, fuses on the second sheet are connected with two source and drain ends of the second NMOS transistor in parallel, the output end of the circuit is led out from the right end of the junction point of the source electrode of the first NMOS transistor and the drain electrode of the second NMOS transistor.

Preferably, all the control switches of the circuit adopt NMOS transistors, control signals of the NMOS transistors work in a low-voltage range, and all the NMOS transistors share one substrate; the fuse wire on the first chip and the fuse wire on the second chip adopt a resistor structure with a thin middle part and wide two ends; the resistor structure uses polysilicon in CMOS process devices or any metal layer.

The invention also provides a programming method using the programming circuit, when the enable signal of the circuit is '0', the whole OTP circuit does not execute editing operation; when the enable signal is '1', the circuit starts editing, at this time, if the programming value signal is '1', the first NMOS transistor is turned on, the first on-chip fuse is shielded, the second NMOS transistor is turned off, the second on-chip fuse is turned on, the passing large current fuses the second on-chip fuse, and finally the signal of the output end is pulled up to '1' by the first on-chip fuse;

on the contrary, if the programming value signal is "0", the fuse on the first chip is blown, the fuse on the second chip is shielded, and finally the signal on the output end is pulled down to "0" by the fuse on the second chip.

Compared with the prior art, the invention at least has the following beneficial effects:

the OTP circuit is realized by adopting the simple NMOS transistor compatible with the standard CMOS process, the normal programming of the fuse on the chip can be fully ensured, meanwhile, the scheme not only reduces the use of a level converter module, but also effectively avoids the requirement of the distance between the substrates of the PMOS transistors at different potentials, greatly saves the hardware overhead and reduces the cost.

Drawings

FIG. 1 is a schematic diagram of a prior art OTP circuit;

FIG. 2 is a schematic diagram of a planar structure of a prior art CMOS device;

FIG. 3 is a schematic diagram of an OTP circuit of the invention;

FIG. 4 is a schematic diagram of an on-chip fuse structure according to the present invention.

Detailed Description

Embodiments of the invention are further described below with reference to the drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below are exemplary and are intended to be illustrative, but not limiting, of the present invention, and any modifications, equivalents, or improvements made within the spirit and principle of the present invention, which are not described in detail in the technical solutions below, are known in the art, and are intended to be included within the scope of the claims of the present invention.

Implementation example:

in order to solve the problem of the prior art, the present invention uses NMOS transistors as control switches of the circuit, as shown in fig. 3, the OTP circuit is composed of an enable switch NMOS transistor, two control switch NMOS transistors, and two on-chip fuses, from top to bottom, the drain of the first NMOS transistor is connected to the OTP burning high voltage power supply VDD, the gate of the first NMOS transistor is connected to the burning value signal OTP _ VA L UE of the OTP circuit, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second NMOS transistor is connected to the reverse burning value signal OTP _ VA L UE _ N of the OTP circuit, the source of the second NMOS transistor is connected to the drain of the third NMOS transistor, the source of the third NMOS transistor is connected to the enable signal OTP circuit OTPEN, the source of the third NMOS transistor is connected to the GND of the OTP circuit, the first on-chip fuse is connected to both source and drain of the first NMOS transistor in parallel, and the second on-chip fuse is connected to both source and drain of the second NMOS transistor, the second on-side of the OTP circuit, the output signal OTP circuit is connected to the high voltage signal OTP _ v 2, when the high voltage signal is pulled to the high voltage signal OTP _ VA 630, the high voltage signal is equal to the high voltage signal output from the upper end of the lower fuse, the upper gate of the upper fuse, the upper fuse is considered as the lower fuse, the upper control switch, and the upper fuse, the upper gate of the lower gate of the PMOS transistor, and lower gate of the upper gate of the lower gate of the PMOS transistor, the lower gate of the upper gate of the.

Figure 4 is a schematic diagram of an on-chip fuse structure. The two end parts are wider, and the middle part is slender. The material of the on-chip fuse can be poly polysilicon in a CMOS process, and can also be any metal layer. When a large voltage is applied to the two ends of the on-chip fuse, the middle slender part of the on-chip fuse is fused by the large current, and the connection relation of the two ends is broken.

The applicant declares that the present invention illustrates the detailed structural features of the present invention through the above embodiments, but the present invention is not limited to the above detailed structural features, that is, it does not mean that the present invention must be implemented depending on the above detailed structural features. It should be understood by those skilled in the art that any modifications of the present invention, equivalent substitutions of selected components of the present invention, additions of auxiliary components, selection of specific modes, etc., are within the scope and disclosure of the present invention.

The preferred embodiments of the present invention have been described in detail, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.

It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.