阅读说明：本技术 一种六轴驱控一体机 (Six drive accuse all-in-one ) 是由 李兴桂 周永森 蒋学程 刘金建 冯招程 于 2020-03-20 设计创作，主要内容包括：本发明涉及一种六轴驱控一体机,用于连接和控制伺服电机或是步进电机,包括壳体以及设置在壳体内的电路板,所述壳体为上盖板与下盖板组成的盒体,所述上盖板包括一体成型的一顶板、一前侧板和两侧板,所述下盖板包括一体成型的一底板和一后侧板。使用一个电路板既可以驱动6个步进电机,也可以驱动6个伺服电机；也可以驱动一部分步进电机,另外一部分驱动伺服电机；实现了使用一个电路板,可以将控制算法和驱动算法全部放进此电路板里。(The invention relates to a six-shaft driving and controlling integrated machine which is used for connecting and controlling a servo motor or a stepping motor and comprises a shell and a circuit board arranged in the shell, wherein the shell is a box body consisting of an upper cover plate and a lower cover plate, the upper cover plate comprises a top plate, a front side plate and two side plates which are integrally formed, and the lower cover plate comprises a bottom plate and a rear side plate which are integrally formed. One circuit board can drive 6 stepping motors and also can drive 6 servo motors; or drive a part of stepping motors, and the other part drives servo motors; the control algorithm and the driving algorithm can be completely put into the circuit board by using one circuit board.)

1. The utility model provides a six drive accuse all-in-one which characterized in that: the connector comprises a shell and a circuit board arranged in the shell, wherein the shell is a box body consisting of an upper cover plate and a lower cover plate, the upper cover plate comprises a top plate, a front side plate and two side plates which are integrally formed, the bottoms of the two side plates are provided with press edges which are turned outwards, the press edges are provided with a first fixed hole group, the two side plates are transversely provided with heat dissipation holes in an array manner, a plurality of interface hole sites for installing interfaces are transversely distributed on the front side plate, and the rear side edge of the top plate is symmetrically provided with positioning convex parts;

the lower cover plate comprises a bottom plate and a rear side plate which are integrally formed, a plurality of interface hole sites for installing interfaces are arranged on the rear side plate at equal intervals in the horizontal direction, and a positioning concave part is arranged on the edge of the upper part of the rear side plate; the upper surface of the bottom plate is provided with a second fixed hole group, a third fixed hole group and a fourth fixed hole group, and the lower surface of the bottom plate is provided with radiating fins; the upper surface of the bottom plate is provided with a mounting groove;

the circuit board comprises double computing cores and an isolation power supply circuit, six motor driving circuits, a back electromotive force release circuit, an external isolation input circuit, an external isolation output circuit and a bus voltage acquisition circuit which are connected with the double computing cores respectively, wherein each motor driving circuit module is connected with a motor and used for connecting and controlling a servo motor or a stepping motor.

2. The six-axis drive and control integrated machine according to claim 1 is characterized in that the double computing cores comprise a TMS320F28375S type DSP chip and an XC6S L X16-2CSG324 type FPGA chip, the DSP chip is connected with the FPGA chip through an expansion bus, the motor driving circuit comprises a first H bridge circuit, a second H bridge circuit, a third H bridge circuit and a fourth H bridge circuit, an E16 pin of the FPGA chip is connected with an S1AP _ H signal, a G13 pin of the FPGA chip is connected with an S1AP _ L signal, an H12 pin of the FPGA chip is connected with an S1AN _ H signal, a D18 pin of the FPGA chip is connected with an S1AN _ L signal, a D17 pin of the FPGA chip is connected with an S1BP _ H signal, a G14 pin of the FPGA chip is connected with an S1 _ L signal, an F14 pin of the FPGA chip is connected with an S1BN H signal, and a C18 pin of the FPGA chip is connected with an S1 _ 599 signal.

3. The six-axis drive and control integrated machine according to claim 2, characterized in that: the first H-bridge circuit comprises an optical coupler U1, an optical coupler U4, an MOS tube Q2, an MOS tube Q3 and an isolated Hall current sensor U3; a 6 th pin of the optocoupler U1 is connected with a capacitor C5 and the cathode of a diode D1, the anode of the diode D1 is connected to a 15V high level through a resistor R1, the other end of the capacitor C5 is connected with a 4 th pin of the optocoupler U1, and the 4 th pin of the optocoupler U1 is connected with one end of the resistor R5 and a 3 rd pin of a MOS transistor Q2; a 5 th pin of the optical coupler U1 is connected with the other end of the resistor R5, a 5 th pin of the optical coupler U1 is connected with a1 st pin of the MOS tube Q2, and a 2 nd pin of the MOS tube Q2 is connected to a 48V high level; pin 3 of the optocoupler U1 is grounded; the 1 st pin of the optical coupler U1 is connected with the E16 pin of the FPGA chip through a resistor R3;

a 6 th pin of the optical coupler U4 is connected with one ends of a capacitor C8 and a resistor R9, the other end of the resistor R9 is connected to a high level of 15V, the other end of the capacitor C8 is connected with a 4 th pin of the optical coupler U4, and a 4 th pin of the optical coupler U4 is connected with one end of the resistor R12 and a 3 rd pin of the MOS transistor Q3; a 5 th pin of the optical coupler U4 is connected with the other end of the resistor R12, a 5 th pin of the optical coupler U4 is connected with a1 st pin of the MOS tube Q3, and a 3 rd pin of the MOS tube Q3 is connected to a high-voltage ground; pin 3 of the optocoupler U4 is grounded; the 1 st pin of the optical coupler U4 is connected with the G13 pin of the FPGA chip through a resistor R11; a 2 nd pin of the MOS tube Q3 is connected with a 3 rd pin of the MOS tube Q2, a 2 nd pin of the MOS tube Q3 is connected with a 3 rd pin and a 4 th pin of the isolation Hall current sensor U3, an 8 th pin of the isolation Hall current sensor U3 is connected with a 5V high level, a 7 th pin of the isolation Hall current sensor U3 is connected to an AD conversion function interface of the DSP chip through a resistor R7, and is grounded through a resistor R8; the 6 th pin of the isolation Hall current sensor U3 is grounded through a capacitor C7, and the 5 th pin of the isolation Hall current sensor U3 is grounded; the 1 st pin and the 2 nd pin of the isolation Hall current sensor U3 are connected in parallel and are connected to the 1 st pin of the motor socket J2, and a signal M1A + _ U is output.

4. The six-axis drive and control integrated machine according to claim 2, characterized in that: the second H-bridge circuit comprises an optical coupler U7, an optical coupler U11, an MOS tube Q5 and an MOS tube Q6; a 6 th pin of the optocoupler U7 is connected with a capacitor C9 and the cathode of a diode D4, the anode of the diode D4 is connected to a 15V high level through a resistor R15, the other end of the capacitor C9 is connected with a 4 th pin of the optocoupler U7, and the 4 th pin of the optocoupler U7 is connected with one end of the resistor R22 and a 3 rd pin of a MOS transistor Q5; a 5 th pin of the optical coupler U7 is connected with the other end of the resistor R22, a 5 th pin of the optical coupler U7 is connected with a1 st pin of the MOS tube Q5, and a 2 nd pin of the MOS tube Q5 is connected to a 48V high level; pin 3 of the optocoupler U7 is grounded; the 1 st pin of the optical coupler U7 is connected with the H12 pin of the FPGA chip through a resistor R26;

a 6 th pin of the optical coupler U11 is connected with one ends of a capacitor C12 and a resistor R29, the other end of the resistor R29 is connected to a high level of 15V, the other end of the capacitor C12 is connected with a 4 th pin of the optical coupler U11, and a 4 th pin of the optical coupler U11 is connected with one end of the resistor R33 and a 3 rd pin of the MOS transistor Q6; a 5 th pin of the optical coupler U11 is connected with the other end of the resistor R33, a 5 th pin of the optical coupler U11 is connected with a1 st pin of the MOS tube Q6, and a 3 rd pin of the MOS tube Q6 is connected to a high-voltage ground; pin 3 of the optocoupler U11 is grounded; the 1 st pin of the optical coupler U11 is connected with the D18 pin of the FPGA chip through a resistor R32; pin 2 of MOS transistor Q6 and pin 3 of MOS transistor Q5 are connected together and to pin 2 of motor socket J2, outputting signal M1A- _ V.

5. The six-axis drive and control integrated machine according to claim 2, characterized in that: the third H-bridge circuit comprises an optical coupler U13, an optical coupler U17, an MOS tube Q8, an MOS tube Q9 and an isolated Hall current sensor U14; a 6 th pin of the optocoupler U13 is connected with a capacitor C14 and the cathode of a diode D6, the anode of the diode D6 is connected to a 15V high level through a resistor R39, the other end of the capacitor C14 is connected with a 4 th pin of the optocoupler U13, and the 4 th pin of the optocoupler U13 is connected with one end of the resistor R42 and a 3 rd pin of a MOS transistor Q8; a 5 th pin of the optical coupler U13 is connected with the other end of the resistor R42, a 5 th pin of the optical coupler U13 is connected with a1 st pin of the MOS tube Q8, and a 2 nd pin of the MOS tube Q8 is connected to a 48V high level; pin 3 of the optocoupler U13 is grounded; the 1 st pin of the optical coupler U13 is connected with the D17 pin of the FPGA chip through a resistor R41;

a 6 th pin of the optical coupler U17 is connected with one end of a capacitor 19 and a resistor R49, the other end of the resistor R49 is connected to a high level of 15V, the other end of the capacitor C19 is connected with a 4 th pin of an optical coupler U17, and a 4 th pin of the optical coupler U17 is connected with one end of a resistor R54 and a 3 rd pin of a MOS tube Q9; a 5 th pin of the optical coupler U17 is connected with the other end of the resistor R54, a 5 th pin of the optical coupler U17 is connected with a1 st pin of the MOS tube Q9, and a 3 rd pin of the MOS tube Q9 is connected to a high-voltage ground; pin 3 of the optocoupler U17 is grounded; the 1 st pin of the optical coupler U17 is connected with the G14 pin of the FPGA chip through a resistor R57; a 2 nd pin of the MOS tube Q9 is connected with a 3 rd pin of the MOS tube Q8, a 2 nd pin of the MOS tube Q9 is connected with a 3 rd pin and a 4 th pin of the isolation Hall current sensor U14, an 8 th pin of the isolation Hall current sensor U14 is connected with a 5V high level, a 7 th pin of the isolation Hall current sensor U14 is connected to an AD conversion function interface of the DSP chip through a resistor R44, and is grounded through a resistor R46; the 6 th pin of the isolation Hall current sensor U14 is grounded through a capacitor C18, and the 5 th pin of the isolation Hall current sensor U14 is grounded; the 1 st pin and the 2 nd pin of the isolation Hall current sensor U14 are connected in parallel and are connected to the 3 rd pin of the motor socket J2, and a signal M1B + _ W is output.

6. The six-axis drive and control integrated machine according to claim 2, characterized in that: the fourth H-bridge circuit comprises an optical coupler U18, an optical coupler U19, an MOS tube Q10 and an MOS tube Q11; a 6 th pin of the optocoupler U18 is connected with a capacitor C24 and the cathode of a diode D7, the anode of the diode D7 is connected to a 15V high level through a resistor R60, the other end of the capacitor C24 is connected with a 4 th pin of the optocoupler U18, and the 4 th pin of the optocoupler U18 is connected with one end of the resistor R63 and a 3 rd pin of a MOS transistor Q10; a 5 th pin of the optical coupler U18 is connected with the other end of the resistor R63, a 5 th pin of the optical coupler U18 is connected with a1 st pin of the MOS tube Q10, and a 2 nd pin of the MOS tube Q10 is connected to a 48V high level; pin 3 of the optocoupler U18 is grounded; the 1 st pin of the optical coupler U18 is connected with the pin F14 of the FPGA chip through a resistor R61;

a 6 th pin of the optical coupler U19 is connected with one ends of a capacitor C25 and a resistor R65, the other end of the resistor R65 is connected to a high level of 15V, the other end of the capacitor C25 is connected with a 4 th pin of the optical coupler U19, and a 4 th pin of the optical coupler U19 is connected with one end of the resistor R68 and a 3 rd pin of the MOS transistor Q11; a 5 th pin of the optical coupler U19 is connected with the other end of the resistor R68, a 5 th pin of the optical coupler U19 is connected with a1 st pin of the MOS tube Q11, and a 3 rd pin of the MOS tube Q11 is connected to a high-voltage ground; pin 3 of the optocoupler U19 is grounded; the 1 st pin of the optical coupler U19 is connected with the C18 pin of the FPGA chip through a resistor R67; the 2 nd pin of the MOS transistor Q11 and the 3 rd pin of the MOS transistor Q10 are connected together and connected to the 4 th pin of the motor socket J2, and the signal M1B-GND is output.

7. The six-axis drive and control integrated machine according to claim 1 is characterized in that the external isolation input circuit comprises a photoelectric coupler E L357 NB U8, a1 st pin of the photoelectric coupler E L357 NB U8 is connected with one end of a resistor R28, a 2 nd pin is connected with a resistor R30 and an anode of a diode D3, a 3 rd pin is grounded, a 4 th pin is connected with one ends of a resistor R24 and a resistor R27, a cathode of the diode D3 and the other end of a resistor R28 are connected to a 24V high level, the other end of the resistor R27 is connected to a 3.3V high level, and the other end of the resistor R24 is grounded through a capacitor C11 and is simultaneously connected to a double-computation core.

8. The six-shaft drive-control all-in-one machine according to claim 1 is characterized in that the external isolation output circuit comprises a photoelectric coupler E L357 NB 12, a1 st pin of the photoelectric coupler E L NB U12 is connected with one end of a resistor R35, a 2 nd pin is grounded, a 3 rd pin is connected with one ends of a resistor R37 and a resistor R38, the other end of the resistor R38 is connected with a GND-HV high-voltage ground, a 4 th pin is connected with a 24V high level, the other end of the resistor R35 is grounded through a resistor R36 and simultaneously connected to a double computing core, the other end of the resistor R37 is connected with a base of a triode Q7, a collector of the triode Q7, an emitter of the triode Q7 is connected with the high-voltage ground and a capacitor C13, a collector of the triode Q7 and the other end of a capacitor C13 are connected with an anode of a diode D5, and a cathode of a diode D.

9. The six-axis drive-control all-in-one machine according to claim 1, wherein the back electromotive force relief circuit comprises an isolation driver ACP-W314U and a NAND gate logic chip SN74AHCT1G00DBV U, a 3 rd pin of the isolation driver ACP-W314U is connected with one end of a resistor R and one end of the resistor R, the other end of the resistor R is connected with a1 st pin of the isolation driver ACP-W314U and connected to a 5V high level through the resistor R, a 6 th pin of the isolation driver ACP-W314U is connected with a 15V high level, a 4 th pin of the isolation driver ACP-W314U is connected to a high voltage ground, a 5 th pin of the isolation driver ACP-W314U is connected with the 1 st pin of the resistor R and the MOS tube Q, the other end of the R is connected to the high voltage ground, a 3 rd pin of the MOS tube Q is connected to the high voltage ground, a 2 nd pin of the MOS tube Q is connected with an anode of a diode D and a 2 nd pin of the high power cement resistor J, a cathode of the diode D is connected with the 1 st pin of the high power resistor SN J and the NAND gate logic chip SN 5V core SN 5V 1 SN74, the NAND gate logic chip SN 3V core SN74 is connected to the NAND gate logic chip SN 5V 1 SN 3V CT of the NAND gate logic chip SN 5 SN U, the NAND gate logic chip SN 5 SN V CT and the NAND gate logic chip SN 5 SN V CT 3V CT U are connected together through the NAND gate logic chip SN 5 SN V CT.

10. The six-axis drive and control integrated machine according to claim 1, characterized in that: the isolation power supply circuit is a 15W power supply module URB4805YMD-15WR3 with the external input direct-current voltage of + VH48V, and isolation conversion from 48V to 5V is realized;

the bus voltage acquisition circuit comprises voltage isolation sensors ACP-C87U and T V2371 IDBVU, wherein the 2 nd pin of the voltage isolation sensors ACP 0-C87U is connected with a resistor R, the other end of the resistor R is connected with one end of a capacitor C, one end of the resistor R and one end of the resistor R, the other end of the resistor R is connected with a 48V high level, the other end of the resistor R is connected with the other end of the capacitor C and is connected to a high voltage ground, the 3 rd pin of the voltage isolation sensors ACP 1-C87U is connected with the 4 th pin and is connected to the high voltage ground, the 1 st pin of the voltage isolation sensors ACP 2-C87U is connected to the 5V high level, the 8 th pin of the voltage isolation sensors ACP 3-C87U is connected to the 5V high level, the 5 th pin of the voltage isolation sensors ACP 4-C87U is connected to the ground, the 7 th pin of the voltage isolation sensors ACP 5-C87AU is connected with the 3 rd pin of the T6V IDU through the resistor R71 BV 71, the first pin of the BV 71U is connected with the other end of the resistor C71V 23U, the resistor R71 and the resistor R71, the other end of the resistor R71 is connected with the resistor R71 and the resistor R71 of the capacitor C235V resistor R71, the other end of the capacitor C71, the resistor R71 and the resistor R71, the resistor R71 is connected to the resistor R71, the resistor BV 71 and the other end of the capacitor C71 and the capacitor C71, the capacitor C71 is connected to the resistor 71, the.

Technical Field

The invention relates to the technical field of drive control, in particular to a six-axis drive control all-in-one machine.

Background

For a plurality of applications (such as a screw machine, a glue dispenser, a welding machine, an AGV trolley, a SCARA robot and the like) in the market, a 6-axis stepping system or a 6-axis servo system of low-voltage direct current can be adopted. Wherein, a 6-axis stepping system generally adopts a mode of one motion controller, 6 low-voltage direct-current stepping drivers and 6 stepping motors; wherein the motion controller is connected with each stepping driver through an external connection; and each stepper driver is connected to the A +, A-, B +, B-of the stepper motor through a power line.

For a low-voltage direct-current 6-axis servo system in the market, a motion controller is generally adopted, and 6 low-voltage direct-current servo drivers and 6 servo motors are added; wherein the motion controller is connected with each servo driver through an external connection; each servo driver is connected to U, V, W, GND of the servo motor through a power line; installation and line connection are complicated, and 6 motors can produce the back electromotive force and raise the problem of busbar voltage after getting up. At present, six-shaft drive and control integrated cabinet machines on the market all adopt a cabinet type structure; a plurality of circuit boards are arranged inside; the whole volume is relatively large.

Disclosure of Invention

In order to solve the above problems, the present invention provides a six-axis driving and controlling integrated machine, which integrates the functions of 6 low-voltage dc drivers and the function of motion control on the same circuit board; six motors are driven by one circuit board (the 6 motors can be all servo motors, the 6 motors can be all stepping motors, even a part of the motors can be servo motors, and the rest is stepping motors).

The embodiment of the invention is realized by adopting the following scheme: the six-axis driving and controlling integrated machine comprises a shell and a circuit board arranged in the shell, wherein the shell is a box body consisting of an upper cover plate and a lower cover plate, the upper cover plate comprises a top plate, a front side plate and two side plates which are integrally formed, the bottoms of the two side plates are provided with press edges which are folded outwards, the press edges are provided with a first fixed hole group, heat dissipation holes are transversely arranged on the two side plates in an array mode, a plurality of interface hole sites for installing interfaces are transversely distributed on the front side plate, and positioning convex parts are symmetrically arranged on the rear side edge of the top plate; the lower cover plate comprises a bottom plate and a rear side plate which are integrally formed, a plurality of interface hole sites for installing interfaces are arranged on the rear side plate at equal intervals in the horizontal direction, and a positioning concave part is arranged on the edge of the upper part of the rear side plate; the upper surface of the bottom plate is provided with a second fixed hole group, a third fixed hole group and a fourth fixed hole group, and the lower surface of the bottom plate is provided with radiating fins; the upper surface of the bottom plate is provided with a mounting groove;

the circuit board comprises double computing cores and an isolation power supply circuit, six motor driving circuits, a back electromotive force release circuit, an external isolation input circuit, an external isolation output circuit and a bus voltage acquisition circuit which are connected with the double computing cores respectively, wherein each motor driving circuit module is connected with a motor and used for connecting and controlling a servo motor or a stepping motor.

In one embodiment of the invention, the double-computing core comprises a TMS320F28375S type DSP chip and an XC6S L X16-2CSG324 type FPGA chip, the DSP chip is connected with the FPGA chip through an expansion bus, the motor driving circuit comprises a first H bridge circuit, a second H bridge circuit, a third H bridge circuit and a fourth H bridge circuit, an E16 pin of the FPGA chip is connected with an S1AP _ H signal, a G13 pin of the FPGA chip is connected with an S1AP _ L signal, an H12 pin of the FPGA chip is connected with an S1AN _ H signal, a D18 pin of the FPGA chip is connected with an S1AN _ L signal, a D17 pin of the FPGA chip is connected with an S1BP _ H signal, a G14 pin of the FPGA chip is connected with an S1BP _ L signal, an F14 pin of the FPGA chip is connected with an S1BN _ H signal, and a C63 18 pin of the FPGA chip is connected with an S1 _ 5928 signal;

in an embodiment of the present invention, the first H-bridge circuit includes an optical coupler U1, an optical coupler U4, a MOS transistor Q2, a MOS transistor Q3, and an isolation hall current sensor U3; a 6 th pin of the optocoupler U1 is connected with a capacitor C5 and the cathode of a diode D1, the anode of the diode D1 is connected to a 15V high level through a resistor R1, the other end of the capacitor C5 is connected with a 4 th pin of the optocoupler U1, and the 4 th pin of the optocoupler U1 is connected with one end of the resistor R5 and a 3 rd pin of a MOS transistor Q2; a 5 th pin of the optical coupler U1 is connected with the other end of the resistor R5, a 5 th pin of the optical coupler U1 is connected with a1 st pin of the MOS tube Q2, and a 2 nd pin of the MOS tube Q2 is connected to a 48V high level; pin 3 of the optocoupler U1 is grounded; the 1 st pin of the optical coupler U1 is connected with the E16 pin of the FPGA chip through a resistor R3;

a 6 th pin of the optical coupler U4 is connected with one ends of a capacitor C8 and a resistor R9, the other end of the resistor R9 is connected to a high level of 15V, the other end of the capacitor C8 is connected with a 4 th pin of the optical coupler U4, and a 4 th pin of the optical coupler U4 is connected with one end of the resistor R12 and a 3 rd pin of the MOS transistor Q3; a 5 th pin of the optical coupler U4 is connected with the other end of the resistor R12, a 5 th pin of the optical coupler U4 is connected with a1 st pin of the MOS tube Q3, and a 3 rd pin of the MOS tube Q3 is connected to a high-voltage ground; pin 3 of the optocoupler U4 is grounded; the 1 st pin of the optical coupler U4 is connected with the G13 pin of the FPGA chip through a resistor R11; a 2 nd pin of the MOS tube Q3 is connected with a 3 rd pin of the MOS tube Q2, a 2 nd pin of the MOS tube Q3 is connected with a 3 rd pin and a 4 th pin of the isolation Hall current sensor U3, an 8 th pin of the isolation Hall current sensor U3 is connected with a 5V high level, a 7 th pin of the isolation Hall current sensor U3 is connected to an AD conversion function interface of the DSP chip through a resistor R7, and is grounded through a resistor R8; the 6 th pin of the isolation Hall current sensor U3 is grounded through a capacitor C7, and the 5 th pin of the isolation Hall current sensor U3 is grounded; the 1 st pin and the 2 nd pin of the isolation Hall current sensor U3 are connected in parallel and are connected to the 1 st pin of the motor socket J2, and a signal M1A + _ U is output.

In an embodiment of the present invention, the second H-bridge circuit includes an optical coupler U7, an optical coupler U11, a MOS transistor Q5, and a MOS transistor Q6; a 6 th pin of the optocoupler U7 is connected with a capacitor C9 and the cathode of a diode D4, the anode of the diode D4 is connected to a 15V high level through a resistor R15, the other end of the capacitor C9 is connected with a 4 th pin of the optocoupler U7, and the 4 th pin of the optocoupler U7 is connected with one end of the resistor R22 and a 3 rd pin of a MOS transistor Q5; a 5 th pin of the optical coupler U7 is connected with the other end of the resistor R22, a 5 th pin of the optical coupler U7 is connected with a1 st pin of the MOS tube Q5, and a 2 nd pin of the MOS tube Q5 is connected to a 48V high level; pin 3 of the optocoupler U7 is grounded; the 1 st pin of the optical coupler U7 is connected with the H12 pin of the FPGA chip through a resistor R26;

a 6 th pin of the optical coupler U11 is connected with one ends of a capacitor C12 and a resistor R29, the other end of the resistor R29 is connected to a high level of 15V, the other end of the capacitor C12 is connected with a 4 th pin of the optical coupler U11, and a 4 th pin of the optical coupler U11 is connected with one end of the resistor R33 and a 3 rd pin of the MOS transistor Q6; a 5 th pin of the optical coupler U11 is connected with the other end of the resistor R33, a 5 th pin of the optical coupler U11 is connected with a1 st pin of the MOS tube Q6, and a 3 rd pin of the MOS tube Q6 is connected to a high-voltage ground; pin 3 of the optocoupler U11 is grounded; the 1 st pin of the optical coupler U11 is connected with the D18 pin of the FPGA chip through a resistor R32; pin 2 of MOS transistor Q6 and pin 3 of MOS transistor Q5 are connected together and to pin 2 of motor socket J2, outputting signal M1A- _ V.

In an embodiment of the present invention, the third H-bridge circuit includes an optical coupler U13, an optical coupler U17, a MOS transistor Q8, a MOS transistor Q9, and an isolation hall current sensor U14; a 6 th pin of the optocoupler U13 is connected with a capacitor C14 and the cathode of a diode D6, the anode of the diode D6 is connected to a 15V high level through a resistor R39, the other end of the capacitor C14 is connected with a 4 th pin of the optocoupler U13, and the 4 th pin of the optocoupler U13 is connected with one end of the resistor R42 and a 3 rd pin of a MOS transistor Q8; a 5 th pin of the optical coupler U13 is connected with the other end of the resistor R42, a 5 th pin of the optical coupler U13 is connected with a1 st pin of the MOS tube Q8, and a 2 nd pin of the MOS tube Q8 is connected to a 48V high level; pin 3 of the optocoupler U13 is grounded; the 1 st pin of the optical coupler U13 is connected with the D17 pin of the FPGA chip through a resistor R41;

a 6 th pin of the optical coupler U17 is connected with one end of a capacitor 19 and a resistor R49, the other end of the resistor R49 is connected to a high level of 15V, the other end of the capacitor C19 is connected with a 4 th pin of an optical coupler U17, and a 4 th pin of the optical coupler U17 is connected with one end of a resistor R54 and a 3 rd pin of a MOS tube Q9; a 5 th pin of the optical coupler U17 is connected with the other end of the resistor R54, a 5 th pin of the optical coupler U17 is connected with a1 st pin of the MOS tube Q9, and a 3 rd pin of the MOS tube Q9 is connected to a high-voltage ground; pin 3 of the optocoupler U17 is grounded; the 1 st pin of the optical coupler U17 is connected with the G14 pin of the FPGA chip through a resistor R57; a 2 nd pin of the MOS tube Q9 is connected with a 3 rd pin of the MOS tube Q8, a 2 nd pin of the MOS tube Q9 is connected with a 3 rd pin and a 4 th pin of the isolation Hall current sensor U14, an 8 th pin of the isolation Hall current sensor U14 is connected with a 5V high level, a 7 th pin of the isolation Hall current sensor U14 is connected to an AD conversion function interface of the DSP chip through a resistor R44, and is grounded through a resistor R46; the 6 th pin of the isolation Hall current sensor U14 is grounded through a capacitor C18, and the 5 th pin of the isolation Hall current sensor U14 is grounded; the 1 st pin and the 2 nd pin of the isolation Hall current sensor U14 are connected in parallel and are connected to the 3 rd pin of the motor socket J2, and a signal M1B + _ W is output.

In an embodiment of the present invention, the fourth H-bridge circuit includes an optical coupler U18, an optical coupler U19, a MOS transistor Q10, and a MOS transistor Q11; a 6 th pin of the optocoupler U18 is connected with a capacitor C24 and the cathode of a diode D7, the anode of the diode D7 is connected to a 15V high level through a resistor R60, the other end of the capacitor C24 is connected with a 4 th pin of the optocoupler U18, and the 4 th pin of the optocoupler U18 is connected with one end of the resistor R63 and a 3 rd pin of a MOS transistor Q10; a 5 th pin of the optical coupler U18 is connected with the other end of the resistor R63, a 5 th pin of the optical coupler U18 is connected with a1 st pin of the MOS tube Q10, and a 2 nd pin of the MOS tube Q10 is connected to a 48V high level; pin 3 of the optocoupler U18 is grounded; the 1 st pin of the optical coupler U18 is connected with the pin F14 of the FPGA chip through a resistor R61;

a 6 th pin of the optical coupler U19 is connected with one ends of a capacitor C25 and a resistor R65, the other end of the resistor R65 is connected to a high level of 15V, the other end of the capacitor C25 is connected with a 4 th pin of the optical coupler U19, and a 4 th pin of the optical coupler U19 is connected with one end of the resistor R68 and a 3 rd pin of the MOS transistor Q11; a 5 th pin of the optical coupler U19 is connected with the other end of the resistor R68, a 5 th pin of the optical coupler U19 is connected with a1 st pin of the MOS tube Q11, and a 3 rd pin of the MOS tube Q11 is connected to a high-voltage ground; pin 3 of the optocoupler U19 is grounded; the 1 st pin of the optical coupler U19 is connected with the C18 pin of the FPGA chip through a resistor R67; the 2 nd pin of the MOS transistor Q11 and the 3 rd pin of the MOS transistor Q10 are connected together and connected to the 4 th pin of the motor socket J2, and the signal M1B-GND is output.

In an embodiment of the invention, the external isolation input circuit comprises a photoelectric coupler E L357 NB U8, a1 st pin of the photoelectric coupler E L357 NB U8 is connected with one end of a resistor R28, a 2 nd pin is connected with a resistor R30 and an anode of a diode D3, a 3 rd pin is grounded, a 4 th pin is connected with one ends of the resistor R24 and the resistor R27, a cathode of the diode D3 and the other end of the resistor R28 are connected to a 24V high level, the other end of the resistor R27 is connected to a 3.3V high level, and the other end of the resistor R24 is grounded through a capacitor C11 and is simultaneously connected to a double-computation core.

In an embodiment of the invention, the external isolation output circuit comprises a photocoupler E L357 NB U12, a1 st pin of the photocoupler E L NB U12 is connected with one end of a resistor R35, a 2 nd pin is grounded, a 3 rd pin is connected with one ends of a resistor R37 and a resistor R38, the other end of the resistor R38 is connected with a GND _ HV high-voltage ground, a 4 th pin is connected with a 24V high level, the other end of the resistor R35 is grounded through a resistor R36 and is simultaneously connected to a double-calculation core, the other end of the resistor R37 is connected with a base electrode of a triode Q7, a collector electrode of the triode Q7 is connected with the high-voltage ground and a capacitor C13, a collector electrode of the triode Q7 and the other end of the capacitor C13 are connected with an anode electrode of a diode D5, and a cathode electrode of the diode D5.

In an embodiment of the invention, the back electromotive force bleeder circuit comprises an isolation driver ACP-W314U and a NAND gate logic chip SN74AHCT1G00DBV U, wherein a 3 rd pin of the isolation driver ACP-W314U is connected with one end of a resistor R and one end of the resistor R, the other end of the resistor R is connected with a1 st pin of the isolation driver ACP-W314U and is connected to a 5V high level through the resistor R, a 6 th pin of the isolation driver ACP-W314U is connected with a 15V high level, a 4 th pin of the isolation driver ACP-W314U is connected to a high voltage ground, a 5 th pin of the isolation driver ACP-W314U is connected with the resistor R and a1 st pin of an MOS tube Q, the other end of the R is connected to the high voltage ground, a 3 rd pin of the MOS tube Q is connected to the high voltage ground, a 2 nd pin of the MOS tube Q is connected with an anode of a diode D and a 2 nd pin of a high power cement resistor J, a cathode of the diode D is connected with the 1 st pin of the high power cement resistor J and is connected to a 48V high voltage ground, the other end of the NAND gate logic chip SN74 is connected to the NAND gate logic chip SN 1 st pin of the NAND gate logic chip AHCT1 SN 74U, and the NAND gate logic chip SN 5 SN of the NAND gate logic chip SN 5V CT 1H CT1G 5V CT, the NAND gate logic chip SN 5 SN of the NAND gate logic chip SN 74U is connected to the NAND gate.

In one embodiment of the invention, the isolation power supply circuit is a 15W power supply module URB4805YMD-15WR3 with an externally input direct current voltage of + VH48V, and isolation conversion from 48V to 5V is realized;

the bus voltage acquisition circuit comprises voltage isolation sensors ACP-C87U and T V2371 IDBVU, wherein the 2 nd pin of the voltage isolation sensors ACP 0-C87U is connected with a resistor R, the other end of the resistor R is connected with one end of a capacitor C, one end of the resistor R and one end of the resistor R, the other end of the resistor R is connected with a 48V high level, the other end of the resistor R is connected with the other end of the capacitor C and is connected to a high voltage ground, the 3 rd pin of the voltage isolation sensors ACP 1-C87U is connected with the 4 th pin and is connected to the high voltage ground, the 1 st pin of the voltage isolation sensors ACP 2-C87U is connected to the 5V high level, the 8 th pin of the voltage isolation sensors ACP 3-C87U is connected to the 5V high level, the 5 th pin of the voltage isolation sensors ACP 4-C87U is connected to the ground, the 7 th pin of the voltage isolation sensors ACP 5-C87U is connected with the 3 rd pin of the T6V IDU through the resistor R71, the BV 71 is connected with the other end of the resistor C71V 23U, the resistor R71 is connected with the BV 71, the other end of the resistor C71, the resistor R71 and the resistor R71 of the capacitor C235V resistor R71, the resistor R71 is connected with the other end of the capacitor C235V resistor R71, the resistor R71 and the resistor R71, the resistor R71 is connected with the other end of the resistor R71, and the resistor R71, the resistor R71.

The six-axis drive and control integrated machine has the advantages that one circuit board is adopted to drive 6 motors simultaneously, for a 6-axis stepping system, only the 6-axis drive and control integrated machine is adopted to be directly connected with the 6 stepping motors to realize connection, for the 6-axis servo system, only the 6-axis drive and control integrated machine is adopted to be directly connected with the 6 servo motors and also can drive a part of stepping motors, the other part of the drive servo motors (the total number of the drive servo motors can be 6, the drive servo motors can be realized only by modifying running software), the whole system adopts a mode of completely isolating a power ground (a high voltage ground) and a digital ground (a logic ground) to reduce the interference of a high-power partial circuit on a digital system, the adopted completely isolated power supply module adopts a URB4805YMD-15 3 power supply module of raising golden sun, a DSP chip of TI and an FPGA chip of XI L INX brand are adopted as double calculation cores, meanwhile, 6 motor drive circuits are provided, the problem of raising the voltage of bus voltage after the 6 motors run is solved, the bus voltage of the bus voltage is found by isolating, the voltage sensing circuit, the bus voltage is reasonably set to be higher than the bus voltage of a low-voltage sensing circuit, and the bus voltage sensing circuit can be reasonably loaded when the bus voltage sensing circuit is loaded, the bus voltage sensing circuit, other bus voltage sensing circuit, the bus voltage sensing circuit is reasonably set by other low-voltage sensing circuit, and the low-voltage sensing circuit, the bus voltage sensing circuit, the.

Drawings

Fig. 1 is a schematic diagram showing the assembly of the upper and lower cover plates in a separated state.

Fig. 2 is a three-dimensional view of the upper cover plate.

Fig. 3 is a three-dimensional view of the lower cover plate.

Fig. 4 is a front view and a top view of the lower cover plate.

Fig. 5 is a schematic circuit block diagram of the six-axis drive-control integrated circuit.

Fig. 6 is a schematic diagram of an isolated power supply circuit.

FIG. 7 is a schematic diagram of the communication interface circuit connection between the DSP and the FPGA.

Fig. 8 is a schematic diagram of the motor drive and current acquisition circuit connections.

Fig. 9 is a first H-bridge circuit schematic.

Fig. 10 is a second H-bridge circuit schematic.

Fig. 11 is a third H-bridge circuit schematic.

Fig. 12 is a fourth H-bridge circuit schematic.

Fig. 13 is a schematic view of a motor receptacle connection.

FIG. 14 is a schematic diagram of a bus voltage acquisition circuit.

Fig. 15 is a back emf bleeder circuit schematic.

Fig. 16 is a schematic diagram of an external isolated input circuit.

Fig. 17 is a schematic diagram of an external isolated output circuit.

Fig. 18 shows a method for determining step loss of a two-box hybrid stepping motor.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

The invention provides a six-axis drive and control integrated machine, which comprises a shell and a circuit board arranged in the shell, wherein the shell is a box body consisting of an upper cover plate 1 and a lower cover plate 2, and please refer to fig. 1; the upper cover plate 1 comprises a top plate 11, a front side plate 12 and two side plates 13 which are integrally formed, wherein the bottoms of the two side plates 13 are provided with press edges 131 which are turned outwards, the press edges 131 are provided with first fixed hole groups 31, the two side plates 13 are provided with heat dissipation holes 41 in a transverse array manner, the front side plate 12 is transversely provided with a plurality of interface hole sites 51 for installing interfaces, the rear side edge of the top plate 11 is symmetrically provided with positioning convex parts 111, and the upper cover plate 1 and the lower cover plate 2 play a role in positioning when assembled together, please refer to fig. 1 and fig. 2; the lower cover plate 2 comprises a bottom plate 21 and a rear side plate 22 which are integrally formed, a plurality of interface hole sites 51 for installing interfaces are arranged on the rear side plate 22 at equal intervals in the horizontal direction, a positioning concave part 221 is arranged on the upper edge of the rear side plate 22, and the upper cover plate 1 and the lower cover plate 2 play a role in positioning when assembled together, please refer to fig. 3; the upper surface of the bottom plate 21 is provided with a second fixed hole group 32, a third fixed hole group 33 and a fourth fixed hole group 34, and the lower surface of the bottom plate 21 is provided with radiating fins; the upper surface of the bottom plate is provided with a mounting groove, please refer to fig. 3 and fig. 4.

Referring to fig. 5, the circuit board includes two computation cores, and an isolation power circuit, six motor driving circuits, a back electromotive force bleeder circuit, an external isolation input circuit, an external isolation output circuit, and a bus voltage acquisition circuit respectively connected to the two computation cores, where each motor driving circuit module is connected to a motor for connecting and controlling a servo motor or a stepping motor.

Referring to fig. 5 to 8, in an embodiment of the present invention, the dual computation core includes a TMS320F28375S type DSP chip and an XC6S L X16-2CSG324 type FPGA chip, the DSP chip is connected to the FPGA chip through an expansion bus, the expansion bus mainly includes 13 address lines (EMA _ a0 to a12),16 data lines (EMA _ D0 to D15), a clock signal EMA _ C L K, a read signal EMA _ RD, a write signal EMA _ WR, a chip selection signal EMA _ CS2, the motor driving circuit includes a first H bridge circuit, a second H bridge circuit, a third H bridge circuit, and a fourth H bridge circuit, a pin E16 of the FPGA chip is connected to a pin S1AP _ H signal, a pin G13 of the FPGA chip is connected to a pin S1AP _ AP signal, a pin H AP of the FPGA chip is connected to a pin S1H AP H, a pin D AP of the FPGA chip is connected to a pin S72H AP, and a pin G AP is connected to the FPGA chip AP S72H AP, and the FPGA chip is connected to the FPGA driving circuit, and the FPGA chip is connected to the FPGA chip, and the FPGA chip is connected to the FPGA driving circuit, and the FPGA chip is connected to the FPGA chip, and the FPGA chip is connected to the FPGA chip, and the.

Referring to fig. 5, 8, 9, and 13, in an embodiment of the present invention, the first H-bridge circuit includes an optical coupler U1, an optical coupler U4, a MOS transistor Q2, a MOS transistor Q3, and an isolated hall current sensor U3; a 6 th pin of the optocoupler U1 is connected with a capacitor C5 and the cathode of a diode D1, the anode of the diode D1 is connected to a 15V high level through a resistor R1, the other end of the capacitor C5 is connected with a 4 th pin of the optocoupler U1, and the 4 th pin of the optocoupler U1 is connected with one end of the resistor R5 and a 3 rd pin of a MOS transistor Q2; a 5 th pin of the optical coupler U1 is connected with the other end of the resistor R5, a 5 th pin of the optical coupler U1 is connected with a1 st pin of the MOS tube Q2, and a 2 nd pin of the MOS tube Q2 is connected to a 48V high level; pin 3 of the optocoupler U1 is grounded; the 1 st pin of the optical coupler U1 is connected with the E16 pin of the FPGA chip through a resistor R3;

a method for detecting the output voltage of a Hall motor includes connecting the first pin of an optical coupler U to the output voltage of a Hall motor U + to a servo motor U + to drive the motor U + to a PWM motor U + Q to a PWM motor U + Q to a PWM motor U to a PWM motor U + Q to a PWM motor U to a PWM motor U to a PWM motor to a PWM motor to a PWM motor to drive motor to a PWM motor to a motor to drive motor to a PWM motor to a motor, a motor to drive motor, a PWM motor, a motor, connecting the PWM motor, connecting the servo.

Referring to fig. 5, 8, 10, and 13, in an embodiment of the present invention, the second H-bridge circuit includes an optical coupler U7, an optical coupler U11, a MOS transistor Q5, and a MOS transistor Q6; a 6 th pin of the optocoupler U7 is connected with a capacitor C9 and the cathode of a diode D4, the anode of the diode D4 is connected to a 15V high level through a resistor R15, the other end of the capacitor C9 is connected with a 4 th pin of the optocoupler U7, and the 4 th pin of the optocoupler U7 is connected with one end of the resistor R22 and a 3 rd pin of a MOS transistor Q5; a 5 th pin of the optical coupler U7 is connected with the other end of the resistor R22, a 5 th pin of the optical coupler U7 is connected with a1 st pin of the MOS tube Q5, and a 2 nd pin of the MOS tube Q5 is connected to a 48V high level; pin 3 of the optocoupler U7 is grounded; the 1 st pin of the optical coupler U7 is connected with the H12 pin of the FPGA chip through a resistor R26;

the method comprises connecting a 6 th pin of an optical coupler U11 with one end of a capacitor C12 and a resistor R29, connecting the other end of the resistor R29 to a 15V high level, connecting the other end of the capacitor C29 with a 4 th pin of the optical coupler U29, connecting the 4 th pin of the optical coupler U29 with one end of the resistor R29 and a 3 rd pin of the MOS tube Q29, connecting a 5 th pin of the optical coupler U29 with the other end of the resistor R29, connecting a 5 th pin of the optical coupler U29 with a1 st pin of the MOS tube Q29, connecting a 3 rd pin of the MOS tube Q29 to a high voltage ground, connecting a 3 rd pin of the optical coupler U29 to the D29 of the FPGA 29, connecting a 2 nd pin of the MOS tube Q29 to the 3 rd pin of the FPGA Q29, connecting the output of the FPGA Q29 to the 2 nd pin of the FPGA Q29, connecting the output 29 to the output 29 of the FPGA Q29, connecting the FPGA Q29 to the output 29 of the FPGA 29, connecting a high voltage power supply level of the FPGA Q29, connecting a driving circuit, connecting the FPGA Q29 to the FPGA 29, connecting a high voltage driving circuit 29 to the FPGA 29, connecting a driving circuit 29 to a driving circuit 29, connecting the FPGA to a high voltage level of the FPGA 29, and a driving circuit 29 to a driving circuit, and a driving circuit 29 to a driving circuit.

Referring to fig. 5, 8, 11, and 13, in an embodiment of the present invention, the third H-bridge circuit includes an optical coupler U13, an optical coupler U17, a MOS transistor Q8, a MOS transistor Q9, and an isolated hall current sensor U14; a 6 th pin of the optocoupler U13 is connected with a capacitor C14 and the cathode of a diode D6, the anode of the diode D6 is connected to a 15V high level through a resistor R39, the other end of the capacitor C14 is connected with a 4 th pin of the optocoupler U13, and the 4 th pin of the optocoupler U13 is connected with one end of the resistor R42 and a 3 rd pin of a MOS transistor Q8; a 5 th pin of the optical coupler U13 is connected with the other end of the resistor R42, a 5 th pin of the optical coupler U13 is connected with a1 st pin of the MOS tube Q8, and a 2 nd pin of the MOS tube Q8 is connected to a 48V high level; pin 3 of the optocoupler U13 is grounded; the 1 st pin of the optical coupler U13 is connected with the D17 pin of the FPGA chip through a resistor R41;

a method for detecting the output voltage of a high-power motor U-Q by a FPGA driver includes such steps as connecting the 6 th pin of an optical coupler U to the 6 th pin of a capacitor R, connecting the other end of the resistor R to 15V high level, connecting the other end of a capacitor C to the 4 th pin of an optical coupler U, connecting the 4 th pin of the optical coupler U to the 3 rd pin of a MOS transistor Q, connecting the 4 th pin of the optical coupler U to high-voltage ground, connecting the 3 rd pin of the optical coupler U to ground, connecting the 1 st pin of the optical coupler U to the G pin of the FPGA chip via the resistor R, connecting the 2 nd pin of the MOS transistor Q to the 3 rd pin of the MOS transistor Q, connecting the 2 nd pin of the isolation Hall current sensor U to the 3 rd pin and the 4 th pin of the isolation Hall current sensor U, connecting the 8 th pin of the isolation current sensor U to 5V high level, connecting the 7 th pin of the isolation Hall current sensor U to the AD conversion interface of the DSP chip via the resistor R, connecting the U to ground, connecting the 6 th pin of the isolation resistor U to the FPGA sensor U, connecting the 5 th pin of the FPGA U to the FPGA driver U + the FPGA driver U, connecting the FPGA U to the output of the FPGA U, connecting the FPGA to the FPGA U, connecting the FPGA U to the FPGA U, and the output of the FPGA U, connecting the FPGA to the FPGA U, connecting the FPGA U, and the FPGA to the FPGA U, and the FPGA, connecting the FPGA to the FPGA, and the output of the FPGA, connecting the FPGA to the FPGA, and the FPGA, detecting circuit, detecting the output of the FPGA, detecting circuit, detecting the output of the FPGA, detecting the high-phase of the FPGA, detecting circuit, detecting the high-phase, detecting the output of the high-phase motor, detecting circuit, detecting.

In one embodiment of the invention, for the stepping motor, as the common stepping motor in the market adopts a 2-phase structure, the current of 2 phases, namely an A + phase and a B + phase of the stepping motor, is completely measured; for the servo motor, there are typically U, V, W phases; the current of the other phase V can be calculated by measuring U, W the current of two phases;

referring to fig. 14, in an embodiment of the present invention, a six-axis drive-control integrated circuit is connected to an upper computer and is configured to perform step loss judgment on a stepping motor, and two-phase sine and cosine current tracking open-loop control is adopted, two-phase voltages and currents are used as input signals, an electric angle position of a rotor of the two-phase stepping motor is observed through a non-linear observer, then a rotor speed estimation value is obtained by differentiating the electric angle position of the rotor, a relative error between the rotor speed estimation value and a given speed signal is calculated, and if the relative error exceeds a set threshold, step loss of the two-phase stepping motor in open-loop control is judged, and motor; the method comprises the following specific steps:

the mathematical model of the AB phase of the two-phase hybrid stepping motor is

Wherein R, L are resistance and inductance of step motor i_a、i_b、u_a、u_bIs the AB phase current voltage; p is a differential operator, theta is the electrical angle of the rotor of the stepping motor, omega_eFor rotor electrical angle, psi of step motor_fIs a stepping motor magnetic linkage.

Assume that the variable is

Corresponding observed variable is

According to the two-phase current amplitude i of the motor given by the upper computer_maxDetermining a given signal of the open-loop control two-phase sine and cosine current of the stepping motor according to the running speed omega required by the motor;

then, the following steps are performed:

s1, setting an amplitude according to the operation speed ω and the operation current of the stepping motor, where θ (k) ═ ω (k) is the rotor position of the stepping motor; determining a given current signal i for the a-axis_a(k)＝i_maxsin (theta (k)) and b-axis given current signal i_b(k)＝i_maxcos (theta (k)) and current loop control period T,Current controller parameters, initializing rotor positionObserved variableObserved variable

S2, substituting the two-phase current collection value and the voltage output value

Calculating the derivative of the variable y

S3, derivative of variable yObserved variableab axis current i_ab(k) Substitution into

ComputingWherein gamma > 0 is the convergence coefficient of the observer;

s4, according toComputingSubstituted typeIs calculated to obtain

S5, passingAnd determining the rotor position estimation value by quadrant-sum discrimination

S6, calculating the motor speed estimated value according to the difference of the rotor position estimated valuesSubstitution intoWhen the value exceeds a preset fixed threshold value, the control period stepping motor is out of step; and estimating the position of each motor rotor in real time, solving a motor speed estimation value according to the difference of the position estimation values in a control period, and judging that the stepping motor is out of step when the speed exceeds a threshold value compared with a given speed.

Referring to fig. 5, 8, 12 and 13, in an embodiment of the present invention, the fourth H-bridge circuit includes an optical coupler U18, an optical coupler U19, a MOS transistor Q10 and a MOS transistor Q11; a 6 th pin of the optocoupler U18 is connected with a capacitor C24 and the cathode of a diode D7, the anode of the diode D7 is connected to a 15V high level through a resistor R60, the other end of the capacitor C24 is connected with a 4 th pin of the optocoupler U18, and the 4 th pin of the optocoupler U18 is connected with one end of the resistor R63 and a 3 rd pin of a MOS transistor Q10; a 5 th pin of the optical coupler U18 is connected with the other end of the resistor R63, a 5 th pin of the optical coupler U18 is connected with a1 st pin of the MOS tube Q10, and a 2 nd pin of the MOS tube Q10 is connected to a 48V high level; pin 3 of the optocoupler U18 is grounded; the 1 st pin of the optical coupler U18 is connected with the pin F14 of the FPGA chip through a resistor R61;

the method comprises the steps of providing a FPGA chip, a servo motor, a first pin 6 of an optical coupler U, a second pin 6 of the optical coupler U, a third pin of the optical coupler U, a fourth pin of the optical coupler U, a fifth pin of the optical coupler U, a sixth pin of the optical coupler U, a fifth pin of the FPGA chip, a sixth pin of the FPGA chip, a seventh pin of the FPGA chip, a sixth pin of the FPGA chip, a sixth pin of the FPGA chip, a sixth pin of the FPGA chip, a pin of the FPGA, a sixth pin of the FPGA chip, a sixth pin of the FPGA, a sixth pin of the FPGA.

Referring to fig. 5 to 8 and 16, IN an embodiment of the present invention, the external isolation input circuit includes a photocoupler E L357 NB U8, a photocoupler E L357 NB U8 has a1 st pin connected to one end of a resistor R28, a 2 nd pin connected to a resistor R30 and an anode of a diode D3, a 3 rd pin grounded, a 4 th pin connected to one end of a resistor R24 and a resistor R27, a cathode of a diode D3 and the other end of a resistor R28 are connected to a 24V high level, the other end of a resistor R27 is connected to a 3.3V high level, the other end of a resistor R24 is grounded via a capacitor C11 and simultaneously connected to a dual-computing core, the circuit is an optical coupling isolated external input interface circuit, if an external signal SIG1_ IN is a low level, the U8.4 optical coupling output pin U8.4 outputs a low level to an IO port of the DSP, if the external signal SIG1_ IN is a high level (24V), the U8.4 optical coupling output pin is connected to an IO port of the DSP, and the external input circuit can be implemented by other input signal input port of the DSP integrated circuit similar to the DSP 3923.

Referring to fig. 5-8 and 17, in an embodiment of the invention, the external isolation output circuit includes a photocoupler E L357 NB U12, a photocoupler E L357 NB U12 with a1 st pin connected to one end of a resistor R35, a 2 nd pin grounded, a 3 rd pin connected to one end of a resistor R37 and a resistor R38, a resistor R38 with the other end connected to GND HV high voltage ground, a 4 th pin connected to 24V high level, a resistor R35 with the other end connected to ground via a resistor R36 and to the dual computational core, a resistor R37 with the other end connected to the base of a transistor Q7, a collector of the transistor Q7, an emitter of the transistor Q7 connected to high voltage ground and a capacitor C7, a collector of the transistor Q7 connected to the other end of the diode D7 with the negative electrode of the diode D7 connected to 24V high level, an IO port of the DSP output signal OUT 7, the transistor Q7 is switched to the high level when the DSP output signal OUT is in an internal pull-on state, the transistor Q7 is connected to the DSP output circuit capable of outputting a low level signal output signal OUT, and the signal output of driving the transistor Q7 is not connected to the transistor Q7, and the internal isolation circuit 7.

According to the present invention, as shown in FIGS. 5-8 and 15, the back electromotive force discharge circuit comprises an isolation driver ACP L-W314U 5 and a NAND gate logic chip SN74AHCT1G00DBV U10, wherein the 3 rd pin connection of the isolation driver ACP L-W314U 5 is connected to one end of a resistor R16 and one end of a resistor R20, the other end of the resistor R16 is connected to the 1 st pin of the isolation driver ACP 16-W314U 16 and connected to a 5V high level through a resistor R16, the 6 th pin of the isolation driver ACP 16-W314U 16 is connected to a 15V high level, the 4 th pin of the isolation driver ACP 16-W314U 16 is connected to a high voltage ground, the 5 th pin of the isolation driver ACP 16-W16 is connected to the 1 st pin of the resistor R16 and the Q16 and the 1 st pin of the resistor R16 and the NAND gate Q16 are connected to a high power transistor V1N 16, the power output of the high power transistor V N16 is connected to a high power transistor V power bus V70V 72, the power bus 16, the power bus is connected to a high power bus 16, the power bus V bus is connected to a high power bus V72, the power bus is connected to the power bus 72, the power bus of the power bus V bus 72, the power bus is connected to the power bus 72, the power bus is connected to the power bus of the power bus 72, the power bus of the power bus 72, the power bus is connected to the power bus 72, the power bus is connected to the power bus of the power bus, the power bus is connected to the power bus, the power bus 72, the power bus of the power bus is connected to the power bus, the power bus is connected to the power bus, the power bus of the power bus is connected to the power bus of the power bus 72, the power bus is connected to the power bus, the power bus of the power bus 72, the power bus of the power bus is connected to the power bus, the power bus of the power bus 72, the power bus of the power bus 72, the power bus of the power bus is connected.

Referring to fig. 5 to 8 and 14, in an embodiment of the invention, the isolation power circuit is a 15W power module URB4805YMD-15WR3 with an externally input dc voltage of + VH48V, so as to realize an isolation conversion from 48V to 5V; the isolation voltage is 1500VDC, and the wide input voltage range reaches 18-75V; the input high voltage ground (GND _ HV) and the output digital ground GND of the module are completely isolated;

the bus voltage acquisition circuit comprises a voltage isolation sensor ACP-C87U and a T V2371 IDBVU, wherein the 2 nd pin of the voltage isolation sensor ACP 0-C87U is connected with a resistor R, the other end of the resistor R is connected with one end of a capacitor C, one end of the resistor R and one end of the resistor R, the other end of the resistor R is connected with one end of a resistor R, the other end of the resistor R is connected with the 48V high level, the other end of the resistor R is connected with the other end of a capacitor C and is connected to a high-voltage ground, the 3 rd pin of the voltage isolation sensor ACP 1-C87U is connected with the 4 th pin and is connected to the high-voltage ground, the 1 st pin of the voltage isolation sensor ACP 2-C87U is connected to the 5V high level, the 8 th pin of the voltage isolation sensor ACP 3-C87U is connected to the 5V high level, the 5 th pin of the voltage isolation sensor ACP 4-C87U is grounded, the 7 th pin of the voltage isolation sensor ACP 5-C87U is connected with the 3 rd pin of the T6V 23U 71, the DSP ACP 71V AD U, the voltage acquisition circuit is connected with the voltage acquisition circuit through the BV, the voltage acquisition circuit, the voltage of the BV 5V signal acquisition circuit, the DSP 5V signal acquisition circuit is connected with the voltage acquisition circuit after the BV, the voltage acquisition circuit, the voltage of the DSP 5V signal acquisition circuit, the DSP 71-C, the DSP 71 is connected with the DSP 5V-C, the DSP 71 and the DSP 71, the DSP 71 is connected with the DSP 71, the DSP 71 is connected with the DSP 71 and the DSP 71, the DSP 71 is connected with the DSP 71, the DSP 71 and the DSP 71, the DSP 71 is connected with the DSP 71, the DSP 71 is connected with the DSP 71 and the DSP.

The above description is only a preferred embodiment of the present invention, and should not be construed as limiting the present invention, and all equivalent variations and modifications made in the claims of the present invention should be covered by the present invention.