阅读说明：本技术 二倍频装置及方法 (Frequency doubling device and method ) 是由 李安明 林嘉亮 涂祐豪 陈育祥 于 2019-07-17 设计创作，主要内容包括：一种二倍频装置及方法,所述二倍频装置包含：二倍频产生电路及工作周期调整电路。二倍频产生电路包含：多工器、可变延迟电路及除二电路。多工器根据选择信号选择互为反相的第一及第二时钟信号其中之一输出,以产生二倍频时钟信号。可变延迟电路将二倍频时钟信号延迟预设时间。除二电路对二倍频时钟信号进行除频产生选择信号。工作周期调整电路包含：平均电压产生电路及比较电路。平均电压产生电路产生二倍频时钟信号的平均电压值。比较电路根据平均电压值以及参考电压的比较结果产生控制信号,以控制延迟时间,进一步控制二倍频时钟信号的工作周期。(A frequency doubling device and method, the frequency doubling device comprising: a frequency doubling generation circuit and a duty cycle adjusting circuit. The frequency doubling generation circuit comprises: multiplexer, variable delay circuit and divide by two circuit. The multiplexer selects one of the first and second clock signals with opposite phases to output according to the selection signal to generate a frequency-doubled clock signal. The variable delay circuit delays the double frequency clock signal by a preset time. The two-division circuit divides the frequency of the two-frequency-doubling clock signal to generate a selection signal. The duty cycle adjusting circuit includes: an average voltage generating circuit and a comparing circuit. The average voltage generating circuit generates an average voltage value of the frequency-doubled clock signal. The comparison circuit generates a control signal according to the comparison result of the average voltage value and the reference voltage to control the delay time and further control the working period of the frequency doubling clock signal.)

1. A frequency doubling device, comprising:

a frequency doubling generation circuit, comprising:

a multiplexer configured to receive and select one of a first clock signal and a second clock signal, which are opposite in phase, to output according to a selection signal, so as to generate a frequency-doubled clock signal having a frequency twice that of the first clock signal and the second clock signal;

a variable delay circuit configured to delay the double frequency clock signal by a predetermined time; and

a divide-by-two circuit configured to divide the delayed double frequency clock signal to generate the selection signal; and

a duty cycle adjustment circuit, comprising:

an average voltage generating circuit configured to receive the double-frequency clock signal to generate an average voltage value of the double-frequency clock signal; and

a comparison circuit configured to receive the average voltage value and a reference voltage, and generate a control signal according to a comparison result between the average voltage value and the reference voltage, so as to control a delay time of the variable delay circuit and further control a duty cycle of the double frequency clock signal.

2. The frequency doubling device of claim 1 wherein the divide-by-two circuit comprises a data flip-flop having a negative feedback structure.

3. The frequency doubling device according to claim 1, wherein a first positive edge, a second positive edge, a third positive edge and a fourth positive edge of the frequency doubling clock signal are generated by the multiplexer selecting a first clock signal positive edge of the first clock signal, a first clock signal positive edge of the second clock signal, a second clock signal positive edge of the first clock signal after the first clock signal positive edge and a second clock signal positive edge of the second clock signal after the second clock signal positive edge, respectively.

4. The frequency doubling device as claimed in claim 1, wherein the average voltage generating circuit comprises:

a resistor including a first terminal for receiving the double frequency clock signal and a second terminal for generating the average voltage value; and

and the capacitor is electrically coupled between the second end of the resistor and a ground potential.

5. The frequency doubling device according to claim 1, wherein the control signal is a voltage signal, and the voltage signal is further provided to the multiplexer and the divide-by-two circuit, so that the multiplexer and the divide-by-two circuit operate according to the voltage signal.

6. The frequency doubling device as claimed in claim 1, wherein the frequency doubling clock signal has a high voltage level, and a relative relationship between the magnitude of the reference voltage and the high voltage level determines the duty cycle of the frequency doubling clock signal.

7. The frequency doubling device as claimed in claim 6, wherein when the duty cycle of the first and second clock signals is 50% and the reference voltage is half of the high voltage level, the control signal makes the delay time of the variable delay circuit be a half period of the frequency doubling clock signal, so that the duty cycle is 50%.

8. A method of frequency doubling, comprising:

a multiplexer of a frequency doubling generation circuit receives and selects one of a first clock signal and a second clock signal which are opposite in phase according to a selection signal to output so as to generate a frequency doubling clock signal with the frequency being twice of the first clock signal and the second clock signal;

a variable delay circuit of the double frequency generation circuit delays the double frequency clock signal for a preset time;

dividing the delayed double-frequency clock signal by a dividing circuit of the double-frequency generating circuit to generate the selection signal;

enabling an average voltage generating circuit of a working period adjusting circuit to receive the double-frequency clock signal so as to generate an average voltage value of the double-frequency clock signal; and

a comparison circuit of the duty cycle adjusting circuit receives the average voltage value and a reference voltage to generate a control signal according to a comparison result of the average voltage value and the reference voltage to control a delay time of the variable delay circuit and further control a duty cycle of the double-frequency clock signal.

9. The method according to claim 8, wherein a first positive edge, a second positive edge, a third positive edge and a fourth positive edge of the double frequency clock signal are generated by the multiplexer selecting a first clock signal positive edge of the first clock signal, a first clock signal positive edge of the second clock signal, a second clock signal positive edge of the first clock signal after the first clock signal positive edge and a second clock signal positive edge of the second clock signal after the second clock signal positive edge.

10. A frequency doubling device, comprising:

a frequency doubling generation circuit, comprising:

a multiplexer configured to receive and select one of a first clock signal and a second clock signal, which are opposite in phase, to output according to a selection signal, so as to generate a frequency-doubled clock signal having a frequency twice that of the first clock signal and the second clock signal;

a variable delay circuit configured to delay the double frequency clock signal by a predetermined time; and

a divide-by-two circuit configured to divide the delayed double frequency clock signal to generate the selection signal; and

a duty cycle adjustment circuit, comprising:

a first average voltage generating circuit configured to receive the double-frequency clock signal to generate a first average voltage value of the double-frequency clock signal;

a second average voltage generating circuit configured to receive the inverted double frequency clock signal and generate a second average voltage value of the inverted double frequency clock signal as a reference voltage; and

a comparison circuit configured to receive the average voltage value and the reference voltage, and generate a control signal according to a comparison result between the average voltage value and the reference voltage, so as to control a delay time of the variable delay circuit and further control a duty cycle of the double frequency clock signal.

Technical Field

The present invention relates to a frequency doubling technology, and more particularly, to a frequency doubling apparatus and method.

Background

Generally, a frequency doubler can be implemented by a phase lock loop (P LL), which can accurately generate a doubled clock signal, but the instantaneous time may slightly differ from the ideal time, which is usually called jitter (jitter).

Therefore, how to design a new frequency doubling device and method to solve the above-mentioned drawbacks is an urgent problem to be solved in the art.

Disclosure of Invention

Drawings

In order to make the aforementioned and other objects, features, and advantages of the invention, as well as others which will become apparent, reference is made to the following description of the preferred embodiments of the invention in which:

FIG. 1 is a block diagram of a frequency doubler according to an embodiment of the present invention;

FIG. 2 is a waveform diagram of signals in a frequency doubler according to an embodiment of the present invention;

FIG. 3 is a block diagram of a frequency doubler according to an embodiment of the present invention; and

fig. 4 is a flowchart of a frequency doubling method according to an embodiment of the invention.

Description of the symbols

1: frequency doubling device 100: double frequency generating circuit

102: the multiplexer 104: variable delay circuit

106: the divide-by-two circuit 120: duty cycle adjusting circuit

122: average voltage generation circuit 124: comparison circuit

C. C', a capacitor C L K1, a first clock signal

C L K2 second clock signal C L K3 select signal

CT L, control signal DFC L K, double frequency clock signal

D L C L K delayed frequency-doubled clock signal GND ground potential

Number R, R': resistance (RC)

IDFC L K, inverse frequency-doubled clock signal Vave, average voltage value

T0-T6: time interval 3: frequency doubling device

Vref: reference voltage 302: inverter with a capacitor having a capacitor element

300: the reference voltage generation circuit 400: frequency doubling method

304: voltage generating circuit

401-405: step (ii) of

Detailed Description

Referring to fig. 1, fig. 1 is a block diagram of a frequency doubling device 1 according to an embodiment of the present invention, the frequency doubling device 1 is configured to generate a frequency doubled clock signal DFC L K with twice the frequency according to received clock signals, such as a first clock signal C L K1 and a second clock signal C L K2, the frequency doubling device 1 includes a frequency doubling generation circuit 100 and a duty cycle adjustment circuit 120.

Please refer to fig. 2. Fig. 2 is a waveform diagram of signals in the frequency doubler 1 according to an embodiment of the present invention. The structure and operation of frequency doubling device 1 will be described in more detail below with reference to fig. 1 and 2.

The frequency doubling generation circuit 100 comprises: a multiplexer 102, a variable delay circuit 104, and a divide-by-two circuit 106.

The multiplexer 102 is configured to receive and select one of the first clock signal C L K1 and the second clock signal C L K2 according to the selection signal C L K3 to generate a double-frequency clock signal DFC L K having a frequency twice as high as the first clock signal C L K and the second clock signal C L K, wherein the first clock signal C L K1 and the second clock signal C L K2 are opposite phases to each other, and in fig. 2, the first clock signal C L K1 is shown by a solid line, and the second clock signal C L K2 is shown by a dashed line.

The variable delay circuit 104 is configured to delay the dual-clock signal DFC L K by a predetermined time to generate a delayed dual-clock signal D L C L K. in one embodiment, the period of the first clock signal C L K1 and the second clock signal C L K2 is T, the period of the dual-clock signal DFC L K is T/2, and the predetermined time is T/4. therefore, the period of the delayed dual-clock signal D L C L K is still T/2, but has a phase difference of T/4 compared to the dual-clock signal DFC L K.

The divide-by-two circuit 106, in one embodiment, includes a data flip-flop (data flip-flop) having a negative feedback structure, which is well known in the art and will not be described herein, the data flip-flop and the negative feedback structure thereof are configured to perform a divide-by-two function, and the divide-by-two circuit 106 is configured to divide the delayed double-frequency clock signal D L C L K to generate the select signal C L K3., so that the period of the select signal C L K3 is T relative to the delayed double-frequency clock signal D L C L K.

Therefore, in the time interval T0 in fig. 2, since the selection signal C L K3 is low, the multiplexer 102 in fig. 1 selects the first clock signal C L K1 for output, at this time, the double-frequency clock signal DFC L K is equal to the positive edge of the first clock signal C L K1 at the positive edge of the time interval T0, and the double-frequency clock signal DFC L K is drawn by the solid line corresponding to the first clock signal C L K1 at the time interval T0.

In the time intervals T1 and T2 of fig. 2, since the selection signal C L K3 is high, the multiplexer 102 of fig. 1 selects the second clock signal C L K2 to output, at this time, the double frequency clock signal DFC L K is equivalent to the positive edge of the second clock signal C L K2 at the positive edges of the time intervals T1 and T2, and is the signal transition caused by the switching of the multiplexer 102 at the negative edges of the time intervals T1 and T2, and the double frequency clock signal DFC L K is plotted by solid lines corresponding to the second clock signal C L K2 at the time intervals T1 and T2.

Similarly, in the time intervals T3 and T4 in fig. 2, since the selection signal C L K3 is low, the multiplexer 102 in fig. 1 selects the first clock signal C L K1 for output, at this time, the dual clock signal DFC L K is the signal transition caused by the switching of the multiplexer 102 at the positive edge of the time intervals T3 and T4, corresponding to the positive edge of the first clock signal C L K1, and at the negative edge of the time intervals T3 and T4, and, at the time intervals T3 and T4, the dual clock signal DFC L K is drawn by the solid line corresponding to the first clock signal C L K1.

In the time intervals T5 and T6 shown in fig. 2, the selection signal C L K3 is high, so that the multiplexer 102 shown in fig. 1 selects the second clock signal C L K2 to output, at this time, the double frequency clock signal DFC L K corresponds to the signal transition caused by the switching of the multiplexer 102 at the positive edge of the time intervals T5 and T6, and corresponds to the signal transition caused by the positive edge of the second clock signal C L K2 at the negative edge of the time intervals T5 and T6, and the double frequency clock signal DFC L K is drawn by the solid line corresponding to the second clock signal C L K2 at the time intervals T5 and T6.

Therefore, through the above mechanism, the frequency doubling generation circuit 100 can generate the frequency doubling clock signal DFC L K with twice the frequency according to the first clock signal C L K1 and the second clock signal C L K2.

The duty cycle adjusting circuit 120 includes: an average voltage generating circuit 122 and a comparing circuit 124.

The average voltage generating circuit 122 is configured to receive the frequency-doubled clock signal DFC L K to generate an average voltage value Vave of the frequency-doubled clock signal DFC L K.

In one embodiment, the average voltage generating circuit 122 includes a resistor R and a capacitor C, the resistor R includes a first terminal for receiving the frequency-doubled clock signal DFC L K and a second terminal for generating the average voltage value Vave, the capacitor C is electrically coupled between the second terminal of the resistor R and the ground potential GND, the resistor R and the capacitor C jointly function as an integrating circuit to generate the average voltage value Vave of the frequency-doubled clock signal DFC L K.

The comparison circuit 124 is configured to receive the average voltage value Vave and the reference voltage Vref, and generate the control signal CT L according to a comparison result between the average voltage value Vave and the reference voltage Vref, so as to control a delay time of the variable delay circuit 104, and further control a duty cycle of the frequency-doubled clock signal DFC L K.

In one embodiment, the reference voltage Vref may be set to VDD/2, and the positive input terminal of the comparison circuit 124 is configured to receive the reference voltage Vref, and the negative input terminal is configured to receive the average voltage value Vave, so that when the average voltage value Vave is smaller than the reference voltage Vref, it indicates that the duty cycle of the double frequency clock signal DFC L K is smaller than 50%.

In contrast, when the average voltage value Vave is greater than the reference voltage Vref, it indicates that the duty cycle of the frequency-doubled clock signal DFC L K is greater than 50%, the comparator circuit 124 may decrease the delay time of the variable delay circuit 104 by generating the control signal CT L, so that the delay time approaches T/4 and the duty cycle approaches 50%.

Therefore, the setting of the duty cycle adjusting circuit 120 can provide the technical effect of stabilizing the duty cycle of the frequency-doubled clock signal DFC L K.

Further, the duty cycle adjusting circuit 120 can adjust the duty cycle of the double frequency clock signal DFC L K by the generation of the control signal CT L when the reference voltage Vref is changed, for example, when the reference voltage Vref is set to VDD/4, the delay time can be set to about T/8 and the duty cycle of the double frequency clock signal DFC L K is controlled to 25%, and when the reference voltage Vref is set to (3/4) VDD, the delay time can be set to about (3/8) T and the duty cycle of the double frequency clock signal DFC L K is controlled to 75%.

Therefore, the high level of the frequency-doubled clock signal DFC L K is relative to the reference voltage Vref and VDD, which determines the duty cycle of the frequency-doubled clock signal DFC L K.

Therefore, the frequency doubling apparatus 1 of the present invention can generate the frequency doubled clock signal DFC L K through the simple circuit structure of the frequency doubling generating circuit 100, and the duty cycle adjusting circuit 120 provides stable and precise control and adjustment for the duty cycle of the frequency doubled clock signal DFC L K.

In one embodiment, if the external power module provides power to the components of the double frequency generation circuit 100 during operation, the components are susceptible to high frequency jitter and cannot be adjusted by the duty cycle adjustment circuit 120 in time, in one embodiment, the comparison circuit 124 may be implemented by a low dropout regulator (L DO) to generate the control signal CT L in the form of a voltage signal, and further provide the control signal CT L to the multiplexer 102 and the divide-by-two circuit 104, so that the multiplexer 102 and the divide-by-two circuit 104 operate according to the control signal CT L.

Under such a design, the frequency doubling apparatus 1 can provide a voltage stabilizing mechanism for the frequency doubling generating circuit 100 without increasing the area and cost of an additional voltage stabilizing circuit, so that the generated frequency doubling clock signal DFC L K is more stable and accurate.

Further, in an embodiment, the frequency doubling device 1 of the present invention may achieve a power-of-two multiplied clock signal (e.g., 4 times, 8 times, 16 times, etc.) by outputting the frequency doubled clock signal DFC L K to one or more frequency doubling circuits (such as, but not limited to, the frequency doubling device 1 itself or other possible frequency doubling circuits) connected in series.

Please refer to fig. 3. Fig. 3 is a block diagram of a frequency doubler 3 according to an embodiment of the present invention. Similar to the frequency doubler 1 shown in fig. 1, the frequency doubler 3 comprises: the frequency doubling generation circuit 100 and the duty cycle adjustment circuit 120 are not described in detail. The difference from the frequency doubler 1 shown in fig. 1 is that the frequency doubler 3 further comprises a reference voltage generating circuit 300.

The reference voltage generating circuit 300 comprises an inverter 302 and a voltage generating circuit 304, wherein the inverter 302 is configured to receive the frequency-doubled clock signal DFC L K to generate an inverted frequency-doubled clock signal IDFC L K the voltage generating circuit 304 is similar in structure to the average voltage generating circuit 122, comprises a resistor R 'and a capacitor C', and is configured to receive the inverted frequency-doubled clock signal IDFC L K to generate an average voltage value of the inverted frequency-doubled clock signal IDFC L K, and is fed to the comparing circuit 124 as the reference voltage Vref.

Under such a configuration, since the phases of the double frequency clock signal DFC L K and the inverted double frequency clock signal IDFC L K are opposite to each other, the average voltage result of the inverted double frequency clock signal IDFC L K can be used as the reference voltage Vref, so as to achieve the output result of automatically adjusting the duty cycle of the double frequency clock signal DFC L K to 50%, and no additional reference voltage manufacturing circuit is required.

Please refer to fig. 4. Fig. 4 is a flow chart of a frequency doubling method 400 according to an embodiment of the invention. The frequency doubling method 400 can be applied to the frequency doubling apparatus 1 of fig. 1.

The frequency doubling method 400 comprises the following steps (it should be understood that the steps mentioned in the present embodiment, except for the sequence specifically mentioned, can be performed simultaneously or partially simultaneously according to the actual requirement.

In step 401, the multiplexer 102 of the frequency doubling generating circuit 100 receives the selection signal C L K3 and selects one of the first clock signal C L K1 and the second clock signal C L K2 with opposite phases to output, so as to generate the frequency doubling clock signal DFC L K with twice the frequency of the first clock signal C L K1 and the second clock signal C L K2.

In step 402, the variable delay circuit 104 of the double frequency generation circuit 100 delays the double frequency clock signal DFC L K by a predetermined time.

In step 403, the divide-by-two circuit 106 of the frequency doubling generating circuit 100 divides the delayed frequency doubled clock signal D L C L K to generate the selection signal C L K3.

In step 404, the average voltage generating circuit 122 of the duty cycle adjusting circuit 120 receives the frequency-doubled clock signal DFC L K to generate an average voltage value Vave of the frequency-doubled clock signal DFC L K.

In step 405, the comparison circuit 124 of the duty cycle adjusting circuit 120 receives the average voltage value Vave and the reference voltage Vref, and generates the control signal CT L according to the comparison result between the average voltage value Vave and the reference voltage Vref, so as to control the delay time of the variable delay circuit 104 and further control the duty cycle of the frequency-doubled clock signal DFC L K.

Although the foregoing embodiments have been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.