阅读说明：本技术 多路共用的时钟占空比校正电路 (Multi-path shared clock duty ratio correction circuit ) 是由 刘雄 于 2020-05-22 设计创作，主要内容包括：本发明涉及时钟占空比校准领域,公开了一种多路共用的时钟占空比校正电路,包括多个主交流耦合缓冲器、一个多路选择器、一个共享电阻串和一个复制偏置模块,每个所述主交流耦合缓冲器分别通过一个偏置电阻与所述所述多路选择器连接,所述多路选择器通过所述共享电阻串与所述复制偏置模块连接。实施本发明的多路共用的时钟占空比校正电路,具有以下有益效果：能节省面积、占空比校准精度较高、噪声低。(The invention relates to the field of clock duty ratio calibration, and discloses a multi-path shared clock duty ratio correction circuit which comprises a plurality of main alternating current coupling buffers, a multi-path selector, a shared resistor string and a copy bias module, wherein each main alternating current coupling buffer is respectively connected with the multi-path selector through a bias resistor, and the multi-path selector is connected with the copy bias module through the shared resistor string. The multi-path shared clock duty ratio correction circuit has the following beneficial effects: the area can be saved, the calibration precision of the duty ratio is higher, and the noise is low.)

1. The multi-path shared clock duty cycle correction circuit is characterized by comprising a plurality of main alternating current coupling buffers, a multiplexer, a shared resistor string and a copy bias module, wherein each main alternating current coupling buffer is respectively connected with the multiplexer through a bias resistor, and the multiplexer is connected with the copy bias module through the shared resistor string.

2. The multi-channel shared clock duty cycle correction circuit according to claim 1, wherein the replica bias module comprises a PMOS transistor and an NMOS transistor, and a gate of the PMOS transistor, a source of the PMOS transistor, a gate of the NMOS transistor, and a source of the NMOS transistor are all connected to the shared resistor string.

3. The multi-channel shared clock duty cycle correction circuit according to claim 2, wherein the shared resistor string includes an upper resistor string and a lower resistor string, and a node at which the upper resistor string is connected in series with the lower resistor string is connected to the gates of the PMOS transistor and the NMOS transistor.

4. The multi-way shared clock duty cycle correction circuit according to claim 3, wherein each of said main ac-coupled buffers comprises a capacitor and an inverter, one end of said capacitor is connected to an input terminal of a clock, and the other end of said capacitor is connected to an output terminal of said clock through said inverter.

5. The multi-way shared clock duty cycle correction circuit according to claim 4, wherein the phase inverter includes a P-channel type main ac buffer transistor and an N-channel type main ac buffer transistor, a gate of the P-channel type main ac buffer transistor and a gate of the N-channel type main ac buffer transistor are both connected to the other end of the capacitor, and a source of the P-channel type main ac buffer transistor and a source of the N-channel type main ac buffer transistor are both connected to the output terminal of the clock.

6. The multi-way shared clock duty cycle correction circuit according to claim 5, wherein the other end of the capacitor is connected to two different input terminals of the multiplexer through the bias resistor.

Technical Field

The invention relates to the field of clock duty ratio calibration, in particular to a multi-path shared clock duty ratio correction circuit.

Background

The duty ratio correction requires precision, but the area is large. When there are multiple clocks to correct the duty cycle, such as clock0, clock90, clock180, and clk270, the occupied area is large. Fig. 1 is a schematic diagram of a conventional duty cycle correction (clock Duty Cycle Correction (DCC)) scheme, specifically fig. 1 based on a variable PMOS/NMOS width, in which method the widths of PMOS (MP1) and NMOS (MN1) in an inverter can be programmed and the duty cycle can be changed by adjusting the strengths of PMOS and NMOS when the inverter is used in a clock chain. Assuming that PMOS has 10 widths and NMOS has 10 widths, when PMOS is opened 5 widths and NMOS is opened 5 widths, the PMOS and NMOS strengths are matched. In this case the output duty cycle will be exactly 50%, assuming an ideal input. When a duty cycle in excess of 50% is required, for example 55%, the PMOS is programmed to be greater than 5 widths. The NMOS can be held at 5 or programmed below 5 widths. Since PMOS is stronger than NMOS, the duty cycle will exceed 50%. Similar operation (more NMOS width on than PMOS) can be applied in cases where less than 50% is required. The method has the advantages of simple structure and low noise. The disadvantage is that the duty cycle adjustment resolution depends on the minimum width it can vary, and therefore the minimum range of duty cycle adjustment is limited.

Fig. 2 is a schematic diagram of a clock Duty Cycle Correction (DCC) output based on programmable current sources in which two current sources (ISR1 and ISR2) are located at the output node and are programmable to adjust the duty cycle. Assuming MP1 and MN1 are intensity matched, the nominal duty cycle is 50%. When a duty cycle in excess of 50% is required, ISR1 is turned on and ISR2 is turned off. The effective pull-up strength (combination of MP1 and ISR1) is greater than the pull-down strength (MN1 and ISR 2). Thus, the duty cycle will exceed 50%. Similar operations (turn on ISR2, turn off ISR1) may be applied where less than 50% is needed. The current flow in ISR1 and ISR2 can be fine tuned to achieve high duty cycle resolution. The main disadvantages are that the current sources ISR1/ISR2 generate extra noise and that when the current sources need to be well matched, a large area is needed to reduce the matching mismatch.

Disclosure of Invention

The present invention provides a multi-channel shared clock duty ratio correction circuit, which can save area, has high duty ratio calibration accuracy, and has low noise.

The technical scheme adopted by the invention for solving the technical problems is as follows: a multi-path shared clock duty ratio correction circuit is constructed and comprises a plurality of main alternating current coupling buffers, a multi-path selector, a shared resistor string and a copy bias module, wherein each main alternating current coupling buffer is respectively connected with the multi-path selector through a bias resistor, and the multi-path selector is connected with the copy bias module through the shared resistor string.

In the multi-path shared clock duty cycle correction circuit, the copy bias module comprises a PMOS tube and an NMOS tube, and a grid electrode of the PMOS tube, a source electrode of the PMOS tube, a grid electrode of the NMOS tube and a source electrode of the NMOS tube are all connected with the shared resistor string.

In the multi-channel shared clock duty ratio correction circuit, the shared resistor string comprises an upper layer resistor string and a bottom layer resistor string, and a node formed by connecting the upper layer resistor string and the bottom layer resistor string in series is connected with the grid electrode of the PMOS tube and the grid electrode of the NMOS tube.

In the multi-path shared clock duty cycle correction circuit, each main AC coupling buffer comprises a capacitor and an inverter, one end of the capacitor is connected with the input end of one path of clock, and the other end of the capacitor is connected with the output end of the clock through the inverter.

In the multi-channel shared clock duty correction circuit according to the present invention, the phase inverter includes a P-channel type main ac buffer transistor and an N-channel type main ac buffer transistor, a gate of the P-channel type main ac buffer transistor and a gate of the N-channel type main ac buffer transistor are both connected to the other end of the capacitor, and a source of the P-channel type main ac buffer transistor and a source of the N-channel type main ac buffer transistor are both connected to the output terminal of the clock.

In the multi-path shared clock duty cycle correction circuit, the other end of the capacitor is connected with two different input ends of the multiplexer through the bias resistor.

The multi-path shared clock duty ratio correction circuit has the following beneficial effects: the design is compact and has small area because the largest module (namely the shared resistor string and the copy bias module) is shared to a plurality of multi-paths (such as clock0, clock1, clock2 and clock3) to save area, and the invention can save area, has higher precision of duty ratio calibration and low noise.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a diagram illustrating a conventional duty cycle correction scheme in the prior art;

FIG. 2 is a diagram of a clock duty cycle correction output based on a programmable current source in the prior art;

FIG. 3 is a schematic structural diagram of an embodiment of a multi-way shared clock duty cycle correction circuit according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the embodiment of the multi-path shared clock duty cycle correction circuit of the present invention, a schematic structural diagram of the multi-path shared clock duty cycle correction circuit is shown in fig. 3. In fig. 3, the multi-path shared clock duty cycle correction circuit includes a plurality of main ac coupled buffers, a multiplexer, a shared resistor string, and a replica bias module, where each main ac coupled buffer is connected to the multiplexer through a bias resistor, and the multiplexer is connected to the replica bias module through the shared resistor string.

It is worth mentioning that 2 main ac-coupled buffers are shown as an example in fig. 3. In practical applications, the main ac coupling buffer may be multiple, for example: 4 of the Chinese herbal medicines. The design is compact and small in area. Since the largest modules (shared resistor string and replica bias module) are shared to multiple lanes (e.g., clock0, clock1, clock2, and clock3) to save area. The invention can save area, and has higher calibration precision of duty ratio and low noise.