阅读说明：本技术 晶片装置、其制造方法以及混合滤波器 (Wafer device, method for manufacturing the same, and hybrid filter ) 是由 M·希克 R·罗塞齐恩 于 2018-11-13 设计创作，主要内容包括：一种晶片装置包括具有顶表面的载体晶片(CW),该定表面被划分为第一表面区域(SA1,ARS)和第二表面区域(SA2,PES)的规则图案(RP),其中每个第一表面区域被分配给相邻地施加的相应的分开的第二表面区域,以一起形成组合滤波区域。薄膜压电材料的斑点被结合到第一表面区域。LC元件的电路(PES)由多层金属化(ML1,ML2)集成地形成在第二表面区域上。每个金属化层的LC元件被嵌入在电介质中。(A wafer device comprises a Carrier Wafer (CW) having a top surface, the top surface being divided into a Regular Pattern (RP) of first surface areas (SA1, ARS) and second surface areas (SA2, PES), wherein each first surface area is assigned to a respective separate second surface area applied adjacently to form together a combined filter area. A spot of thin film piezoelectric material is bonded to the first surface area. The circuitry (PES) of the LC element is integrally formed on the second surface area by a multilayer metallization (ML1, ML 2). The LC elements of each metallization layer are embedded in a dielectric.)

1. A wafer device comprises

-a Carrier Wafer (CW) having at least an electrically insulating top surface, the surface being divided into a Regular Pattern (RP) of first and second surface areas (SA1, SA2), wherein each first surface area (SA1) is assigned to a respective separate second surface area (SA2) applied adjacently to form together a combined filter area;

-a spot of thin film piezoelectric material (TF) bonded to said first surface area (SA 1);

-a circuit of LC elements (LC) integrally formed on said second surface area by a plurality of layers of metallization, said LC elements of each Metallization Layer (ML) being embedded in a dielectric.

2. Wafer device according to the preceding claim,

-wherein thin film SAW devices (TFS) are formed on the spot of thin film piezoelectric material (TF) such that each first surface area comprises one thin film SAW device (TFS),

-wherein each thin film SAW device is electrically interconnected with the circuitry of an assigned LC element (LC) to form a combined filter circuit comprising LC elements and thin film SAW devices (TFS).

3. Wafer device according to one of the preceding claims,

wherein the regular pattern of the first surface area and the second surface area is

a) A checkerboard pattern formed by the circuit of the LC element and the spot including the thin film SAW device (TFS), or

b) An alternating pattern of first parallel strips and second parallel strips, each first strip comprising a row of thin film SAW devices and each second strip comprising a row of LC circuits, or

c) A parallel arrangement of a first strip and a second strip, wherein the first strip and an adjacent second strip form a first pair of strips, wherein the second parallel strip and a second pair of strips of the adjacent first parallel strip are mirror-inverted with respect to the first pair of strips, and wherein the first pair of strips and the second pair of strips are alternately arranged.

4. Wafer device according to one of the preceding claims,

-wherein a spot of thin film piezoelectric material comprising more than one TFSAW device is provided with a trench pattern (TR),

-wherein the grooves are cut into the bottom surface of the spot of thin film Piezoelectric Material (PM) bonded into the carrier wafer,

-wherein the depth of the trenches ranges from half the layer thickness of the thin-film piezoelectric material to the total thickness d2 of the thin-film piezoelectric material, such that the top surface of the carrier wafer is exposed from the top in a separation line.

5. Wafer device according to one of the preceding claims,

wherein the thin film SAW device (TFS) is enclosed under a cover layer of a Thin Film Package (TFP) providing a cavity between the thin film SAW device (TFS) and the cover layer.

6. Wafer device according to one of the preceding claims,

the Dielectric (DE) in which the LC element (LC) is embedded is an organic dielectric.

7. Wafer device according to one of the preceding claims,

the Dielectric (DE) in which the LC element (LC) is embedded is an oxide such as silicon dioxide.

8. Wafer arrangement according to one of the preceding claims, wherein

-the LC element (LC) is formed by a multilayer metallization,

-each Metallization Layer (ML) of the LC element is embedded in a Dielectric (DE),

-the LC elements formed in the same metallization layer are electrically connected by wires,

-the LC elements formed in different metallization layers are interconnected by vias,

-said TFSAW device being electrically connected to the LC circuit by conducting lines guided on top of said thin film SAW device (TFS) and on top of said multilayer metallised topmost Dielectric (DE), respectively.

9. A method of manufacturing the wafer device of claim 1, comprising the steps of

a) Providing a Functional Wafer (FW) comprising a crystalline Functional Layer (FL);

b) dividing the functional wafer (W1) into a Regular Array (RA) of virtual functional chip parts (FCS), and separating the functional wafer (W1) into smaller spots, each spot comprising

Only a single functional chip part, or

A strip with several functional chip parts arranged in a row, or

-a strip with functional chip portions arranged in two parallel rows;

c) providing a Carrier Wafer (CW);

d) dividing the main surface of the carrier wafer (W2) into a regular pattern of virtual carrier chip portions (CCS), each virtual carrier chip portion comprising an area for a virtual functional chip portion and a virtual passive component portion;

e) bonding the spots to the main surface (BS) of the carrier wafer (W2) such that

-each functional chip portion of the patch completely covers a first surface area of the respective virtual carrier chip portion, while a second surface area of the respective carrier chip portion (CCS) remains exposed;

f) the thickness d1 of the functional layer of all spots is reduced until a thin film functional layer (TF) with the desired thickness d2 is achieved in each spot.

10. The method according to the preceding claim, wherein,

comprising a step h

h) The first partial circuit (PC1) of the hybrid filter is formed by a circuit of LC elements (LS) which is produced on the exposed second surface (SA2) area of each such virtual carrier chip section.

11. The method according to one of the preceding claims,

comprising a step i) performed before or after step h)

i) Forming a second partial circuit of the filter circuit by a circuit of the SAW resonator generated on each of the functional chip sections;

k) integrally connecting a first sub-circuit and a second sub-circuit on each of the carrier chip sections to form a combined filter circuit;

l) separating the carrier wafer into individual carrier chip sections by dicing.

12. A hybrid filter comprising a combined filter circuit singulated from a wafer device as claimed in any one of the preceding claims.

Background

In order to satisfy the fifth generation (5G) mobile communication standard, a band pass filter function at an increased operating frequency and a high bandwidth is required.

The acoustic filter typically has a ladder or lattice structure. In a ladder configuration, series resonators and parallel resonators are combined to create a desired filter function, e.g., a bandpass function. In the lattice structure, two series signal lines having series resonators are interconnected with parallel arms in which the parallel resonators are arranged, respectively. It is estimated that the achievable bandwidth of such a filter structure may be about twice the pole-zero distance PZD of the resonator used. The standard topology of such filter structures uses SAW resonators or BAW resonators, which are comparable in terms of PZD.

However, the required bandwidth and selectivity cannot be achieved simultaneously using conventional ladder bandpass filters.

LC elements may also be used to form filter structures. The bandwidth of the LC filter is high but due to the low Q factor the skirt of the achievable passband is not as steep as the skirt of the acoustic resonator in SAW or BAW technology.

To further improve the performance of critical skirts of the filter passband, acoustic resonators are used in combination with LC elements to enhance the steepness of the skirt to maintain a high bandwidth.

A recent approach for improving the quality of LC elements is described in the published patent application US 2017/0077079 a 1. There, glass substrates are used to build high-Q LC elements in multilayer metallizations embedded in dielectrics. Vias are used to interconnect different metallization layers and improve the degree of integration. In the following context, these LC elements are referred to as POGs (passive on glass).

Recently, a high performance SAW device called a thin film SAW (tfsaw) has been proposed to provide low loss wave propagation. TFSAW is formed from a thin film piezoelectric layer disposed on a carrier substrate such as Si, glass or ceramic. The device can be fabricated by bonding a piezoelectric single crystal wafer to a carrier wafer and thinning the single crystal wafer to a desired low thickness of about 1 μm.

In order to form a hybrid filter by combining a TFSAW structure and an LC structure, it would be necessary to use two different and therefore separate wafers to achieve this combination. Two dies result in a large area consumption, which is undesirable and may be critical in mobile or handheld devices.

Disclosure of Invention

It is an object of the present invention to provide a hybrid filter that overcomes the above problems.

This and other objects are achieved by a wafer arrangement according to claim 1. Other embodiments of the invention are the subject of other claims.

The general idea of the invention is to arrange the spots of thin-film piezoelectric material and the circuitry of the LC elements together on a common carrier wafer. The carrier wafer has at least an electrically insulating top surface divided into a regular pattern of first and second surface areas. Each first surface area is assigned to a respective second surface area directly adjacent to the respective first surface area. The respective first surface area and the assigned adjacent second surface area together form a combined filter area. A spot of thin film piezoelectric material is bonded to the first surface area and the circuitry of each LC element is integrally formed on the respective second surface area by the multilayer metallization. The LC elements of each metallization layer are embedded in a dielectric.

Each spot provides an area of piezoelectric film corresponding to an area of at least one SAW device to be fabricated on the spot. Each SAW device in the future requires an area referred to as a virtual functional chip portion of thin film piezoelectric material. However, the blob may include a greater number of functional chip portions.

Each second surface area includes an area sufficient for at least one LC circuit, which is referred to as a dummy passive component portion. The LC circuit is part of a combined filter that also includes a corresponding SAW device.

The size of the spots and the arrangement of the functional chip parts and the passive component parts depend on the prerequisite that, in a regular pattern of the carrier wafer, each virtual functional chip part on a first surface area needs to be adjacent to a corresponding passive component part and that all first surface area has to be occupied by a spot. Preferably, the blob is large to include as many virtual functional chip portions as possible.

The choice of the size of the regular pattern depends on the area required for the subsequent combining filter. Each section is preferably rectangular or square. The combined filter or the hybrid filter includes: thin film SAW devices formed on corresponding virtual functional chip portions on spots of thin film piezoelectric material; and a circuit of assigned LC elements interconnected with the SAW device.

Hybrid filters combine two different technologies. The first surface region may be different in size from the second surface region depending on the area requirements. Thus, a regular pattern refers to an alternating sequence of first and second surface regions arranged in two dimensions on a carrier wafer.

The regular pattern may include a checkerboard pattern formed by a dummy functional chip portion and a corresponding dummy passive element portion. A thin film SAW device can be incorporated on each functional chip portion and a corresponding LC circuit can be formed on each virtual passive element portion. In each row of the checkerboard pattern, the first surface area and the second surface area are alternating, and each first surface area and second surface area in this row comprises only one SAW device and one LC circuit, as is necessary to form a combined or hybrid filter. The same alternating sequence is present in each column of the regular pattern. For a checkerboard pattern, the first surface area and the second surface area must have the same size.

Another possible regular pattern includes first parallel strips and second parallel strips, where each first strip includes a row of thin film SAW devices and each second strip includes a row of LC circuits. The first and second strips are adjacent to each other such that each first surface area is adjacent to a second surface area. Each bar may have a length according to a diameter of the carrier wafer. However, smaller strips (i.e., shorter strips) are also possible.

In another possible arrangement, the first and second strips are arranged such that the first strip and the adjacent second strip form a first pair of strips. The second parallel strip and a second pair of strips adjacent the first parallel strip are mirror-inverted with respect to the first pair of strips. The first and second pairs of strips are alternately arranged. In this pattern, the smallest repeating unit includes four parallel stripes, which are two adjacent first stripes and a second stripe adjacently disposed on both sides of the two first stripes.

The arrangement of the first and second bars allows for the required size of the first and second surface areas to be independently selected for the virtual functional chip portion and the virtual passive component portion, respectively.

The proposed wafer arrangement has the great advantage that the size of the carrier wafer can be selected as large as possible and that, independently of the size of the functional wafer, spots of thin-film piezoelectric material are cut out of the functional wafer. As a result, and in addition, hybrid filters can be implemented on a carrier wafer in parallel for a greater number of devices than on a functional wafer.

In a first step of manufacturing such a wafer device, a spot of piezoelectric material is bonded to a carrier wafer. The first thickness d1 of the spot of piezoelectric material is higher than the second thickness d2 of the rear thin film SAW device.

If the spot of piezoelectric material bonded to the carrier wafer comprises more than one thin film SAW device, the thin film piezoelectric material is preferably provided with a pattern of spaced lines to support later singulation of the completed individual hybrid filter chips. The separation line is cut into the bottom surface of the spot, which is the surface bonded to the carrier wafer.

The depth of the separation line may be in the range of about half the layer thickness of the thin-film piezoelectric material to its total thickness. The spots (which have areas that are compliant with a relatively high number of virtual functional chip parts) can be handled and bonded without any problems due to their relatively high thickness. In a subsequent step, a final thickness d1 is achieved due to the thinning process of the spots, wherein d1< d 2.

According to one embodiment, the electrode structures of thin film SAW devices fabricated on and in the first surface area above each virtual functional chip portion are enclosed in a cavity below, between the cover layer of the thin film package and the surface of the thin film piezoelectric material.

The cover layer may enclose the entire thin film SAW device within a single cavity. Since SAW devices typically comprise a series of resonators, it is preferred to arrange one or more resonators in respective cavities. Thus, each SAW device includes multiple cavities beneath the cladding layer.

The multilayer metallized LC elements may be embedded in an organic dielectric. According to another embodiment, the dielectric may be a ceramic or another inorganic dielectric. Furthermore, different dielectrics may be used to stack different metallization layers on top of each other. Preferred inorganic dielectrics are oxides such as silicon dioxide.

The LC elements formed in the same metallization layer may be electrically connected by wires. LC elements formed in different metallization layers may be interconnected by vias.

The thin film SAW devices may be electrically connected to the LC circuit by top wires that are routed on top of the thin film SAW devices and on top of the uppermost dielectric of the LC circuit, respectively. LC elements requiring two or more metallization layers may have additional or alternative electrical connections formed by the bottom conductors.

A method of manufacturing a wafer device is also within the scope of the invention. The method comprises the following steps:

a) providing a functional wafer comprising a crystalline functional layer;

b) dividing the functional wafer into a regular array of virtual functional chip portions, and separating the functional wafer (W1) into smaller spots, each spot comprising

Only a single functional chip part, or

A strip with several functional chip parts arranged in a row, or

-a strip with functional chip portions arranged in two parallel rows;

c) providing a carrier wafer;

d) dividing the main surface of the carrier wafer into a regular array of virtual carrier chip sections, each virtual carrier chip section comprising areas for virtual functional chip sections and virtual passive component sections;

f) bonding the spots to the major surface of the carrier wafer such that

Each functional chip portion of the spot completely covers a first surface area of the respective virtual carrier chip portion, while a second surface area of the respective functional chip portion remains exposed;

g) the thickness d1 of the functional layer of all spots is reduced until a thin film functional layer with the desired thickness d2 is achieved in each spot.

Preferably, the functional wafer is a piezoelectric wafer cut out from a crystal bar. The dummy functional chip portion is an area required for forming a thin film SAW device thereon. Therefore, the virtual functional chip section is the smallest unit of the functional wafer and the subsequent wafer device.

The area of the carrier wafer can be larger than the area of the functional wafer because there are no restrictions due to crystal growth. The virtual carrier chip portion is the area on which the hybrid filter, including the circuitry of the LC elements and the thin film SAW devices, is formed. The areas of the first surface area and the second surface area may be the same or different within the virtual carrier chip section.

The size and dimensions of the spots may be the same. However, the spots may also have different sizes or dimensions, arranged to form the above-described arrangement with a single row of strips, or with strips comprising two parallel rows adjacent to each other. This is because the sizes of the carrier wafer and the functional wafer may differ by more than a factor of 2 such that the number of carrier chip portions on the carrier wafer is greater than the number of functional chip portions that can be retrieved from one functional wafer. Due to the circular form of the functional wafer, dividing the functional wafer into spots as described above results in spots of different sizes. Thus, the placement of spots of functional wafer material onto the carrier wafer results in a kind of damascene.

The bonding of the spots to the main surface of the carrier wafer can be carried out simultaneously for all spots in a single bonding step. According to a variant, each spot may be bonded to the carrier wafer separately.

After bonding the spots to the carrier wafer, the thickness of the functional layer of all spots is reduced such that all first surface areas are partially covered by the functional chip.

The thickness of the functional layer of all spots can be reduced by a grinding method followed by Chemical Mechanical Polishing (CMP).

In a subsequent step h), a circuit of LC elements is formed on the exposed second surface area of each virtual carrier chip section. The circuit is the first part of the circuit of a combined or hybrid filter.

According to a variant of the method, the thin-film piezoelectric material is polished after the second partial circuit comprising the LC element is manufactured. Thus, any impurities due to LC production performed on the piezoelectric material can be removed.

In a subsequent step i) which can be carried out after step h), a second partial circuit of the hybrid filter comprising the SAW resonator is produced on each functional chip part.

According to an alternative embodiment, the order of steps h) and i) may be interchanged.

In a subsequent step k), the first partial circuit and the second partial circuit on each carrier chip section are connected to form a combined filter circuit as a hybrid filter. Alternatively, the interconnection is realized during integration forming the first partial circuit or the second partial circuit.

In a subsequent step, the carrier wafer is separated into individual carrier chip portions by dicing. Each carrier chip part then comprises an active hybrid filter, which can later be provided with a package. According to one variation, the packaging of thin film SAW devices can be fabricated on a wafer stage prior to separating the carrier wafer into individual carrier chip portions.

Forming a thin film package for a SAW device includes applying and structuring a sacrificial layer of material that can be easily removed in subsequent steps. Such a sacrificial layer may be an organic material or may comprise silicon oxide.

After structuring the sacrificial material, the sacrificial material remains only on the areas that need to be enclosed under the cavity of the package. As already mentioned, one or more individual resonators may be included in each cavity.

A capping layer is created onto the structured sacrificial material to seal to the surface of the piezoelectric material. In a next step, openings are formed and the sacrificial material is removed through the openings. After closing the opening, a further cover layer may be applied.

According to further embodiments, the SAW device may be packaged in another manner, for example, by mounting a rigid cap thereon or incorporating the entire arrangement of covers prior to separation and singulation of the individual carrier chip portions.

Drawings

Hereinafter, the present invention will be explained in more detail with reference to specific embodiments and drawings. The figures are merely schematic and not drawn to scale, so that for better understanding, individual parts of the figures may be depicted larger than their actual parts. Therefore, neither absolute nor relative dimensions can be derived from the figures.

FIG. 1 shows a functional wafer in top view and cross-section;

FIG. 2A shows a schematic top view of a carrier wafer having a checkerboard pattern of first and second surface areas;

fig. 2B shows a carrier wafer with a regular pattern comprising rows of functional chip sections in a top view;

fig. 2C shows in top view a carrier wafer with a regular pattern comprising two parallel rows of strips of functional chip portions;

fig. 3A to 3i show different stages of the manufacturing process in cross-sectional views;

FIG. 4 is a schematic cross-sectional view of a hybrid filter;

fig. 5 is a block diagram of the LC element and the first and second partial circuits of the acoustic resonator;

FIG. 6 is a more detailed cross-sectional view of the multilayer metallization of the circuit including the LC elements;

fig. 7 shows a cross section of a hybrid filter comprising a first part-circuit and a second part-circuit interconnected;

figure 8 is a block diagram of a ladder filter of acoustic resonators;

fig. 9 is a block diagram of a lattice filter of acoustic resonators.

Detailed Description

The method for producing a wafer arrangement starts with a functional wafer FW. The functional wafer FW is divided into a regular array of virtual functional chip parts FCS, as shown in the top view on the left side of fig. 1. A corresponding cross section of functional wafer FW is shown on the right side of fig. 1. The functional wafer has a thickness d 1.

In a next step, the functional wafer FW is separated into smaller spots such that each spot includes

Only a single functional chip part, or

A strip with several functional chip parts arranged in a row, or

-a strip with functional chip portions arranged in two parallel rows.

Different sized spots can be retrieved from one functional wafer. However, it is preferred to retrieve the blob that includes the largest number of functional chip portions to support processing of the blob.

Independently thereof, the carrier wafer CW is divided into a Regular Pattern (RP) of Carrier Chip Sections (CCS), each CCS comprising a first surface area SA1 and a second surface area SA 2.

Fig. 2A to 2C show different arrangements of the first and second surface regions and the respective carrier parts comprising the first and second surface regions.

Fig. 2A shows a carrier wafer in which first surface area SA2 and second surface area SA2 are arranged in a checkerboard pattern. This means that in a horizontal row the first surface area and the second surface area alternate. In each vertical column, the first surface area and the second surface area also alternate such that each row is shifted relative to an adjacent row. First surface area SA1 and adjacent second surface area SA2 form a virtual carrier chip section CCS. In the figure, only two such virtual carrier chip sections CCS are marked with bold line rectangles.

Fig. 2B shows a carrier wafer CW having a second arrangement of first surface areas SA1 and second surface areas SA 2. A row of first surface areas SA1 and a row of second surface areas SA2 are arranged parallel to each other in an alternating order. The dimensions of the rows are determined to cover the maximum amount of carrier wafer CW so that the maximum number of carrier chip portions CCS can be retrieved.

Fig. 2C shows a third possible arrangement, in which the first surface areas SA1 are arranged in two adjacent parallel rows. Between the two pairs of rows, two rows of second surface areas are interposed, thereby forming carrier chip sections CCS each of which includes first surface area SA1 and adjacent second surface area SA 2.

Spots of piezoelectric material cut out from the functional wafer FW are arranged on the carrier wafer CW thus divided such that each first surface area SA1 is partially covered by a virtual functional chip of the spot of piezoelectric material. In order to cover all the first surface area SA1 of the carrier wafer with corresponding virtual functional chip portions FCS, different sized spots of piezoelectric material may be used. This means that any one row of the first surface area of fig. 2B and 2C may be covered by a plurality of different spots, wherein each spot may comprise one or more virtual functional chip portions FCS.

Fig. 3A shows a cross-section of a carrier wafer CW provided with spots of piezoelectric material PM according to the arrangement shown in fig. 2A or 2B. The piezoelectric material PM has the original thickness d1 of the original functional wafer FW. To obtain the thin-film piezoelectric material TF, the thickness of the spot of piezoelectric material PM is reduced to a thickness d 2. Fig. 3B shows the arrangement at this stage.

In the next step, on each exposed second surface area SA2 of fig. 3B, a circuit of the LC element is formed. The LC elements form the first part of the circuit of the desired hybrid filter. Fig. 3C shows a cross-section of the carrier wafer at this stage, in which the first surface area is covered by the thin-film piezoelectric material and the second surface area is covered by the circuitry of the LC element LC.

Another embodiment includes a series of steps and stages as shown in figures 3D, 3E and 3C. The method starts with a carrier wafer as shown in fig. 2. As shown in fig. 3D, the circuit of the LC element LC is created on the second surface area SA2 of the carrier wafer, and the first surface area SA1 is exposed.

Spots of piezoelectric material PM of thickness d1 are arranged into these exposed first surface areas and bonded to the carrier wafer CW. Fig. 3E shows the arrangement of this stage.

After thinning the spot of piezoelectric material PM to a thickness d2, the arrangement according to fig. 3C is realized. This phase corresponds to the corresponding phase of the first variant.

According to an alternative embodiment, not shown in the drawings, the arrangement shown in fig. 3B is subjected to a process of forming a thin film SAW device TFS on a spot of thin film piezoelectric material.

A further intervening step includes encapsulating the thin film SAW device TFS with a thin film SAW package such that the pad PD of the thin film SAW device TFS is exposed for electrical interconnection with the circuitry of the subsequent LC element. The electrical contacts may be integrally formed when creating the circuit of the LC element LC.

In a step subsequent to the stage shown in fig. 3B or 3C, the thin-film SAW device TFs is fabricated by forming a metal electrode structure on the top surface of the thin-film piezoelectric material TF. The thin-film SAW devices TFS of the carrier chip section are then connected by means of corresponding wires to the circuits of the corresponding LC elements LC of the same carrier chip section CCS. In this way, a hybrid filter including respective circuits of thin film SAW devices and LC elements is realized in each carrier chip section CCS.

In a subsequent step, the hybrid filter thus produced is singulated by dicing the carrier chip and the corresponding structures formed thereon along the separation lines SL, as shown in fig. 3F.

Fig. 3G shows a single hybrid filter comprising exactly one carrier chip part CCS comprising an interconnection circuit of thin film SAW devices TFS and LC elements LC.

Alternatively, the packaging of the hybrid filter may be performed at the stage shown in fig. 3F. The encapsulation is not shown in the figure.

Fig. 3H and 3i show a preferred method of processing spots of piezoelectric material PM comprising more than one functional chip part FCS. To facilitate later separation into individual chips, grooves TR are provided on the bottom surface of the spots. The trenches divide adjacent functional chip portions. As shown in fig. 3H, each trench TR may have a thickness between d1 and d2, but leaves sufficient mechanical stability to the spot for safe handling thereof.

Fig. 3i shows the arrangement after thinning the piezoelectric material PM to a thickness d 2. Thereby, the trenches are exposed from the top, and gaps GP are formed between adjacent functional chip portions of the thin-film piezoelectric material TF. The second surface area SA2 on the carrier wafer CW remains exposed. This may be followed by a step of polishing the surface.

Fig. 4 schematically shows a hybrid filter. The hybrid filter comprises a passive element part PES and an acoustic resonator part ARS. The acoustic resonator section ARS includes a SAW resonator circuit forming a SAW device which is the second partial circuit of the hybrid filter. The exact structure of the SAW devices forming the second partial circuit PC2 of the hybrid filter is not shown.

The passive element part PES comprises several metallization layers ML1, ML2, two of which are shown in fig. 4. In the first metallization layer ML1, for example, a capacitor MIM may be formed. In the second metallization layer ML2, an inductor or coil may be formed and interconnected with the passive elements of the first metallization layer ML1 by vias. Alternatively, after embedding the first metallization layer ML1 in the dielectric, it is necessary to expose the structures of the first metallization layer ML1 that are to be connected with the structures of the second metallization layer ML 2. The figure does not show the wires and vias connecting the passive elements of the passive element part PES and the SAW resonator SR of the acoustic resonator part ARS.

Fig. 5 shows a block diagram of a hybrid filter with a minimum number of elements. A practical circuit may comprise a greater number of such structures. In fig. 5, the first partial circuit PC1 comprises a series impedance element IE_SAnd a parallel impedance element IE_P. Series impedance element IE_SCan be embodied as a capacitor and connected in parallel with an impedance element IE_PMay be embodied as a coil. The second sub-circuit PC2 comprises at least one series SAW resonator SR_SAnd at least one parallel SAW resonator SR_P. As shown in fig. 5, within the combined circuit, the first partial circuit PC1 and the second partial circuit PC2 may be arranged alternately or in an arbitrary order. The precise design of such a hybrid filter can be optimized according to the requirements of the desired hybrid filter. Such optimization can be easily accomplished by a skilled person by optimizing the computer program.

Fig. 6 shows a schematic cross section of the passive element part PES of the hybrid filter. The passive component part may be formed according to the method described in the above-mentioned US 2017/0077079 a 1. On a carrier wafer CW, preferably a planar glass wafer, a first LC element is formed and embedded in a first dielectric DE 1. In this figure, the LC element is embodied as a metal-insulator-metal capacitor MIM (which is a first metal structure covered by a dielectric layer DL and another metal structure as a second capacitor electrode).

Above the first dielectric DE1, a second metallization layer ML2 is formed, structured and embedded in the second dielectric DE 2. Both dielectrics DE1 and DE2 may be the same or different for both metallization layers. One element of the capacitor MIM can be constructed as a top electrode in the second metallization layer.

The metal structure may be made of Al or AlCu alloy. The dielectric layer DL may be an oxide such as silicon oxide.

Above the first dielectric DE1, a second metallization layer ML2 is formed, structured and embedded in the second dielectric DE 2. The coil IND consists of a second metallization layer ML2, in addition to the top electrode of the capacitor MIM. To form the planar coil IND, a single masking step is used to construct the second metallization layer ML2 accordingly.

The metallization layer ML may be structured by first forming and structuring a resist mask and then depositing metal in the areas exposed by the resist mask. The deposition of the metal may be done by electroplating the metal onto a seed layer applied to the entire surface of the substrate SU for the first metallization layer, or by electroplating the metal onto the first dielectric DE1 or higher. After the electroplating step, the resist mask is removed, thereby exposing the remaining seed layer regions, which are then also removed.

A three-dimensional coil IND (not shown) needs to be formed in two adjacent metallization layers. One of the two adjacent metallization layers may be a first metallization layer ML 1.

To interconnect the two metallization layers ML1, ML2, the respective metallization in the lower metallization layer ML1 is exposed by forming an opening in the top surface of the first dielectric DE 1. The structures of the second metallization layer ML2, which may now be applied thereon, contact corresponding structures in the first metallization layer ML 1. All structures that do not require interlayer electrical connections are isolated from each other by the first dielectric DE 1.

The circuitry of the LC element LC is formed integrally in the two-layer metallization.

In the area of the interconnect ICN, vias may provide electrical contact between different metallization layers and contact areas CA on the top surface of the circuitry of the LC elements. Alternatively, the electrical interconnections of the LC circuits are placed at the bottom by wires on the top surface of the carrier wafer or at a higher level, depending on the structures present on the carrier wafer CW.

Fig. 7 shows a cross section of a carrier chip section CCS of a wafer arrangement that can be singulated from the wafer arrangement. As already schematically shown in fig. 4, the combined filter circuit is arranged on the carrier wafer CW and comprises a passive element part PES and an acoustic resonator part ARS. The acoustic resonator section ARS comprises a thin film SAW device TFS realized by providing an electrode structure above the functional layer FL of the thin film piezoelectric layer. The thin film SAW device TFS is enclosed by a thin film encapsulation TFP which provides a cavity enclosing the electrode structure of the thin film SAW device.

The thin film package TFP may expose a pad PD connected to the electrode structure of the thin film SAW device TFS to enable electrical contact to the circuitry of the LC element arranged in the passive element portion PES. In this embodiment, the thin film SAW device TFS is fully encapsulated before the multilayer metallization of the circuitry of the LC elements is fabricated and deposited in the passive elements portion PES. In the figure, the metal structure of the second metallization layer ML2 is in direct contact with the pad PD to interconnect the passive element portion PES and the acoustic resonator portion ARS.

The acoustic resonator section ARS may comprise a circuit of thin film SAW resonators SR connected in a ladder or lattice type topology as schematically shown in fig. 8 and 9.

FIG. 8 shows a resonator SR comprising a series SAW resonator_SAnd parallel SAW resonator SR_PA ladder-type arrangement of (a). In this embodiment, the corresponding series SAW resonator SR_SAnd corresponding parallel SAW resonator SR_PForming a basic part BS of a ladder-type arrangement_LT. The ladder arrangement comprises a plurality of basic sections BS_LTThese basic parts may be connected in series electrical circuit to achieve the desired filtering function of the second partial filter circuit PC 2.

Fig. 9 shows a lattice type arrangement of SAW resonators including series SAW resonators and parallel SAW resonators. Parallel SAW resonator SR in contrast to ladder arrangement_PArranged in parallel branches which connect two series signal lines with the series SAW resonator SR_SAnd (7) interconnection. The parallel branches are connected in a cross arrangement circuit such that the lattices arrange BS_LCComprises a first SAW resonator SR arranged in series in two different signal lines_SAnd a second SAW resonator SR_SAnd with respective parallel SAW resonators SR arranged therein_PTwo crossed parallel branches of the circuit connection. The lattice type filter may also include a plurality of basic sections according to the requirements of the filter.

The present invention has been described only by way of a limited number of examples and is therefore not limited to these examples. The invention is defined by the scope of the claims and may be different from the embodiments presented.

Such other embodiments may include other details not shown in the presented embodiments. Further, the wafer device and each hybrid filter may include any circuit of LC elements and SAW devices of any structure. The hybrid filter may implement any one of a range of different filter functions. Examples are band-pass, high-pass and low-pass and combination filters, such as extractors, duplexers or multiplexers. Such other embodiments may include other details not shown in the presented embodiments. Further, the wafer device and each hybrid filter may include any circuit of LC elements and SAW devices of any structure. The hybrid filter may implement any one of a range of different filter functions. Examples are band-pass, high-pass and low-pass and combination filters, such as extractors, duplexers or multiplexers.

List of reference signs used