阅读说明：本技术 一种对组合逻辑电路等价验证的分级方法 (Grading method for equivalent verification of combinational logic circuit ) 是由 袁军 陈梦洁 于 2020-07-08 设计创作，主要内容包括：本发明属于芯片设计领域,公开了一种对组合逻辑电路等价验证的分级方法,包括以下步骤：S1、对优化前后的芯片设计进行触发器配对；S2、对配对后的触发器的跳转逻辑电路进行分级,所述分级包括：所述跳转逻辑电路的输入信号级数为0；所述跳转逻辑电路中任意一个逻辑门电路的内部信号级数为当前输入信号级数的最大值加1；S3、对分级后的所述逻辑门电路的内部信号逐级匹配,得到匹配信号；S4、对所述匹配信号进行逐级的等价验证,若当级匹配信号被证明等价,则仅保留一个代表信号进行下级验证。逐级分级对电路进行简化并进行等价验证,更大限度的降低整个芯片设计电路验证的复杂度。(The invention belongs to the field of chip design and discloses a grading method for equivalent verification of a combinational logic circuit, which comprises the following steps: s1, carrying out trigger pairing on the chip designs before and after optimization; s2, classifying the jump logic circuit of the paired trigger, wherein the classification comprises the following steps: the input signal stage number of the skip logic circuit is 0; the internal signal stage number of any logic gate circuit in the jump logic circuit is the maximum value of the current input signal stage number plus 1; s3, matching the internal signals of the logic gate circuit after grading step by step to obtain matching signals; and S4, performing stage-by-stage equivalence verification on the matching signals, and if the stage-by-stage matching signals are proved to be equivalent, only one representative signal is reserved for performing lower-stage verification. The circuit is simplified and equivalent verification is carried out step by step, and the complexity of circuit verification of the whole chip design is reduced to the greatest extent.)

1. A method of ranking combinatorial logic circuit equivalence verification, comprising: the method comprises the following steps:

s1, carrying out trigger pairing on the chip designs before and after optimization;

s2, classifying the jump logic circuit of the paired trigger, wherein the classification comprises the following steps: the input signal stage number of the skip logic circuit is 0; the internal signal stage number of any logic gate circuit in the jump logic circuit is the maximum value of the current input signal stage number plus 1;

s3, matching the internal signals of the logic gate circuit after grading step by step to obtain matching signals;

and S4, performing stage-by-stage equivalence verification on the matching signals, and if the stage-by-stage matching signals are proved to be equivalent, only one representative signal is reserved for performing lower-stage verification.

2. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: the grading further comprises: the output signal level of any logic gate circuit is the maximum value of the current input signal level plus 1.

3. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: the method before S1 further includes the step of reading in chip design codes and parsing the chip design codes into a netlist.

4. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: and matching the internal signals of the logic gate circuit after grading by adopting a simulation pairing mode.

5. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: performing step-by-step equivalence verification on the matching signal further comprises: if the current stage matching signal proves to be not equivalent, the verification is finished.

6. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: the step-by-step equivalence verification is carried out according to the sequence of signal steps from small to large.

7. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: the equivalence verification adopts BDD or SAT algorithm.

8. A method of ranking combinatorial logic circuit equivalence verification according to claim 1, characterized in that: the skip logic circuit has only one output signal, and the equivalence verification further comprises: the output signal is verified.

9. A method of ranking combinatorial logic circuit equivalence verification according to claim 8, wherein: verifying the output signal comprises: if the value of the output signal is 0, the whole circuit is equivalent.

10. A method of ranking combinatorial logic circuit equivalence verification according to claim 8, wherein: if the value of the output signal is 1, the whole circuit is not equivalent.

Technical Field

The invention relates to the field of chip design, in particular to a grading method for equivalent verification of a combinational logic circuit.

Background

Equivalence verification is a common method for verifying functional consistency of a design before and after optimization in chip design. In the equivalence verification, the two designs before and after optimization are firstly paired with triggers, and then jump (input) logics of the paired triggers are compared. Since the jump logic is combinational logic, all such comparisons are referred to as combinational logic equivalence verification.

The combinational logic equivalence verification is usually solved directly by using BDD and SAT algorithms, but under the condition that the scale of a combinational logic circuit is large, the direct solving may not be converged, and with the increase of the complexity of the circuit, the memory requirement is increased sharply, and finally the verification failure may be caused.

Disclosure of Invention

The invention mainly solves the technical problem of providing an equivalence verification method, which can solve the problem that the complexity of the design verification of the whole combinational logic circuit cannot be reduced to a greater extent in the prior art.

In order to solve the technical problems, the invention adopts a technical scheme that: a grading method for the equivalence verification of a combinational logic circuit is provided, which comprises the following steps:

s1, carrying out trigger pairing on the chip designs before and after optimization;

s2, classifying the jump logic circuit of the paired trigger, wherein the classification comprises the following steps: the input signal stage number of the skip logic circuit is 0; the internal signal stage number of any logic gate circuit in the jump logic circuit is the maximum value of the current input signal stage number plus 1;

s3, matching the internal signals of the logic gate circuit after grading step by step to obtain matching signals;

and S4, performing stage-by-stage equivalence verification on the matching signals, and if the stage-by-stage matching signals are proved to be equivalent, only one representative signal is reserved for performing lower-stage verification.

The logical hierarchy is based on logical dependencies, i.e., the logic device inputs are ranked higher than the outputs. In chip design, the combinational logic generally has no loop, and if the combinational logic has the loop, the loop cutting process is carried out. The grading is thus complete. After signals in the pairing trigger jump logic are graded in the netlist, the signals are further subjected to simulation pairing, and then equivalence verification is performed from the pairing signal with the highest grade.

Preferably, the ranking further comprises: the output signal level of any logic gate circuit is the maximum value of the current input signal level plus 1.

Preferably, a hierarchical method for equivalence verification of combinational logic circuits further includes the step of reading in chip design codes and parsing into a netlist before S1.

Preferably, in the classification method for the equivalence verification of the combinational logic circuit, a simulation pairing mode is adopted for the matching of the internal signals of the logic gate circuit after classification.

Preferably, a method for performing equivalence verification on a combinational logic circuit in a hierarchical manner, where performing equivalence verification on the matching signal in a hierarchical manner further includes: if the current stage matching signal proves to be not equivalent, the verification is finished.

Preferably, the step-by-step equivalence verification is performed according to the sequence of signal steps from small to large.

Preferably, a hierarchical method for equivalence verification of combinational logic circuits employs a BDD or SAT algorithm.

Preferably, a hierarchical method for equivalence verification of a combinational logic circuit, said toggle logic circuit having only one output signal, said equivalence verification further comprising: the output signal is verified.

Preferably, a hierarchical method of validating an equivalence of combinational logic circuits, validating the output signal comprises: if the value of the output signal is 0, the whole circuit is equivalent.

A grading method for the equivalence verification of a combinational logic circuit is characterized in that if the value of an output signal is 1, the whole circuit is not equivalent.

The invention has the beneficial effects that: the combined logic circuit is classified by adopting a step-by-step classification method, and the classified jump logic is subjected to step-by-step equivalent verification, so that the combined logic circuit is simplified in a grading manner, and the complexity of design verification of the combined logic circuit is greatly reduced.

Drawings

FIG. 1 is a logic level schematic of a two gate level circuit;

FIG. 2 is a schematic diagram of a simplified circuit after the 2 nd stage gate circuit verifies equivalence;

FIG. 3 is a schematic diagram of a simplified circuit after the 2 nd stage gate circuit verifies equivalence.

Detailed Description

In order to make the technical solution and the purpose of the present invention clearer, the following embodiments are further illustrated with reference to the accompanying drawings.