阅读说明：本技术 高频放大电路及半导体装置 (High-frequency amplifier circuit and semiconductor device ) 是由 濑下敏树 栗山保彦 于 2019-07-09 设计创作，主要内容包括：实施方式提供使输出端口间的隔离性能提高的高频放大电路。根据一个实施方式,高频放大电路具备第1放大电路、第2放大电路及噪声指数改善电路,具备：单一输出模式,从第1放大电路及第2放大电路中的一方输出放大后的信号；及分路输出模式,从第1放大电路及第2放大电路这双方输出放大后的信号。第1放大电路,将源极经由第1源极电感器而接地且在栅极被施加输入信号的第1晶体管、与从漏极输出将从上述第1晶体管的漏极输出的信号放大后的信号且栅极接地的第3晶体管级联连接而成。第2放大电路具备具有与第1放大电路同样的电路常数的电路元件。噪声指数改善电路将第1晶体管的源极及第2放大电路的第2晶体管的源极经由电容器而连接。(The embodiment provides a high-frequency amplifying circuit which improves the isolation performance between output ports. According to one embodiment, a high-frequency amplifier circuit includes a1 st amplifier circuit, a 2 nd amplifier circuit, and a noise figure improvement circuit, and includes: a single output mode in which the amplified signal is output from one of the 1 st amplifier circuit and the 2 nd amplifier circuit; and a split output mode in which amplified signals are output from both the 1 st amplifier circuit and the 2 nd amplifier circuit. The 1 st amplifier circuit is formed by cascade-connecting a1 st transistor having a source grounded via a1 st source inductor and a gate to which an input signal is applied, and a 3 rd transistor having a drain from which a signal obtained by amplifying a signal output from the drain of the 1 st transistor is output and a gate grounded. The 2 nd amplifier circuit includes circuit elements having the same circuit constants as those of the 1 st amplifier circuit. The noise figure improvement circuit connects the source of the 1 st transistor and the source of the 2 nd transistor of the 2 nd amplification circuit via a capacitor.)

1. A high-frequency amplification circuit is provided with:

a1 st amplifier circuit in which a1 st transistor, a source of which is grounded via a1 st source inductor and a gate of which an input signal is applied, and a 3 rd transistor, a gate of which is grounded, are connected in cascade, the 3 rd transistor outputting a signal obtained by amplifying a signal output from the drain of the 1 st transistor from the drain;

a 2 nd amplifier circuit in which a 2 nd transistor and a 4 th transistor having a grounded gate are cascade-connected, the 2 nd transistor having a source grounded via a 2 nd source inductor and a gate to which the input signal is applied, and the 4 th transistor having a drain from which a signal obtained by amplifying the signal output from the drain of the 2 nd transistor is output, and having the same circuit constant as the 1 st amplifier circuit; and

a noise figure improvement circuit, wherein the source of the 1 st transistor and the source of the 2 nd transistor are connected through a capacitor,

the high-frequency amplifier circuit includes: a single output mode in which the amplified signal is output from one of the 1 st amplifier circuit and the 2 nd amplifier circuit; and a split output mode in which the amplified signal is output from both of the 1 st amplifier circuit and the 2 nd amplifier circuit.

2. The high-frequency amplifier circuit according to claim 1, further comprising:

a1 st switch connected between the 1 st source inductor and the 1 st transistor, and turned on when the amplified signal is output from the 1 st amplifier circuit, and turned off when the amplified signal is not output from the 1 st amplifier circuit;

a 2 nd switch connected between the 2 nd source inductor and the 2 nd transistor, and turned on when the amplified signal is output from the 2 nd amplifier circuit and turned off when the amplified signal is not output from the 2 nd amplifier circuit,

the noise figure improvement circuit is connected between the 1 st transistor and the 1 st switch, and between the 2 nd transistor and the 2 nd switch.

3. The high-frequency amplifier circuit according to claim 1, further comprising:

a1 st switch connected between the 1 st source inductor and the 1 st transistor, and turned on when the amplified signal is output from the 1 st amplifier circuit, and turned off when the amplified signal is not output from the 1 st amplifier circuit;

a 2 nd switch connected between the 2 nd source inductor and the 2 nd transistor, and turned on when the amplified signal is output from the 2 nd amplifier circuit and turned off when the amplified signal is not output from the 2 nd amplifier circuit,

the noise figure improvement circuit is connected between the 1 st switch and the 1 st source inductor, and between the 2 nd switch and the 2 nd source inductor.

4. The high frequency amplification circuit according to claim 1,

the capacitor of the noise figure improvement circuit forms a noise transmission path for transmitting a noise voltage induced in the source of the 2 nd transistor to the gate of the 1 st transistor, and the capacitance value is set so that the phase of noise passing through the noise transmission path is shifted by 180 ° from the phase of noise not passing through the noise transmission path and transmitted to the gate of the 1 st transistor.

5. The high frequency amplification circuit according to claim 1,

the noise figure improvement circuit is enabled in the case of the branch output mode and disabled in the case of the single output mode.

6. The high frequency amplification circuit according to claim 5,

the noise figure improving circuit comprises a noise figure improving element, a1 st switch of the noise figure improving circuit, a 2 nd switch of the noise figure improving circuit,

the 1 st changeover switch of the noise figure improvement circuit is provided between the 1 st amplification circuit and the noise figure improvement element, and includes a transistor which is turned off in the 1 st single output mode and the 2 nd single output mode, is turned on in the shunt output mode, and is equal to the gate oxide film thickness, the gate length, and the threshold voltage of the 1 st transistor,

the 2 nd switch of the noise figure improvement circuit is provided between the 2 nd amplifier circuit and the noise figure improvement element, and includes a transistor which is turned off in the 1 st single output mode and the 2 nd single output mode, is turned on in the shunt output mode, and is equal to the gate oxide film thickness, the gate length, and the threshold voltage of the 2 nd transistor,

the noise figure improvement element is configured such that a difference between the noise figure in the split output mode and the noise figure in the 1 st single output mode or the 2 nd single output mode becomes smaller as compared with a case where the noise figure improvement element is not provided.

7. The high frequency amplification circuit according to claim 1,

also provided with an isolation improvement circuit which is provided with a circuit,

the isolation improvement circuit connects the drain of the 3 rd transistor and the drain of the 4 th transistor via a circuit in which a capacitor and a resistor are connected in series.

8. The high frequency amplification circuit according to claim 7,

the values of the admittances of the isolation improvement circuit are determined based on the values of the Y21 component of the admittance matrix of the circuit,

the circuit is that,

removing a circuit element connected to the drain of the 3 rd transistor,

Removing circuit elements connected to the drain of the 4 th transistor,

The drain of the 3 rd transistor is set as the 1 st port,

The drain of the 4 th transistor is set as the 2 nd port,

And a circuit in which an input of an input matching circuit provided on an input side of the 1 st transistor and the 2 nd transistor is grounded.

9. The high frequency amplification circuit according to claim 7,

the isolation improvement circuit is enabled in the case of the branch output mode and disabled in the case of the single output mode.

10. The high-frequency amplifier circuit according to claim 1, further comprising:

a1 st electrostatic discharge protection circuit provided between a node between a source of the 1 st transistor and the 1 st source inductor and a node on an input side of a capacitor connected between a gate of the 1 st transistor and an input terminal; and

and a 2 nd electrostatic discharge protection circuit provided between a node between the source of the 2 nd transistor and the 2 nd source inductor and a node on the input side of the capacitor.

11. The high-frequency amplifier circuit according to claim 1, further comprising:

the 1 st output matching circuit includes: a1 st output matching resistor and a1 st output matching inductor provided in parallel between the drain of the 3 rd transistor and a power supply voltage; and a1 st output matching capacitor connected in series to both the drain of the 3 rd transistor and the 1 st output matching resistor and the 1 st output matching inductor, and outputting the amplified signal from the drain of the 3 rd transistor via the 1 st output matching capacitor; and

the 2 nd output matching circuit includes: a 2 nd output matching resistor and a 2 nd output matching inductor provided in parallel between the drain of the 4 th transistor and a power supply voltage; and a 2 nd output matching capacitor connected in series to both the drain of the 4 th transistor and the 2 nd output matching resistor and the 2 nd output matching inductor, and outputting the amplified signal from the drain of the 4 th transistor through the 2 nd output matching capacitor.

12. The high-frequency amplifier circuit according to claim 1, further comprising:

a 5 th transistor having a source connected to the drain of the 3 rd transistor and a gate grounded; and

a 6 th transistor having a source connected to the drain of the 4 th transistor and a gate grounded,

the 1 st amplifier circuit outputs the amplified signal from the drain of the 5 th transistor,

the 2 nd amplifier circuit outputs the amplified signal from the drain of the 6 th transistor.

13. The high-frequency amplifier circuit according to claim 12, further comprising:

the 1 st output matching circuit includes: a1 st output matching resistor and a1 st output matching inductor provided in parallel between the drain of the 5 th transistor and a power supply voltage; and a1 st output matching capacitor connected in series to both the drain of the 5 th transistor and the 1 st output matching resistor and the 1 st output matching inductor, the amplified signal being output from the drain of the 5 th transistor via the 1 st output matching capacitor; and

the 2 nd output matching circuit includes: a 2 nd output matching resistor and a 2 nd output matching inductor provided in parallel between the drain of the 6 th transistor and a power supply voltage; and a 2 nd output matching capacitor connected in series to both the drain of the 6 th transistor and the 2 nd output matching resistor and the 2 nd output matching inductor, and outputting the amplified signal from the drain of the 6 th transistor through the 2 nd output matching capacitor.

14. A high-frequency amplification circuit is provided with:

a1 st amplifier circuit in which a1 st transistor, a source of which is grounded via a1 st source inductor and a gate of which an input signal is applied, and a 3 rd transistor, a gate of which is grounded, are connected in cascade, the 3 rd transistor outputting a signal obtained by amplifying a signal output from the drain of the 1 st transistor from the drain;

a 2 nd amplifier circuit in which a 2 nd transistor and a 4 th transistor having a grounded gate are cascade-connected, the 2 nd transistor having a source grounded via a 2 nd source inductor and a gate to which the input signal is applied, and the 4 th transistor having a drain from which a signal obtained by amplifying the signal output from the drain of the 2 nd transistor is output, and having the same circuit constant as the 1 st amplifier circuit; and

an isolation improvement circuit in which a drain of the 3 rd transistor and a drain of the 4 th transistor are connected to each other through a circuit in which a capacitor and a resistor are connected in series,

the high-frequency amplifier circuit includes: a single output mode in which the amplified signal is output from one of the 1 st amplifier circuit and the 2 nd amplifier circuit; and a split output mode in which the amplified signal is output from both of the 1 st amplifier circuit and the 2 nd amplifier circuit.

15. The high-frequency amplification circuit according to any one of claims 1 to 14, further comprising:

an SPnT switch, i.e., a single-pole n-throw switch, which selects signals of a plurality of frequencies and outputs the input signal; and

an input matching circuit for matching the input signals between the patterns.

16. A semiconductor device includes:

a plurality of high-frequency amplifier circuits disposed on an SOI substrate which is a silicon-on-insulator substrate; and

a high-frequency switch disposed on the SOI substrate so as to correspond to each of the plurality of high-frequency amplifier circuits, for selecting 1 of the plurality of high-frequency signals and supplying the selected signal to the corresponding high-frequency amplifier circuit,

at least one of the plurality of high-frequency amplifier circuits includes:

a1 st amplifier circuit in which a1 st transistor, a source of which is grounded via a1 st source inductor and a gate of which an input signal is applied, and a 3 rd transistor, a gate of which is grounded, are connected in cascade, the 3 rd transistor outputting a signal obtained by amplifying a signal output from the drain of the 1 st transistor from the drain;

a 2 nd amplifier circuit in which a 2 nd transistor and a 4 th transistor having a grounded gate are cascade-connected, the 2 nd transistor having a source grounded via a 2 nd source inductor and a gate to which the input signal is applied, and the 4 th transistor having a drain from which a signal obtained by amplifying the signal output from the drain of the 2 nd transistor is output, and having the same circuit constant as the 1 st amplifier circuit; and

a noise figure improvement circuit, wherein the source of the 1 st transistor and the source of the 2 nd transistor are connected through a capacitor,

at least one of the plurality of high-frequency amplifier circuits includes: a single output mode in which the amplified signal is output from one of the 1 st amplifier circuit and the 2 nd amplifier circuit; and a split output mode in which the amplified signal is output from both of the 1 st amplifier circuit and the 2 nd amplifier circuit.

Technical Field

Background

Low Noise Amplifiers (LNAs) generally use SiGe bipolar technology, but in recent years, many have been based on silicon-on-insulator (SOI) CMOS technology. This is because a high-performance circuit can be realized by incorporating a high-frequency switching FET into the LNA. In recent years, Carrier Aggregation (CA) has been introduced to increase the speed of wireless communication. In this case, the outputs of the LNAs need to be branched into 2, and in order to realize an LNA compatible with the in-band CA, a single output mode and a split (split) output mode are required as the output mode. However, the Isolation between outputs (Isolation) in the split output mode requires about 25dB, but it is not easy to realize the Isolation.

Disclosure of Invention

Drawings

Fig. 1 is a circuit diagram showing an example of an S23 improving circuit according to an embodiment.

Fig. 2 is a circuit diagram showing an example of a Δ NF improvement circuit according to an embodiment.

Fig. 3 is a circuit diagram showing an example of a Δ NF improvement circuit according to an embodiment.

Fig. 4 is a block diagram showing an example of an LNA according to an embodiment.

Fig. 5 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 6 is a diagram showing control signals in the circuit of fig. 5.

Fig. 7 is a diagram showing an S parameter in the single output mode of the circuit of fig. 5.

Fig. 8 is a diagram showing NF in the single output mode of the circuit of fig. 5.

Fig. 9 is a diagram showing an S parameter in the shunt output mode of the circuit of fig. 5.

Fig. 10 is a diagram showing NF in the shunt output mode of the circuit of fig. 5.

Fig. 11 is a diagram showing characteristics in the circuit of fig. 5.

Fig. 12 is a diagram showing characteristics in the case where the circuit of fig. 5 is not improved by S23.

Fig. 13 is a diagram showing characteristics in the case where the Δ NF improving circuit is not provided in the circuit of fig. 5.

Fig. 14 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 15 is a diagram showing an S parameter in the single output mode of the circuit of fig. 14.

Fig. 16 is a diagram showing NF in the single output mode of the circuit of fig. 14.

Fig. 17 is a diagram showing an S parameter in the shunt output mode of the circuit of fig. 14.

Fig. 18 is a diagram showing NF in the shunt output mode of the circuit of fig. 14.

Fig. 19 is a diagram showing characteristics in the circuit of fig. 14.

Fig. 20 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 21 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 22 is a diagram showing control signals in the circuit of fig. 21.

Fig. 23 is a diagram showing an S parameter in the single output mode of the circuit of fig. 21.

Fig. 24 is a diagram showing NF in the single output mode of the circuit of fig. 21.

Fig. 25 is a diagram showing an S parameter in the shunt output mode of the circuit of fig. 21.

Fig. 26 is a diagram showing NF in the shunt output mode of the circuit of fig. 21.

Fig. 27 is a diagram showing characteristics in the circuit of fig. 21.

Fig. 28 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 29 is a circuit diagram showing an example of the LNA according to the embodiment.

Fig. 30 is a diagram showing control signals in the circuit of fig. 29.

Fig. 31 is an explanatory diagram of an S23 improving circuit in the circuit of fig. 29.

Fig. 32 is a diagram showing an S parameter in the single output mode of the circuit of fig. 29.

Fig. 33 is a diagram showing NF in the single output mode of the circuit of fig. 29.

Fig. 34 is a diagram showing an S parameter in the shunt output mode of the circuit of fig. 29.

Fig. 35 is a diagram showing NF in the shunt output mode of the circuit of fig. 29.

Fig. 36 is a diagram showing characteristics in the circuit of fig. 29.

Fig. 37 is a diagram showing a comparison between the circuit of fig. 29 and a comparative example without the S23 improving circuit.

Fig. 38 is a circuit diagram showing an example of an LNA according to an embodiment.

The embodiment relates to a high-frequency amplifier circuit and a semiconductor device.