阅读说明：本技术 用于静态存储器功能检测的晶圆允收测试模块和方法 (Wafer acceptance test module and method for static memory function detection ) 是由 赖振安 陈俊晟 黄召颖 于 2019-10-31 设计创作，主要内容包括：本发明公开了一种用于静态存储器功能检测的晶圆允收测试模块,包括形成于晶圆上的精简指令内建自我测试电路,用于对静态存储器进行功能检测。精简指令内建自我测试电路包括：环形振荡器,分频器,计数器,数据锁存器和比较器。环形振荡器和分频器用于形成内部时钟信号。计数器用于计数,计数同时作为地址解码器和数据输入端口的输入信号；计数器的最高有效位作为读写控制信号。数据锁存器和比较器连接地址解码器的输出端和灵敏放大器的输出端并对两个输出信号进行比较从而得到测试结果。本发明还公开了一种用于静态存储器功能检测的晶圆允收测试方法。本发明不需依赖存储器的专用测试机台进行静态存储器功能检测,能简化测试程序。(The invention discloses a wafer acceptance test module for static memory function detection, which comprises a simplified instruction built-in self-test circuit formed on a wafer and used for performing function detection on a static memory. The simplified instruction built-in self-test circuit includes: a ring oscillator, a frequency divider, a counter, a data latch and a comparator. A ring oscillator and a frequency divider are used to form the internal clock signal. The counter is used for counting and simultaneously used as input signals of the address decoder and the data input port; the most significant bit of the counter is used as a read-write control signal. The data latch and the comparator are connected with the output end of the address decoder and the output end of the sensitive amplifier and compare the two output signals to obtain a test result. The invention also discloses a wafer acceptance test method for the function detection of the static memory. The invention does not need to rely on a special test machine of the memory to carry out the function detection of the static memory, and can simplify the test procedure.)

1. A wafer acceptance test module for static memory function testing, comprising: the wafer acceptance test module comprises a simplified instruction built-in self-test circuit formed on a wafer and composed of test patterns, wherein the simplified instruction built-in self-test circuit is used for carrying out function detection on a static memory formed on the wafer;

the static memory comprises a memory cell array, an address decoder, a data input port and a sensitive amplifier;

the simplified instruction built-in self-test circuit comprises: a ring oscillator, a frequency divider, a counter, a data latch and a comparator;

the simplified instruction built-in self-test circuit works under the direct current voltage provided by the wafer acceptance test equipment;

the ring oscillator and the frequency divider are used for forming an internal clock signal;

the counter is used for counting the internal clock signals, and the counting is simultaneously used as input signals of the address decoder and the data input port; the most significant bit of the counter is used as a read-write control signal;

the data latch and the comparator are connected with the output end of the address decoder and the output end of the sense amplifier, and the data latch and the comparator are used for comparing the output signal of the address decoder with the output signal of the sense amplifier and judging whether the test result is successful or failed according to the comparison result.

2. The wafer acceptance test module for static memory function testing of claim 1, wherein: the ring oscillator is formed by connecting an odd number of inverters end to end.

3. The wafer acceptance test module for static memory function testing of claim 1, wherein: the counter is formed by connecting n +1 bit triggers, the output signals of the 1 st to n bit triggers form n bit counts, and the output signals of the n +1 th bit triggers form the read-write control signals.

4. The wafer acceptance test module for static memory function testing of claim 3, wherein: the trigger adopts a D trigger.

5. The wafer acceptance test module for static memory function testing of claim 1, wherein: when the output of the data latch and the comparator indicates that the output signal of the address decoder is the same as the output signal of the sensitive amplifier, the test result is successful; and when the output of the data latch and the comparator indicates that the output signal of the address decoder is different from the output signal of the sensitive amplifier, the test result is failure.

6. The wafer acceptance test module for static memory function testing of claim 3, wherein: and when the output signal of the trigger at the (n + 1) th bit is 0, the read-write control signal is a write signal, the memory cell array is subjected to write operation under the control of the write signal, and in the write operation, the count is gradually increased from 0 and data which is the same as the count is sequentially written in the address which is the same as the count.

7. The wafer acceptance test module for static memory function testing of claim 6, wherein: and when the output signal of the n +1 th bit of the trigger is 1, the read-write control signal is a read signal, the memory cell array is read under the control of the read signal, in the read operation, the count is gradually increased from 0, and data in the address which is the same as the count is sequentially read through the sensitive amplifier.

8. The wafer acceptance test module for static memory function testing of claim 3, wherein: the number of memory cells in the memory cell array is less than or equal to 2ⁿ。

9. A wafer acceptance test method for static memory function detection is characterized in that: in the manufacturing process of a wafer, a step of forming a wafer acceptance test module on the wafer while forming a crystal memory on the wafer is also included, wherein the wafer acceptance test module comprises a simplified instruction built-in self-test circuit formed on the wafer and composed of test patterns, and the simplified instruction built-in self-test circuit is used for carrying out function detection on the static memory;

the static memory comprises a memory cell array, an address decoder, a data input port and a sensitive amplifier;

the simplified instruction built-in self-test circuit comprises: a ring oscillator, a frequency divider, a counter, a data latch and a comparator;

the simplified instruction built-in self-test circuit works under the direct current voltage provided by the wafer acceptance test equipment;

the ring oscillator and the frequency divider are used for forming an internal clock signal;

the counter is used for counting the internal clock signals, and the counting is simultaneously used as input signals of the address decoder and the data input port; the most significant bit of the counter is used as a read-write control signal;

the data latch and the comparator are connected with the output end of the address decoder and the output end of the sense amplifier, and the data latch and the comparator are used for comparing the output signal of the address decoder with the output signal of the sense amplifier and judging whether the test result is successful or failed according to the comparison result.

10. The wafer acceptance test method for static memory functional testing of claim 9, wherein: the ring oscillator is formed by connecting an odd number of inverters end to end.

11. The wafer acceptance test method for static memory functional testing of claim 9, wherein: the counter is formed by connecting n +1 bit triggers, the output signals of the 1 st to n bit triggers form n bit counts, and the output signals of the n +1 th bit triggers form the read-write control signals.

12. The wafer acceptance test method for static memory functional testing of claim 11, wherein: the trigger adopts a D trigger.

13. The wafer acceptance test method for static memory functional testing of claim 9, wherein: when the output of the data latch and the comparator indicates that the output signal of the address decoder is the same as the output signal of the sensitive amplifier, the test result is successful; and when the output of the data latch and the comparator indicates that the output signal of the address decoder is different from the output signal of the sensitive amplifier, the test result is failure.

14. The wafer acceptance test method for static memory functional testing of claim 11, wherein: and when the output signal of the trigger at the (n + 1) th bit is 0, the read-write control signal is a write signal, the memory cell array is subjected to write operation under the control of the write signal, and in the write operation, the count is gradually increased from 0 and data which is the same as the count is sequentially written in the address which is the same as the count.

15. The wafer acceptance test method for static memory functional testing of claim 14, wherein: and when the output signal of the n +1 th bit of the trigger is 1, the read-write control signal is a read signal, the memory cell array is read under the control of the read signal, in the read operation, the count is gradually increased from 0, and data in the address which is the same as the count is sequentially read through the sensitive amplifier.

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Wafer Acceptance Test (WAT) module for static memory function detection. The invention also relates to a wafer acceptance test method for the static memory function detection.

Background

Disclosure of Invention

The invention aims to provide a wafer acceptance test module for static memory function detection, which does not need to rely on a special test machine of a memory to carry out the static memory function detection, can simplify the test procedure of the static memory function detection, can realize simple and steady test, can reduce the cost of test equipment and can improve the test efficiency. The invention also provides a wafer acceptance test method for the function detection of the static memory.

In order to solve the above technical problem, the wafer acceptance test module for static memory function detection provided by the present invention includes a reduced instruction built-in self-test circuit formed on a wafer and composed of test patterns, where the reduced instruction built-in self-test circuit is used to perform function detection on a static memory formed on the wafer.

The static memory comprises a memory cell array, an address decoder, a data input port and a sensitive amplifier.

The simplified instruction built-in self-test circuit comprises: a ring oscillator, a frequency divider, a counter, a data latch and a comparator.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator and the frequency divider are used to form an internal clock signal.

The counter is used for counting the internal clock signals, and the counting is simultaneously used as input signals of the address decoder and the data input port; the most significant bit of the counter is used as a read-write control signal.

The data latch and the comparator are connected with the output end of the address decoder and the output end of the sense amplifier, and the data latch and the comparator are used for comparing the output signal of the address decoder with the output signal of the sense amplifier and judging whether the test result is successful or failed according to the comparison result.

In a further refinement, the ring oscillator is formed from an odd number of inverters connected end to end.

In a further improvement, the counter is formed by connecting n +1 bit flip-flops, n bits of the count are formed by output signals of the 1 st to n bits of the flip-flops, and the read-write control signal is formed by output signals of the n +1 th bit of the flip-flops.

In a further improvement, the flip-flop is a D flip-flop.

In a further refinement, the test result is successful when the outputs of the data latch and comparator indicate that the output signal of the address decoder and the output signal of the sense amplifier are the same; and when the output of the data latch and the comparator indicates that the output signal of the address decoder is different from the output signal of the sensitive amplifier, the test result is failure.

A further improvement is that when the output signal of the n +1 th bit of the flip-flop is 0, the read-write control signal is a write signal, and the memory cell array is subjected to write operation under the control of the write signal, wherein in the write operation, the count is gradually increased from 0 and data which is the same as the count is sequentially written in the same address as the count.

A further improvement is that when the output signal of the n +1 th bit of the flip-flop is 1, the read-write control signal is a read signal, and the memory cell array is read under the control of the read signal, wherein in the read operation, the count is gradually increased from 0 and data in the same address as the count is sequentially read through the sense amplifier.

In a further improvement, the number of memory cells in the memory cell array is less than or equal to 2ⁿ。

In order to solve the above technical problem, the wafer acceptance test method for static memory function inspection provided by the present invention comprises: in the manufacturing process of the wafer, a step of forming a wafer acceptance test module on the wafer is also included while forming a crystal memory on the wafer, wherein the wafer acceptance test module comprises a reduced instruction built-in self-test circuit formed on the wafer and composed of test patterns, and the reduced instruction built-in self-test circuit is used for carrying out function detection on the static memory.

The static memory comprises a memory cell array, an address decoder, a data input port and a sensitive amplifier.

The simplified instruction built-in self-test circuit comprises: a ring oscillator, a frequency divider, a counter, a data latch and a comparator.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator and the frequency divider are used to form an internal clock signal.

The counter is used for counting the internal clock signals, and the counting is simultaneously used as input signals of the address decoder and the data input port; the most significant bit of the counter is used as a read-write control signal.

The data latch and the comparator are connected with the output end of the address decoder and the output end of the sense amplifier, and the data latch and the comparator are used for comparing the output signal of the address decoder with the output signal of the sense amplifier and judging whether the test result is successful or failed according to the comparison result.

In a further refinement, the ring oscillator is formed from an odd number of inverters connected end to end.

In a further improvement, the counter is formed by connecting n +1 bit flip-flops, n bits of the count are formed by output signals of the 1 st to n bits of the flip-flops, and the read-write control signal is formed by output signals of the n +1 th bit of the flip-flops.

In a further improvement, the flip-flop is a D flip-flop.

In a further refinement, the test result is successful when the outputs of the data latch and comparator indicate that the output signal of the address decoder and the output signal of the sense amplifier are the same; and when the output of the data latch and the comparator indicates that the output signal of the address decoder is different from the output signal of the sensitive amplifier, the test result is failure.

A further improvement is that when the output signal of the n +1 th bit of the flip-flop is 0, the read-write control signal is a write signal, and the memory cell array is subjected to write operation under the control of the write signal, wherein in the write operation, the count is gradually increased from 0 and data which is the same as the count is sequentially written in the same address as the count.

A further improvement is that when the output signal of the n +1 th bit of the flip-flop is 1, the read-write control signal is a read signal, and the memory cell array is read under the control of the read signal, wherein in the read operation, the count is gradually increased from 0 and data in the same address as the count is sequentially read through the sense amplifier.

The invention can form a wafer acceptance test module for static memory function detection by arranging a simplified instruction built-in self-test circuit consisting of test patterns on a wafer, thereby directly adopting wafer acceptance test equipment which only can provide direct-current voltage to carry out function detection on the static memory, not depending on a special test machine of the memory to carry out the static memory function detection, simplifying the test procedure of the static memory function detection, realizing simple and steady test, reducing the cost of the test equipment, having simple circuit and steady operation, and improving the test efficiency.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a device connection diagram for prior art static memory function detection;

FIG. 2 is a block diagram of a wafer acceptance test module for static memory function testing according to an embodiment of the present invention;

FIG. 3 is a block diagram of a wafer acceptance test module for static memory function testing in accordance with a preferred embodiment of the present invention;

FIG. 4 is a diagram illustrating read/write control of the wafer acceptance test module for static memory function testing according to the preferred embodiment of the invention.

Detailed Description

FIG. 2 is a block diagram of a wafer acceptance test module for static memory function testing according to an embodiment of the present invention; the wafer acceptance test module for static memory function detection in the embodiment of the invention comprises a simplified instruction built-in self-test circuit formed on a wafer 1 and composed of test patterns, wherein the simplified instruction built-in self-test circuit is used for performing function detection on a static memory formed on the wafer 1.

The static memory comprises a memory cell array 2, an address decoder 3, a data input port 4 and a sensitive amplifier 5.

The simplified instruction built-in self-test circuit comprises: a ring oscillator 8, a frequency divider 9, a counter 10, a data latch and a comparator 7. The circuit arrangement in which the ring oscillator 8, the frequency divider 9 and the counter 10 are combined is designated individually by reference numeral 6.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator 8 and the frequency divider 9 are used to form an internal clock signal CLK.

The counter 10 is used for counting the internal clock signal CLK, and the counting is simultaneously used as input signals of the address decoder 3 and the data input port 4; the most significant bit of the counter 10 serves as a read/write Control signal R/W Control.

The data latch and comparator 7 is connected to the output end of the address decoder 3 and the output end of the sense amplifier 5, and the data latch and comparator 7 is used for comparing the output signal of the address decoder 3 with the output signal of the sense amplifier 5 and judging whether the test result is successful or failed according to the comparison result.

In the embodiment of the invention, the wafer acceptance test module for static memory function detection can be formed by arranging the simplified instruction built-in self-test circuit consisting of the test patterns on the wafer 1, so that the wafer acceptance test equipment which can only provide direct-current voltage can be directly adopted to carry out the function detection on the static memory, a special test machine of the memory is not needed to carry out the function detection on the static memory, the test program for the function detection of the static memory can be simplified, the simple and steady test can be realized, the cost of the test equipment can be reduced, and the circuit is simple and can operate steadily.

FIG. 4 is a block diagram of a wafer acceptance test module for static memory function testing according to a preferred embodiment of the present invention; the preferred embodiment of the present invention is further improved based on the embodiment of the present invention shown in fig. 3, and the preferred embodiment of the present invention further has the following features:

the ring oscillator 8 is formed by an odd number of inverters 11 connected end to end.

The counter 10 is formed by connecting n +1 bit flip-flops 12, the output signals of the 1 st to n bit flip-flops 12 form n bit count, and the output signals of the n +1 th bit flip-flops 12 form the read-write control signal R/WControl.

The flip-flop 12 is a D flip-flop.

In fig. 4, n is the output signal of the flip-flop 12 forming n bits of the address signals a1, a2 to An to the address decoder 3 and n is the data signals D1, D2 to Dn to the data input port 4, respectively.

In fig. 4, the signal diagram shown by the symbol 11 shows a timing diagram of data output by the first 4 flip-flops 12, D1 is an output signal of the Q terminal of the first flip-flop 12, D2 is an output signal of the Q terminal of the second flip-flop 12, D3 is an output signal of the Q terminal of the third flip-flop 12, and D4 is an output signal of the Q terminal of the fourth flip-flop 12, and it can be seen that the periods of the signals D1 to D4 are sequentially doubled, the signal D1 is the lowest bit, and the signal D4 is the highest bit, so that the signals D1 to D4 can represent 32 counts from 0 to 31, and then the counts become 0 again from 32.

When the output of the data latch and comparator 7 indicates that the output signal of the address decoder 3 and the output signal of the sense amplifier 5 are the same, the test result is successful; when the output of the data latch and comparator 7 indicates that the output signal of the address decoder 3 and the output signal of the sense amplifier 5 are not the same, the test result is a failure.

When the output signal of the n +1 th bit of the flip-flop 12 is 0, the read-write Control signal R/W Control is a write signal, and a write operation is performed on the memory cell array 2 under the Control of the write signal, where in the write operation, the count is gradually increased from 0 and data identical to the count is sequentially written in an address identical to the count.

When the output signal of the n +1 th bit flip-flop 12 is 1, the read-write Control signal R/W Control is a read signal, and the memory cell array 2 is read under the Control of the read signal, in the read operation, the count is gradually increased from 0, and the data in the address same as the count is sequentially read by the sense amplifier 5.

The number of memory cells in the memory cell array 2 is 2 or lessⁿ。

Fig. 4 is a schematic diagram illustrating read/write control of a wafer acceptance test module for static memory function detection according to a preferred embodiment of the present invention, the circuit structure diagram in fig. 4 still adopts the modular structure shown in fig. 2, where n is 2 in fig. 4, and the memory cell array 2 includes 4 memory cells as an example for description:

since n is 2, it is necessary to complete the test of all the memory cells of the memory cell array 2 by 2 in total⁽ⁿ⁺¹⁾Namely 8 clock cycles, the address is 2-bit address, 4 in total; the data also has 4 values. As shown in Table one below, the 1 st to 4 th clock cycles are all write operations, and the operation sequence is: starting from address 00, the next address is address 01, the next address is address 10, and the last address is address 11, and the writing operation sequence is indicated by arrows in fig. 4, and the data and addresses written in the addresses are the same.

The 5 th to 8 th clock cycles are all read operations, and the read operation sequence and the write operation sequence are the same.

As can be seen from the above, when the test as table one is implemented, the counter 10 needs to adopt 3 bits of the flip-flop 12 in total, and the first two bits of the flip-flop 12 are used for outputting the count and sequentially outputting the values required by the four addresses and data from 00 to 11; the output signal of the 3 rd bit of the trigger 12 is used as a read-write Control signal R/W Control, and if the output signal of the 3 rd bit of the trigger 12 is 0, the write operation is realized; and when the output signal of the 3 rd bit flip-flop 12 is 1, the read operation is realized.

The simplified instruction built-in self-test circuit comprises: a ring oscillator 8, a frequency divider 9, a counter 10, a data latch and a comparator 7. The circuit arrangement in which the ring oscillator 8, the frequency divider 9 and the counter 10 are combined is designated individually by reference numeral 6.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator 8 and the frequency divider 9 are used to form an internal clock signal CLK.

The counter 10 is used for counting the internal clock signal CLK, and the counting is simultaneously used as input signals of the address decoder 3 and the data input port 4; the most significant bit of the counter 10 serves as a read/write Control signal R/W Control.

Watch 1

Clock period	Address	Operation of	Data of
				1	00	Writing	00
2	01	Writing	01
				3	10	Writing	10
4	11	Writing	11
				5	00	Reading	00
6	01	Reading	01
				7	10	Reading	10
8	11	Reading	11

The wafer acceptance test method for the function detection of the static memory in the embodiment of the invention comprises the following steps: in the manufacturing process of the wafer 1, a step of forming a wafer acceptance test module on the wafer 1 while forming a crystal memory on the wafer 1 is also included, the wafer acceptance test module includes a reduced instruction built-in self-test circuit formed on the wafer 1 and composed of test patterns, and the reduced instruction built-in self-test circuit is used for performing function detection on the static memory.

As shown in fig. 2, the static memory includes a memory cell array 2, an address decoder 3, a data input port 4, and a sense amplifier 5.

The simplified instruction built-in self-test circuit comprises: a ring oscillator 8, a frequency divider 9, a counter 10, a data latch and a comparator 7. The circuit arrangement in which the ring oscillator 8, the frequency divider 9 and the counter 10 are combined is designated individually by reference numeral 6.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator 8 and the frequency divider 9 are used to form an internal clock signal CLK.

The counter 10 is used for counting the internal clock signal CLK, and the counting is simultaneously used as input signals of the address decoder 3 and the data input port 4; the most significant bit of the counter 10 serves as a read/write Control signal R/W Control.

The data latch and comparator 7 is connected to the output end of the address decoder 3 and the output end of the sense amplifier 5, and the data latch and comparator 7 is used for comparing the output signal of the address decoder 3 with the output signal of the sense amplifier 5 and judging whether the test result is successful or failed according to the comparison result.

The method of the preferred embodiment of the present invention also has the following features:

the ring oscillator 8 is formed by an odd number of inverters 11 connected end to end.

The counter 10 is formed by connecting n +1 bit flip-flops 12, the output signals of the 1 st to n bit flip-flops 12 form n bit count, and the output signals of the n +1 th bit flip-flops 12 form the read-write control signal R/WControl.

The flip-flop 12 is a D flip-flop.

In fig. 4, the signal diagram shown by the symbol 11 shows a timing diagram of data output by the first 4 flip-flops 12, D1 is an output signal of the Q terminal of the first flip-flop 12, D2 is an output signal of the Q terminal of the second flip-flop 12, D3 is an output signal of the Q terminal of the third flip-flop 12, and D4 is an output signal of the Q terminal of the fourth flip-flop 12, and it can be seen that the periods of the signals D1 to D4 are sequentially doubled, the signal D1 is the lowest bit, and the signal D4 is the highest bit, so that the signals D1 to D4 can represent 32 counts from 0 to 31, and then the counts become 0 again from 32.

When the output of the data latch and comparator 7 indicates that the output signal of the address decoder 3 and the output signal of the sense amplifier 5 are the same, the test result is successful; when the output of the data latch and comparator 7 indicates that the output signal of the address decoder 3 and the output signal of the sense amplifier 5 are not the same, the test result is a failure.

When the output signal of the n +1 th bit of the flip-flop 12 is 0, the read-write Control signal R/W Control is a write signal, and a write operation is performed on the memory cell array 2 under the Control of the write signal, where in the write operation, the count is gradually increased from 0 and data identical to the count is sequentially written in an address identical to the count.

When the output signal of the n +1 th bit flip-flop 12 is 1, the read-write Control signal R/W Control is a read signal, and the memory cell array 2 is read under the Control of the read signal, in the read operation, the count is gradually increased from 0, and the data in the address same as the count is sequentially read by the sense amplifier 5.

The number of memory cells in the memory cell array 2 is 2 or lessⁿ。

Fig. 4 is a schematic diagram of read/write control in a wafer acceptance test method for static memory function detection according to a preferred embodiment of the present invention, the circuit structure diagram in fig. 4 still adopts the modular structure shown in fig. 2, where n is 2 in fig. 4, and the memory cell array 2 includes 4 memory cells as an example for description:

since n is 2, it is necessary to complete the test of all the memory cells of the memory cell array 2 by 2 in total⁽ⁿ⁺¹⁾Namely 8 clock cycles, the address is 2-bit address, 4 in total; the data also has 4 values. As shown in Table one above, the 1 st to 4 th clock cycles are all write operations, and the operation sequence is: starting from address 00, the next address is address 01, the next address is address 10, and the last address is address 11, and the writing operation sequence is indicated by arrows in fig. 4, and the data and addresses written in the addresses are the same.

The 5 th to 8 th clock cycles are all read operations, and the read operation sequence and the write operation sequence are the same.

As can be seen from the above, when the test as table one is implemented, the counter 10 needs to adopt 3 bits of the flip-flop 12 in total, and the first two bits of the flip-flop 12 are used for outputting the count and sequentially outputting the values required by the four addresses and data from 00 to 11; the output signal of the 3 rd bit of the trigger 12 is used as a read-write Control signal R/W Control, and if the output signal of the 3 rd bit of the trigger 12 is 0, the write operation is realized; and when the output signal of the 3 rd bit flip-flop 12 is 1, the read operation is realized.

The simplified instruction built-in self-test circuit comprises: a ring oscillator 8, a frequency divider 9, a counter 10, a data latch and a comparator 7. The circuit arrangement in which the ring oscillator 8, the frequency divider 9 and the counter 10 are combined is designated individually by reference numeral 6.

The reduced instruction built-in self-test circuit operates at a DC voltage provided by wafer acceptance test equipment.

The ring oscillator 8 and the frequency divider 9 are used to form an internal clock signal CLK.

The counter 10 is used for counting the internal clock signal CLK, and the counting is simultaneously used as input signals of the address decoder 3 and the data input port 4; the most significant bit of the counter 10 serves as a read/write Control signal R/W Control.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.