阅读说明：本技术 基于延迟门控正反馈的高速动态多米诺全加器 (High-speed dynamic domino full adder based on delay gating positive feedback ) 是由 汪鹏君 张笑天 张会红 张跃军 俞海珍 于 2019-10-14 设计创作，主要内容包括：本发明公开了一种基于延迟门控正反馈的高速动态多米诺全加器,包括第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管、第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第九PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第五NMOS管、第六NMOS管、第七NMOS管、第八NMOS管、第九NMOS管、第十NMOS管、第十一NMOS管、第一反相器、第二反相器、第三反相器和第四反相器；优点是减少正反馈的阻碍作用,从而减少了亚稳态时反相器上拉网络与下拉网络同时弱导通的时长,不仅提升了速度性能,也降低了整体功耗,不但具有较快的运行速度,而且具有较低功耗。(The invention discloses a high-speed dynamic domino full adder based on delay gating positive feedback, which comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter and a fourth phase inverter; the method has the advantages that the blocking effect of positive feedback is reduced, so that the time length of the simultaneous weak conduction of the pull-up network and the pull-down network of the phase inverter in a metastable state is reduced, the speed performance is improved, the overall power consumption is reduced, and the method not only has higher operation speed, but also has lower power consumption.)

1. A high-speed dynamic domino full adder based on delay gate control positive feedback is characterized by comprising a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first inverter, a second inverter, a third inverter and a fourth inverter, wherein a source electrode of the first PMOS tube, a source electrode of the second PMOS tube, a source electrode of the fourth PMOS tube, a source electrode of the fifth PMOS tube, a source electrode of the seventh PMOS tube and a source electrode of the eighth PMOS tube are connected, a connection end of the high-speed dynamic domino full adder is used for external access to a power supply end of the high-speed dynamic domino full adder, the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the seventh PMOS tube, the grid electrode of the eleventh NMOS tube and the input end of the second phase inverter are connected, and the connection end of the connection end is the clock end of the high-speed dynamic domino full adder, the clock end of the high-speed dynamic domino full adder is used for accessing an external clock signal, the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the third PMOS tube are connected with the input end of the first phase inverter, the grid electrode of the second PMOS tube, the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the seventh NMOS tube are connected, and the connection end of the grid electrode of the second PMOS tube, the source electrode of the second NMOS tube and the grid electrode of the third NMOS tube is the first input end of the high-speed dynamic domino full adder, the first input end of the high-speed dynamic domino full adder is used for accessing a first addend signal. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate of the second NMOS transistor, the source of the third NMOS transistor and the gate of the eighth NMOS transistor are connected, and the connection end thereof is the second input end of the high-speed dynamic domino full adder, the second input end of the high-speed dynamic domino full adder is used for accessing a second addend signal, the drain of the fourth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the seventh NMOS transistor and the input end of the third inverter are connected, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the fifth PMOS transistor and the output end of the third inverter are connected, and the connection end thereof is the high-order carry signal output end of the high-order dynamic domino full adder, the high-speed dynamic domino full adder is characterized in that a high carry signal output end of the high-speed dynamic domino full adder is used for outputting carry signals to a high position, a grid electrode of a sixth PMOS tube is connected with an output end of a second phase inverter, a drain electrode of a seventh PMOS tube, a drain electrode of an eleventh NMOS tube, a drain electrode of a ninth PMOS tube are connected with an input end of a fourth phase inverter, a drain electrode of an eighth PMOS tube is connected with a source electrode of the ninth PMOS tube, a grid electrode of the eighth PMOS tube, a grid electrode of a fifth NMOS tube, a grid electrode of a ninth NMOS tube and a source electrode of the tenth NMOS tube are connected, a connecting end of the connecting end is a low carry signal input end of the high-speed dynamic domino full adder, a low carry signal input end of the high-speed dynamic domino full adder is used for accessing low carry signals, and a grid electrode of the ninth PMOS tube, a source electrode of the ninth NMOS tube, a drain electrode of the eleventh NMOS tube, a drain electrode of the ninth NMOS tube and, The grid electrode of the tenth NMOS tube and the grid electrode of the sixth NMOS tube are connected with the output end of the first phase inverter, the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected, the drain electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube and the source electrode of the eighth NMOS tube are connected, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the seventh NMOS transistor is connected with the drain electrode of the eighth NMOS transistor, the drain electrodes of the ninth NMOS transistor and the tenth NMOS transistor are connected with the source electrode of the eleventh NMOS transistor, the output end of the fourth inverter is the sum signal output end of the high-speed dynamic domino full adder, and the sum signal output end of the high-speed dynamic domino full adder is used for outputting a sum signal.

Technical Field

The invention relates to a high-speed dynamic domino full adder, in particular to a high-speed dynamic domino full adder based on delay gating positive feedback.

Background

Addition is a widely used basic arithmetic operation. In the design of digital circuit systems such as specific digital signal processing architectures and microprocessors, the performance of the full adder will have a decisive influence on the overall system performance. Compared with CMOS logic, dynamic domino logic has obvious advantages in speed and area overhead due to its non-complementary structure and dynamic operating characteristics. Digital circuits using dynamic domino logic designs suffer from noise margins due to negative effects such as sub-threshold leakage and charge sharing. At present, the charge is supplemented by positive feedback to improve the noise tolerance of such digital circuits. At the same time, however, positive feedback prevents such circuits from changing states, thereby limiting further improvements in speed performance of such circuits.

In document 1(Meher P, Mahapatra K K.A High Speed Low Noise CMOS Dynamic full Adder Cell [ C ]. IEEE International Conference on Circuits,2014:1-4.) Meher P et al propose a half-domino logic adder, which is improved based on Dynamic domino logic, improving the Speed performance of a full adder circuit, but leading to the increase of the static power consumption of the full adder. In order to suppress the static power consumption of a full adder, a reduced swing output dynamic Domino adder is proposed by Ahn S Y in document 2(Ahn S Y, Cho k. small-swing Domino Logic Based on two-connected transistors [ J ]. Electronics Letters,2014,50(15):1054-1056.), although the reduced swing output dynamic Domino adder can suppress the static power consumption, the reduced swing output dynamic Domino adder has poor driving capability during pre-charge and Logic operation due to the addition of a diode-connected transistor, so that the inter-stage circuit signal transmission current is weak, and finally the speed performance is affected. Lian X et al in document 3(Lian X, Wey I C, Peng C, et al, dynamic-static Hybrid Near-Threshold-voltageadadder Design for deep-Low Power Applications [ J ]. IEICE Electron Express,2015,12(3):20141122.) propose a dynamic-static Hybrid adder that consumes less Power, but with too many transistors stacked in a pull-down network that also results in slow circuit speed. Therefore, the existing full adders have not been improved in speed and power consumption comprehensively.

Disclosure of Invention

The invention aims to provide a high-speed dynamic domino full adder which has higher running speed and lower power consumption and is based on delay gating positive feedback.

The technical scheme adopted by the invention for solving the technical problems is as follows: a high-speed dynamic domino full adder based on delay gate control positive feedback comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a first phase inverter, a second phase inverter, a third phase inverter and a fourth phase inverter, wherein the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the seventh PMOS tube and the source electrode of the eighth PMOS tube are connected, the connection end of the high-speed dynamic domino full adder is used for external access of a power supply, the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube, the grid electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the seventh PMOS tube, the grid electrode of the eleventh NMOS tube and the input end of the second phase inverter are connected, and the connection end of the connection end is the clock end of the high-speed dynamic domino full adder, the clock end of the high-speed dynamic domino full adder is used for accessing an external clock signal, the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the drain electrode of the third PMOS tube are connected with the input end of the first phase inverter, the grid electrode of the second PMOS tube, the source electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the seventh NMOS tube are connected, and the connection end of the grid electrode of the second PMOS tube, the source electrode of the second NMOS tube and the grid electrode of the third NMOS tube is the first input end of the high-speed dynamic domino full adder, the first input end of the high-speed dynamic domino full adder is used for accessing a first addend signal. The drain of the second PMOS transistor is connected to the source of the third PMOS transistor, the gate of the second NMOS transistor, the source of the third NMOS transistor and the gate of the eighth NMOS transistor are connected, and the connection end thereof is the second input end of the high-speed dynamic domino full adder, the second input end of the high-speed dynamic domino full adder is used for accessing a second addend signal, the drain of the fourth PMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth PMOS transistor, the drain of the seventh NMOS transistor and the input end of the third inverter are connected, the drain of the fifth PMOS transistor is connected to the source of the sixth PMOS transistor, the gate of the fifth PMOS transistor and the output end of the third inverter are connected, and the connection end thereof is the high-order carry signal output end of the high-order dynamic domino full adder, the high-speed dynamic domino full adder is characterized in that a high carry signal output end of the high-speed dynamic domino full adder is used for outputting carry signals to a high position, a grid electrode of a sixth PMOS tube is connected with an output end of a second phase inverter, a drain electrode of a seventh PMOS tube, a drain electrode of an eleventh NMOS tube, a drain electrode of a ninth PMOS tube are connected with an input end of a fourth phase inverter, a drain electrode of an eighth PMOS tube is connected with a source electrode of the ninth PMOS tube, a grid electrode of the eighth PMOS tube, a grid electrode of a fifth NMOS tube, a grid electrode of a ninth NMOS tube and a source electrode of the tenth NMOS tube are connected, a connecting end of the connecting end is a low carry signal input end of the high-speed dynamic domino full adder, a low carry signal input end of the high-speed dynamic domino full adder is used for accessing low carry signals, and a grid electrode of the ninth PMOS tube, a source electrode of the ninth NMOS tube, a drain electrode of the eleventh NMOS tube, a drain electrode of the ninth NMOS tube and, The grid electrode of the tenth NMOS tube and the grid electrode of the sixth NMOS tube are connected with the output end of the first phase inverter, the source electrode of the first NMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected, the drain electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube and the source electrode of the eighth NMOS tube are connected, the source electrode of the fourth NMOS tube is grounded, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the seventh NMOS transistor is connected with the drain electrode of the eighth NMOS transistor, the drain electrodes of the ninth NMOS transistor and the tenth NMOS transistor are connected with the source electrode of the eleventh NMOS transistor, the output end of the fourth inverter is the sum signal output end of the high-speed dynamic domino full adder, and the sum signal output end of the high-speed dynamic domino full adder is used for outputting a sum signal.

Compared with the prior art, the high-speed dynamic domino full adder has the advantages that the high-speed dynamic domino full adder is constructed by the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, the sixth NMOS tube, the seventh NMOS tube, the eighth NMOS tube, the ninth NMOS tube, the tenth NMOS tube, the eleventh NMOS tube, the first inverter, the second inverter, the third inverter and the fourth inverter, when a clock signal CLK is low level 0, a full adder circuit is in a pre-charging state, the first PMOS tube, the fourth PMOS tube and the seventh PMOS tube are started, a dynamic node X1 (a connection node of a drain electrode of the first PMOS tube, a drain electrode of the first NMOS tube, a drain electrode of the third PMOS tube and an input end of the first inverter), and a dynamic node X2 (a drain electrode of the fourth PMOS tube), A drain electrode of a fifth NMOS transistor, a drain electrode of a sixth PMOS transistor, a connection node of a drain electrode of a seventh NMOS transistor and an input terminal of a third inverter), and a dynamic node X3 (a connection node of a drain electrode of a seventh PMOS transistor, a drain electrode of an eleventh NMOS transistor, a drain electrode of a ninth PMOS transistor and an input terminal of a fourth inverter) are charged to a high level "1" through the first PMOS transistor, the fourth PMOS transistor and the seventh PMOS transistor, respectively, at which time the first input signal a, the second input signal B and the low carry signal Cin, and the signal Sum and the high carry signal Cout will be output a low level "0" through the fourth inverter and the third inverter, when the clock signal CLK is a high level "1", the first PMOS transistor, the fourth PMOS transistor and the seventh PMOS transistor are turned off, while the first NMOS transistor, the fourth NMOS transistor and the eleventh NMOS transistor are turned on, according to input logics of the first input signal a, the second input signal B and the low carry signal Cin, the dynamic nodes X1, X2 and X3 discharge to low level '0' selectively through the pull-down network to complete the logical operation of addition and carry, in the process of logical calculation, the second NMOS tube and the third NMOS tube, the ninth NMOS tube and the tenth NMOS tube form the pull-down network in a cross coupling mode, the number of transistors is reduced to reduce the equivalent resistance of the pull-down network, the second PMOS tube and the third PMOS tube, the first phase inverter, the eighth PMOS tube and the ninth PMOS tube, and the fourth phase inverter respectively form a selective feedback network, the stability of the circuit is improved under the condition of not influencing the speed performance of the full adder, the fifth PMOS tube and the sixth PMOS tube, and the second phase inverter and the third phase inverter form a reverse delay clock gating feedback network to reduce the blocking effect of positive feedback, thereby reducing the weak time of the simultaneous conduction of the pull-up network and the pull-down network of the phase inverter in a metastable state, the invention not only improves the speed performance, but also reduces the overall power consumption, thereby having higher running speed and lower power consumption.

Drawings

FIG. 1 is a circuit diagram of a high-speed dynamic domino full adder based on delay-gated positive feedback according to the present invention;

FIG. 2 is a waveform diagram illustrating the functional simulation of the high-speed dynamic domino full adder based on delay-gated positive feedback according to the present invention;

FIG. 3 is a waveform diagram illustrating a critical path simulation of the high-speed dynamic domino full adder based on delay-gated positive feedback according to the present invention;

FIG. 4 is a graph comparing pull-down speed simulation for a high-speed dynamic domino full adder based on delayed gating positive feedback according to the present invention with a conventional full adder;

FIG. 5 is a graph comparing the power consumption delay product of the high speed dynamic domino full adder based on delay gated positive feedback of the present invention with that of the four prior art full adders;

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.