阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 藤井光太郎 永嶋贤史 中嶋由美 于 2019-02-14 设计创作，主要内容包括：本发明的实施方式提供一种能够提升可靠性的半导体存储装置。实施方式的半导体存储装置包含第1配线层(46)、与第1配线层相邻地配置的第2配线层(46)、设置在第1配线层与第2配线层之间的第1半导体层(31_2)、设置在第1配线层与第2配线层之间的第2半导体层(31_3)、设置在第1半导体层与第2半导体层之间且与第1半导体层及第2半导体层分别相接的第1绝缘层(30)、设置在第1及第2半导体层以及第1绝缘层上的第3半导体层(31B)、设置在第1配线层与第2配线层之间且与第1绝缘层相接的第2绝缘层(49)、设置在第1配线层与第1半导体层之间的第1电荷储存层(33)以及设置在第2配线层与第2半导体层之间的第2电荷储存层(33)。(Embodiments of the invention provide a semiconductor memory device capable of improving reliability. The semiconductor memory device of the embodiment comprises a1 st wiring layer (46), a2 nd wiring layer (46) arranged adjacent to the 1 st wiring layer, a1 st semiconductor layer (31_2) arranged between the 1 st wiring layer and the 2 nd wiring layer, and a2 nd semiconductor layer (31_3) arranged between the 1 st wiring layer and the 2 nd wiring layer, the semiconductor device includes a1 st insulating layer (30) provided between the 1 st semiconductor layer and the 2 nd semiconductor layer and in contact with the 1 st semiconductor layer and the 2 nd semiconductor layer, respectively, a 3 rd semiconductor layer (31B) provided on the 1 st and the 2 nd semiconductor layers and the 1 st insulating layer, a2 nd insulating layer (49) provided between the 1 st wiring layer and the 2 nd wiring layer and in contact with the 1 st insulating layer, a1 st charge storage layer (33) provided between the 1 st wiring layer and the 1 st semiconductor layer, and a2 nd charge storage layer (33) provided between the 2 nd wiring layer and the 2 nd semiconductor layer.)

1. A semiconductor memory device includes:

a semiconductor substrate;

a1 st wiring layer provided above the semiconductor substrate and extending in a1 st direction parallel to the semiconductor substrate;

a2 nd wiring layer which is arranged adjacent to the 1 st wiring layer in a2 nd direction parallel to the semiconductor substrate and intersecting the 1 st direction, and which extends in the 1 st direction;

a1 st semiconductor layer provided between the 1 st wiring layer and the 2 nd wiring layer and extending in a 3 rd direction perpendicular to the semiconductor substrate;

a2 nd semiconductor layer provided between the 1 st wiring layer and the 2 nd wiring layer and extending in the 3 rd direction;

a1 st insulating layer provided between the 1 st semiconductor layer and the 2 nd semiconductor layer, in contact with the 1 st semiconductor layer and the 2 nd semiconductor layer, respectively, and extending in the 3 rd direction;

a 3 rd semiconductor layer provided on the 1 st and 2 nd semiconductor layers and the 1 st insulating layer;

a2 nd insulating layer provided between the 1 st wiring layer and the 2 nd wiring layer, in contact with the 1 st insulating layer, and extending in the 2 nd direction;

a1 st charge storage layer provided between the 1 st wiring layer and the 1 st semiconductor layer; and

and a2 nd charge storage layer disposed between the 2 nd wiring layer and the 2 nd semiconductor layer.

2. The semiconductor memory device according to claim 1, wherein the 1 st charge storage layer is opposed to the 1 st wiring layer in the 2 nd direction, and the 2 nd charge storage layer is opposed to the 2 nd wiring layer in the 2 nd direction.

3. The semiconductor memory device according to claim 1 or 2, further comprising:

a 3 rd wiring layer provided above the semiconductor substrate and below the 1 st and 2 nd wiring layers and the 2 nd insulating layer;

a 4 th semiconductor layer surrounding the 1 st insulating layer in the 3 rd wiring layer and having an upper surface in contact with the 1 st and 2 nd semiconductor layers; and

a gate insulating film provided between the 3 rd wiring layer and the 4 th semiconductor layer; and is

The gate insulating film includes the same material as the 1 st and 2 nd charge storage layers.

4. The semiconductor storage device according to claim 1 or 2, wherein

An air gap is disposed within the 2 nd insulating layer.

5. The semiconductor memory device according to claim 1 or 2, further comprising:

a1 st memory cell including a part of the 1 st wiring layer and a part of the 1 st semiconductor layer; and

and a2 nd memory cell including a part of the 2 nd wiring layer and a part of the 2 nd semiconductor layer.

6. The semiconductor memory device according to claim 1 or 2, further comprising:

a 4 th wiring layer disposed above the 1 st wiring layer and extending in the 1 st direction;

a 5 th wiring layer provided above the 2 nd wiring layer, disposed adjacent to the 4 th wiring layer in the 2 nd direction, and extending in the 1 st direction;

a 3 rd charge storage layer disposed between the 4 th wiring layer and the 1 st semiconductor layer; and

a 4 th charge storage layer provided between the 5 th wiring layer and the 2 nd semiconductor layer; and is

The 1 st insulating layer has a protrusion protruding in the 1 st and 2 nd directions above the 1 st wiring layer and below the 4 th wiring layer.

Technical Field

Embodiments of the present invention relate to a semiconductor memory device.

Background

As a semiconductor memory device, a NAND (Not AND) type flash memory is known.

Disclosure of Invention

Drawings

Fig. 1 is a block diagram of a semiconductor memory device according to embodiment 1.

Fig. 2 is a circuit diagram of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 3 is a plan view of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 4 is a sectional view taken along line B1-B2 in fig. 3.

Fig. 5 is a sectional view taken along line a1-a2 in fig. 3.

Fig. 6 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 7 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 8 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 9 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 10 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 11 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 12 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 13 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 14 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 15 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 16 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 17 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 18 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 19 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 20 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 21 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 1.

Fig. 22 is a cross-sectional view B1 through B2 of the memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 23 is a sectional view a1-a2 of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 24 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 25 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 26 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 27 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 28 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 29 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 30 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 31 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 32 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 33 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 34 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 35 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 36 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 2.

Fig. 37 is a sectional view B1-B2 of the memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 38 is a sectional view a1-a2 of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 39 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 40 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 41 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 42 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 43 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 44 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 45 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 46 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 47 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 48 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 49 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 50 is a view showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 51 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 52 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 53 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 54 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Fig. 55 is a diagram showing a manufacturing process of a memory cell array included in the semiconductor memory device according to embodiment 3.

Embodiments provide a semiconductor memory device capable of improving reliability.