阅读说明：本技术 熔断器测试电路及方法、集成电路 (Fuse test circuit and method, and integrated circuit ) 是由 不公告发明人 于 2018-09-07 设计创作，主要内容包括：本公开是关于熔断器测试电路及方法、集成电路,该熔断器测试电路包括熔断器和闩锁电路,闩锁电路,和所述熔断器连接,所述闩锁电路具有信号接收端,所述信号接收端用于接收触发信号,使得所述闩锁电路中的电流增大,能够将熔断器熔断。在熔断多个熔断器时,只需触发一个熔断器对应的闩锁电路即可接着触发另一个熔断器对应的闩锁电路,避免了相关技术中需要等待一个熔断器熔断接着熔断另一个熔断器,导致的测试时间长,测试效率低的问题。(The fuse test circuit comprises a fuse, a latch circuit and an integrated circuit, wherein the latch circuit is connected with the fuse, the latch circuit is provided with a signal receiving end, and the signal receiving end is used for receiving a trigger signal, so that the current in the latch circuit is increased, and the fuse can be fused. When a plurality of fuses are blown, the latch circuit corresponding to one fuse can be triggered to trigger the latch circuit corresponding to the other fuse, so that the problems that in the related art, one fuse needs to be waited to be blown and then another fuse is blown, the testing time is long, and the testing efficiency is low are solved.)

1. A fuse test circuit, comprising:

a fuse;

a latch circuit connected to the fuse, the latch circuit having a signal receiving end for receiving a trigger signal such that a current in the latch circuit increases.

2. The fuse test circuit of claim 1, wherein the latch circuit comprises:

the first parasitic transistor is provided with a first emitter and a second emitter which receive a first power supply signal, a collector which receives a second power supply signal, and a base which receives a first trigger signal;

and the collector of the second parasitic transistor is connected with the base of the first parasitic transistor, the collector receives the first power supply signal, the base of the second parasitic transistor is connected with the collector of the first parasitic transistor, the base of the second parasitic transistor receives the second trigger signal, and the first emitter and the second emitter of the second parasitic transistor receive the second power supply signal.

3. The fuse test circuit of claim 2, wherein the fuse is connected at the first emitter of the first parasitic transistor.

4. The fuse test circuit of claim 2, wherein the fuse is connected to the second emitter of the first parasitic transistor.

5. The fuse test circuit of claim 2, wherein the fuse is connected at the first emitter of the second parasitic transistor.

6. The fuse test circuit of claim 2, wherein the fuse is connected to the second emitter of the second parasitic transistor.

7. The fuse test circuit of claim 1, wherein the latch circuit comprises:

a third parasitic transistor, an emitter of which receives the first power supply signal, a collector of which receives the second power supply signal, and a base of which receives the first trigger signal;

and the collector of the fourth parasitic transistor is connected with the base of the third parasitic transistor, the collector receives the first power supply signal, the base of the fourth parasitic transistor is connected with the collector of the third parasitic transistor, the base of the fourth parasitic transistor receives the second trigger signal, and the emitter of the fourth parasitic transistor receives the second power supply signal.

8. The fuse test circuit of claim 7, wherein the fuse is connected at an emitter of the third parasitic transistor.

9. The fuse test circuit of claim 7, wherein the fuse is connected at an emitter of the fourth parasitic transistor.

10. A fuse test circuit as claimed in any one of claims 1 to 9, wherein the fuse test circuit comprises:

the fuse is connected with latch circuit respectively, the fuse forms the detecting element with the latch circuit who is connected with it, the one end of detecting element is connected with the high level, and the other end is connected with the low level, and is a plurality of the detecting element is parallelly connected.

11. A fuse testing method, comprising:

the latch circuit receives a trigger signal;

the latch circuit outputs fusing current;

the fusing current flows through the fuse, fusing the fuse.

12. The test method of claim 11, further comprising:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.

13. An integrated circuit comprising the fuse test circuit of any of claims 1 to 10.

Technical Field

The disclosure relates to the technical field of integrated circuits, in particular to a fuse testing circuit and method and an integrated circuit.

Background

With the development and progress of the technology, the application of the integrated circuit is more and more extensive, and the integrated circuit needs to be tested when the integrated circuit is designed and manufactured.

When the integrated circuit is tested, the fuse in the integrated circuit is often required to be tested, and at present, when the integrated circuit is tested, if a plurality of fuses are required to be tested, one fuse is generally required to be blown, and then the next fuse is blown. The whole testing process consumes more time and has low testing efficiency.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a fuse testing circuit and method and an integrated circuit, and further solves the problems that in the related technology, the testing process is time-consuming and the testing efficiency is low during fuse testing at least to a certain extent.

According to a first aspect of the present disclosure, there is provided a fuse test circuit comprising:

a fuse;

a latch circuit connected to the fuse, the latch circuit having a signal receiving end for receiving a trigger signal such that a current in the latch circuit increases.

According to an embodiment of the present disclosure, the latch circuit includes:

the first parasitic transistor is provided with a first emitter and a second emitter which receive a first power supply signal, a collector which receives a second power supply signal, and a base which receives a first trigger signal;

and the collector of the second parasitic transistor is connected with the base of the first parasitic transistor, the collector receives the first power supply signal, the base of the second parasitic transistor is connected with the collector of the first parasitic transistor, the base of the second parasitic transistor receives the second trigger signal, and the first emitter and the second emitter of the second parasitic transistor receive the second power supply signal.

According to an embodiment of the present disclosure, the fuse is connected to a first emitter of the first parasitic transistor.

According to an embodiment of the present disclosure, the fuse is connected to the second emitter of the first parasitic transistor.

According to an embodiment of the present disclosure, the fuse is connected to a first emitter of the second parasitic transistor.

According to an embodiment of the present disclosure, the fuse is connected to the second emitter of the second parasitic transistor.

According to an embodiment of the present disclosure, the latch circuit includes:

a third parasitic transistor, an emitter of which receives the first power supply signal, a collector of which receives the second power supply signal, and a base of which receives the first trigger signal;

and the collector of the fourth parasitic transistor is connected with the base of the third parasitic transistor, the collector receives the first power supply signal, the base of the fourth parasitic transistor is connected with the collector of the third parasitic transistor, the base of the fourth parasitic transistor receives the second trigger signal, and the emitter of the fourth parasitic transistor receives the second power supply signal.

According to an embodiment of the present disclosure, the fuse is connected to an emitter of the third parasitic transistor.

According to an embodiment of the present disclosure, the fuse is connected to an emitter of the fourth parasitic transistor.

According to an embodiment of the present disclosure, the fuse test circuit includes:

the fuse is connected with latch circuit respectively, the fuse forms the detecting element with the latch circuit who is connected with it, the one end of detecting element is connected with first power, and the other end is connected with the second power, and is a plurality of the detecting element is parallelly connected.

According to a second aspect of the present disclosure, there is provided a fuse testing method, including:

the latch circuit receives a trigger signal;

the latch circuit outputs fusing current;

the fusing current flows through the fuse, fusing the fuse.

According to an embodiment of the present disclosure, the testing method further includes:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.

According to a third aspect of the present disclosure, there is provided an integrated circuit comprising the fuse test circuit provided by the present disclosure.

The present disclosure provides a fuse test circuit, connect fuse and latch circuit, receive trigger signal through the signal receiving terminal on the latch circuit, current in the latch circuit increases gradually when the latch circuit is triggered, can fuse the fuse. When a plurality of fuses are blown, the latch circuit corresponding to one fuse can be triggered to trigger the latch circuit corresponding to the other fuse, so that the problems that in the related art, one fuse needs to be waited to be blown and then another fuse is blown, the testing time is long, and the testing efficiency is low are solved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

FIG. 1 is a schematic diagram of a first fuse test circuit provided by an exemplary embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a CMOS device according to an exemplary embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a second fuse test circuit provided by an exemplary embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a third fuse test circuit provided by an exemplary embodiment of the present disclosure;

FIG. 5 is a circuit diagram of a fourth fuse test circuit provided by an exemplary embodiment of the present disclosure;

FIG. 6 is a circuit diagram of a fifth fuse test circuit provided by an exemplary embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of another CMOS device provided in an exemplary embodiment of the present disclosure;

FIG. 8 is a circuit diagram of a sixth fuse test circuit provided in an exemplary embodiment of the present disclosure;

fig. 9 is a circuit diagram of a seventh fuse test circuit provided in an exemplary embodiment of the present disclosure.

FIG. 10 is a diagram of a first latch circuit trigger signal provided by an exemplary embodiment of the present disclosure;

FIG. 11 is a diagram of a second latch circuit trigger signal provided by an exemplary embodiment of the present disclosure;

FIG. 12 is a diagram of third latch circuit trigger signals provided by an exemplary embodiment of the present disclosure;

FIG. 13 is a diagram of fourth latch circuit trigger signals provided by an exemplary embodiment of the present disclosure;

FIG. 14 is a flowchart of a fuse testing method provided by an exemplary embodiment of the present disclosure.

FIG. 15 is a flow chart of another fuse testing method provided by exemplary embodiments of the present disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.

Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.

The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.

First, in the present exemplary embodiment, there is provided a fuse test circuit, as shown in fig. 1, which includes a fuse Fu and a latch circuit LC;

the latch circuit LC is connected to the fuse Fu, and the latch circuit LC has a signal receiving terminal for receiving a trigger signal, so that a current in the latch circuit LC increases.

The fuse Fu may be a fuse disposed in the integrated circuit, such as a fuse. The latch circuit LC may be generated by a latch effect of the CMOS device, and the signal receiving terminal of the latch circuit LC may be a plurality of receiving terminals that receive the trigger signal, so that a current in the latch circuit LC is increased, and a fuse Fu connected to the latch circuit LC is blown.

The utility model provides a fuse test circuit, connect fuse Fu and latch circuit LC, receive trigger signal through the signal receiving terminal on the latch circuit LC, the electric current in the latch circuit LC crescent when the latch circuit LC is triggered, can fuse the fuse Fu. When fusing a plurality of fuses Fu, only need trigger the latch circuit LC that one fuse Fu corresponds and can trigger the latch circuit LC that another fuse Fu corresponds next, avoided needing to wait for one fuse fusing Fu and then fusing another fuse Fu among the correlation technique, the test time that leads to is long, problem that efficiency of software testing is low.

Further, the fuse test circuit that this disclosed embodiment provided can include a plurality of fuses, and a plurality of fuses are connected with latch circuit respectively, and the fuse forms the detecting element with the latch circuit who is connected with it, and the one end of detecting element is connected with first power, and the other end is connected with the second power, and a plurality of detecting element are parallelly connected. The plurality of parallel detection units can trigger the latch circuit in turn during the detection process. In the latch circuit, when the latch circuit is triggered, the current in the latch circuit is gradually increased until the fuse is blown. Therefore, only the latch circuit needs to be triggered during detection. Because the triggering time of the latch circuit is less than the fusing time of the fuse, the testing time is saved, and the testing efficiency is improved.

The following describes the fuse test circuit provided in the embodiments of the present disclosure in detail:

in one possible embodiment of the present disclosure, as shown in fig. 3, the latch circuit LC may include a first parasitic transistor Q1 and a second parasitic transistor Q2;

the first emitter and the second emitter of the first parasitic transistor Q1 receive a first power signal, the collector receives a second power signal, and the base receives a first trigger signal; a second parasitic transistor Q2 having a collector connected to the base of the first parasitic transistor Q1, the collector receiving the first power signal, a base connected to the collector of the first parasitic transistor Q1, the base receiving the second trigger signal, and a first emitter and a second emitter receiving the second power signal. The first power signal may be high and the second power signal may be low.

Wherein the first parasitic transistor Q1 and the second parasitic transistor Q2 are both parasitic transistors in cmos devices, the first parasitic transistor Q1 and the second parasitic transistor Q2 may be created by a structure as shown in fig. 2. As shown in fig. 2, the CMOS includes a substrate Su, an NMOS and a PMOS are disposed on the substrate Su, the NMOS includes a P-type silicon substrate Su with a lower doping concentration, i.e., a P-well PW shown in the figure, and two heavily doped N + regions and one heavily doped P + region are fabricated on the P-well PW. The PMOS includes an N-type silicon substrate Su with a low doping concentration, i.e., an N-well NW as shown in the figure, and two heavily doped P + regions and one heavily doped N + region are formed on the N-well NW.

In the CMOS, a first parasitic transistor Q1 and a second parasitic transistor Q2 are formed due to latch-up effect, a first emitter and a second emitter of the first parasitic transistor Q1 are connected with high level, a collector is connected with low level, and a base receives a first trigger signal; the collector of the second parasitic transistor Q2 is connected to the base of the first transistor, the collector is connected to high level, the base is connected to the collector of the first parasitic transistor Q1, the base receives the second trigger signal, and the first emitter and the second emitter are connected to low level, forming a latch circuit LC. In the latch circuit LC, the current in the latch circuit LC gradually increases after receiving the trigger signal.

The first emitter of the first parasitic transistor Q1 corresponds to the source of the PMOS in the cmos, and the second emitter of the first parasitic transistor Q1 corresponds to the drain of the PMOS in the cmos. The first emitter of the second parasitic transistor Q2 corresponds to the source of an NMOS in COMS, and the second emitter of the second parasitic transistor Q2 corresponds to the drain of an NMOS in COMS.

Fig. 3 is an equivalent circuit diagram of the parasitic circuit of fig. 2 connected to a fuse Fu, and as shown in fig. 3, the fuse Fu may be connected to the first emitter of the first parasitic transistor Q1, one end of the fuse Fu is connected to the first emitter of the first parasitic transistor Q1, and the other end is connected to a power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of the PMOS. When the latch-up effect of the CMOS is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, thereby finally blowing the fuse Fu.

Fig. 4 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 2, and the fuse Fu may be connected to the second emitter of the first parasitic transistor Q1, as shown in fig. 4. One end of the fuse Fu is connected to the second emitter of the first parasitic transistor Q1, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the drain of the PMOS. When the latch-up effect of the CMOS is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, thereby finally blowing the fuse Fu.

Fig. 5 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 2, and the fuse Fu may be connected to the first emitter of the second parasitic transistor Q2, as shown in fig. 5. One end of the fuse Fu is connected to the first emitter of the second parasitic transistor Q2, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the source of the NMOS. When the latch-up effect of the CMOS is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, thereby finally blowing the fuse Fu.

Fig. 6 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 2, and the fuse Fu may be connected to the second emitter of the second parasitic transistor Q2, as shown in fig. 6. One end of the fuse Fu is connected to the second emitter of the second parasitic transistor Q2, and the other end is connected to the power supply. Correspondingly, in CMOS, the fuse Fu is connected to the drain of the NMOS. When the latch-up effect of the CMOS is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, thereby finally blowing the fuse Fu.

In another possible embodiment of the present disclosure, as shown in fig. 8, the latch circuit LC may include: a third parasitic transistor Q3 and a fourth parasitic transistor Q4.

The emitter of the third parasitic transistor Q3 receives the first power signal, the collector receives the second power signal, and the base receives the first trigger signal; the fourth parasitic transistor Q4 has a collector connected to the base of the third parasitic transistor Q3, the collector receiving the first power signal, a base connected to the collector of the third parasitic transistor Q3, the base receiving the second trigger signal, and the emitter receiving the second power signal.

The third parasitic transistor Q3 and the fourth parasitic transistor Q4 may be produced by a structure as shown in fig. 7, which includes a substrate Su having an N-type region and a P-type region, i.e., an N-well NW and a P-well PW, formed thereon, the N-well NW being heavily doped with P + and N +, and the P-well PW being heavily doped with P + and N +, as shown in fig. 7. A third parasitic transistor Q3 and a fourth parasitic transistor Q4 are formed on the structure, wherein the emitter of the third parasitic transistor Q3 is connected with high level, the collector is connected with low level, and the base receives the first trigger signal; the fourth parasitic transistor Q4 has a collector connected to the base of the third transistor, a collector connected to a high level, a base connected to the collector of the first parasitic transistor Q1, a base receiving the second trigger signal, and an emitter connected to a low level, forming a latch circuit LC. In the latch circuit LC, the current in the latch circuit LC gradually increases after receiving the trigger signal.

Fig. 8 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 7, and the fuse Fu may be connected to the emitter of the third parasitic transistor Q3, as shown in fig. 8. One end of the fuse Fu is connected to the emitter of the third parasitic transistor Q3, and the other end is connected to the power supply. Correspondingly, a P + terminal on the N-type region. When the latch-up is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, so as to finally fuse the fuse Fu.

Fig. 9 is an equivalent circuit diagram of the parasitic circuit and the fuse Fu in fig. 7, and the fuse Fu may be connected to the emitter of the fourth parasitic transistor Q4, as shown in fig. 9. One end of the fuse Fu is connected to the emitter of the fourth parasitic transistor Q4, and the other end is connected to the power supply. Correspondingly, the N + end on the P-type region. When the latch-up is triggered, the current in the latch circuit LC continuously increases, and the current flowing through the fuse Fu also continuously increases, so as to finally fuse the fuse Fu.

As shown in the fuse Fu test circuit of fig. 3 to 6, the latch circuit LC signal receiving terminal may include a plurality of receiving terminals, for example, four receiving terminals as shown in the figure, wherein the first receiving terminal G1 is disposed at the base of the second parasitic transistor Q2, the second receiving terminal G2 is disposed at the base of the first parasitic transistor Q1, the third receiving terminal G3 is disposed at the high-level terminal, and the fourth receiving terminal G4 is disposed at the low-level terminal. In the fuse Fu test circuit shown in fig. 8 and 9, among the signal receiving terminals of the latch circuit LC, the first receiving terminal G1 is provided at the base of the fourth parasitic transistor Q4, the second receiving terminal G2 is provided at the base of the third parasitic transistor Q3, the third receiving terminal G3 is provided at the high-level terminal, and the fourth receiving terminal G4 is provided at the low-level terminal.

According to the fuse Fu test circuit provided by the embodiment of the disclosure, after the latch effect is triggered, the current in the latch circuit LC is continuously increased, the fuse Fu is fused, and the latch circuit LC can be triggered in the following manner.

In a first possible implementation manner provided by the embodiment of the present disclosure, as shown in fig. 10, an overshoot signal is input at the first receiving terminal G1, the emitter-base forward bias of the second parasitic transistor Q2 is provided, and a current is fed back to the first parasitic transistor Q1, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form a positive feedback, and the current increases until the fuse Fu is blown.

In a second possible embodiment of the present disclosure, as shown in fig. 11, an undershoot signal is input at the second receiving terminal G2, the emitter-base of the first parasitic transistor Q1 is forward biased, and a current is fed back to the second parasitic transistor Q2, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form a positive feedback, and the current increases until the fuse Fu is blown.

In a third possible embodiment of the present disclosure, as shown in fig. 12, an overshoot signal is input at the third receiving terminal G3, the emitter-base forward bias of the first parasitic transistor Q1 is forward biased, and a current is fed back to the second parasitic transistor Q2, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form a positive feedback, and the current increases until the fuse Fu is blown.

In a fourth possible embodiment of the present disclosure, as shown in fig. 13, an undershoot signal is input at the fourth receiving terminal G4, the emitter-base forward bias of the second parasitic transistor Q2 is provided, and a current is fed back to the first parasitic transistor Q1, so that the first parasitic transistor Q1 and the second parasitic transistor Q2 are turned on. The first parasitic transistor Q1 and the second parasitic transistor Q2 form a positive feedback, and the current increases until the fuse Fu is blown.

There is also provided in this exemplary embodiment a fuse testing method, as shown in fig. 14, including the steps of:

step S1, the latch circuit receives the trigger signal;

step S2, the latch circuit outputs fusing current;

in step S3, the blowing current flows through the fuse, blowing the fuse.

By triggering the latch effect of the latch circuit, the fusing current output by the latch circuit is continuously increased, so that the fuse is rapidly fused, and the detection time is saved. When a plurality of fuses are detected, the fuses can be guaranteed only by sequentially triggering the latch circuits, the condition that the fuses of another fuse are blown after the current fuse is blown in the related technology is avoided, the detection time is saved, and the detection efficiency is improved.

Optionally, as shown in fig. 15, after step S3, the method for detecting a fuse of an integrated circuit chip according to the embodiment of the present disclosure may further include:

step S4, detecting whether the fuse is blown;

step S5, if the fuse is fused, outputting a first signal;

and step S6, if the fuse is not fused, outputting a second signal.

In step S4, whether the fuse is blown or not may be detected by a disconnection detecting means, such as a latch circuit or the like; in step S5, if the fuse is blown, the entire circuit is opened, and the disconnection detecting means outputs a first signal indicating that the fuse has been blown; in step S6, if the fuse is blown, a second signal is output, and the second signal indicates that the fuse is defective or that the circuit is faulty.

Whether the fuse is fused or not is detected, the first signal is output when the fuse is fused, and the second signal is output when the fuse is not fused, so that the fuse test result is convenient to obtain, and the problem that the test result of the fuse cannot be directly obtained because the fuse is located inside an integrated circuit chip is avoided.

The integrated circuit is further provided in the example implementation manner, and the integrated circuit comprises the fuse testing circuit provided by the embodiment of the disclosure. In practical applications, the integrated circuit may further include elements such as a capacitor, a resistor, and other transistors, which are all the prior art and are not repeated herein.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.