阅读说明：本技术 集成电路芯片及熔断器的测试方法 (Integrated circuit chip and fuse testing method ) 是由 不公告发明人 于 2018-09-07 设计创作，主要内容包括：本公开是关于一种集成电路芯片及熔断器的测试方法,包括：衬底、多层导电层、介电层、熔断器和闩锁电路；其中,相邻的所述导电层之间设置有介电层,所述衬底和与其相邻的导电层之间设置有介电层,所述介电层上设置有接触孔；熔断器位于第一导电层上,所述第一导电层为多层所述导电层中位于最上层的导电层,其中,靠近所述衬底为底层,远离所述衬底为上层；闩锁电路设置在衬底上,和所述熔断器连接。在集成电路芯片测试时,触发闩锁效应,使得闩锁电路中的电流不断增大,直至烧断熔断器,实现了对熔断器测试时的熔断。并且在测试多个熔断器时,只需顺序触发每个熔断器的闩锁电路即可,提升了测试效率,节约了测试时间。(The present disclosure relates to a method for testing an integrated circuit chip and a fuse, comprising: a substrate, a plurality of conductive layers, a dielectric layer, a fuse, and a latch circuit; a dielectric layer is arranged between the adjacent conducting layers, a dielectric layer is arranged between the substrate and the conducting layer adjacent to the substrate, and a contact hole is formed in the dielectric layer; the fuse is positioned on a first conducting layer, the first conducting layer is the conducting layer positioned on the uppermost layer in the multiple conducting layers, the conducting layer is the bottom layer close to the substrate, and the conducting layer is the upper layer far away from the substrate; a latch circuit is disposed on the substrate and connected to the fuse. When the integrated circuit chip is tested, the latch effect is triggered, so that the current in the latch circuit is continuously increased until the fuse is blown, and the fuse is blown during the test of the fuse. And when testing a plurality of fuses, only need the latch circuit of order triggering every fuse can, promoted efficiency of software testing, practiced thrift test time.)

1. An integrated circuit chip, comprising:

a substrate;

the multilayer conducting layer is provided with a dielectric layer between the adjacent conducting layers, a dielectric layer is arranged between the substrate and the conducting layer adjacent to the substrate, and a contact hole is formed in the dielectric layer;

the fuse is positioned on a first conducting layer, the first conducting layer is the conducting layer positioned on the uppermost layer in the multiple conducting layers, the conducting layer is the bottom layer close to the substrate, and the conducting layer is the upper layer far away from the substrate;

and a latch circuit disposed in the substrate and connected to the fuse.

2. The integrated circuit chip of claim 1, wherein the first conductive layer has a first via disposed thereon, the fuse being located in the via.

3. The integrated circuit chip of claim 2, wherein the integrated circuit chip further comprises:

and the connector is positioned in the contact hole of the dielectric layer and is used for connecting the conducting layers on two sides of the dielectric layer.

4. The integrated circuit chip of claim 1, wherein the first conductive layer is for connection to a power supply for receiving a power supply signal.

5. The integrated circuit chip of claim 1, wherein a disconnection detection device is coupled to the second conductive layer, the disconnection detection device being configured to detect whether the fuse is blown, the second conductive layer being a conductive layer located between the first conductive layer and the substrate.

6. The integrated circuit chip of claim 1, wherein the fuse is a metal fuse.

7. The integrated circuit chip of claim 1, wherein a plurality of said conductive layers and said substrate are disposed parallel to each other.

8. The integrated circuit chip of claim 1, wherein the fuse is a fuse having a resistance greater than a resistance of the first conductive layer and a resistance of the connector.

9. The integrated circuit chip of claim 8, wherein a width of the fuse is less than a width of the first conductive layer.

10. The integrated circuit chip of claim 8, wherein a thickness of the fuse is less than a thickness of the first conductive layer.

11. The integrated circuit chip of any of claims 1-10, wherein the integrated circuit chip further comprises:

and the passivation layer is positioned on one side of the first conducting layer far away from the substrate.

12. A method of testing an integrated circuit chip fuse, comprising:

triggering the latch effect of the latch circuit and outputting fusing current;

the fusing current flows through the connector, the conductive layer and the fuse, fusing the fuse.

13. The test method of claim 12, further comprising:

detecting whether the fuse is blown;

if the fuse is fused, outputting a first signal;

and if the fuse is not fused, outputting a second signal.