阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 不公告发明人 于 2018-09-10 设计创作，主要内容包括：本发明提供了一种半导体器件,衬底中形成有定义出有源区的沟槽隔离结构,所述衬底上形成有栅电极,所述栅电极位于所述有源区上并延伸至所述沟槽隔离结构,所述栅电极在所述有源区及所述沟槽隔离结构的交界处具有凸出部,以使所述栅电极在所述交界处的横向宽度尺寸大于所述栅电极位于所述有源区中心区域上的横向宽度尺寸,进而增加了所述交界处的沟道区域的长度,降低了导通电流,能够抑制沟槽隔离结构俘获电子所带来的效应,从而提升器件的性能,且所述凸出部的横向宽度尺寸从所述交界处往所述有源区中心的方向逐渐减小,在增加所述交界处的沟道区域的长度的同时,导通电流不至于下降的太多,从而对器件的导通性能影响较小。(The invention provides a semiconductor device, a trench isolation structure defining an active region is formed in a substrate, a gate electrode is formed on the substrate, the gate electrode is positioned on the active region and extends to the trench isolation structure, a protruding part is arranged at the junction of the active region and the trench isolation structure, so that the transverse width dimension of the gate electrode at the junction is larger than that of the gate electrode at the central region of the active region, the length of a channel region at the junction is further increased, the conduction current is reduced, the effect brought by electron capture of the trench isolation structure can be inhibited, the performance of the device is improved, the transverse width dimension of the protruding part is gradually reduced from the junction to the center of the active region, and while the length of the channel region at the junction is increased, the on-current does not drop too much, and thus the on-performance of the device is less affected.)

1. A semiconductor device, comprising:

the semiconductor device comprises a substrate, a plurality of trench isolation structures and a plurality of active regions, wherein the trench isolation structures define the active regions; and the number of the first and second groups,

the gate electrode is provided with a transverse protruding part at the junction of the active region and the trench isolation structure, the transverse protruding direction of the protruding part is perpendicular to the extending direction of the gate electrode, so that the transverse width dimension of the gate electrode at the junction is larger than that of the gate electrode in the middle area of the active region, and the transverse width dimension of the protruding part is gradually reduced from the junction to the center of the active region.

2. The semiconductor device according to claim 1, wherein an active region and a drain region are formed in the active region, and both the active region and the drain region extend to a boundary of the active region in a direction parallel to an extension direction of the gate electrode, the gate electrode is located between the active region and the drain region to constitute a transistor, a length of a channel region of the transistor near the boundary is longer than a length of a channel region of the transistor in a middle region of the active region, and the length of the channel region of the transistor near the boundary is gradually reduced from the boundary toward a center of the active region.

3. The semiconductor device of claim 2, wherein the protrusion further extends into the active region and into the trench isolation structure at the interface such that the protrusion is partially on the active region and partially on the trench isolation structure.

4. The semiconductor device according to claim 1, wherein a side wall of the projection is inclined or stepped.

5. The semiconductor device according to claim 4, wherein a sidewall of the projection forms a step of 2 to 5 steps.

6. The semiconductor device according to claim 1, wherein a width dimension of the projection in parallel with an extending direction of the gate electrode is between 30nm and 140 nm.

7. The semiconductor device of claim 6, wherein a lateral width dimension of the protrusion is between 20nm-100 nm.

8. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is applied to an integrated circuit memory, the integrated circuit memory including a plurality of transistors.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device.

Background

Conventional MOS transistors generally employ a planar gate structure, and the gate structure of the transistor and the trench isolation structure have a cross section, but since the transistor is in operation, electrons migrate from the source region to the drain region, and since the trench isolation structure also has the capability of capturing high-energy electrons, the device generates a "kink" effect, a bimodal I-V curve, or a hot electron induced punch-through (HEIP) effect, etc., which results in the performance degradation of the device.

Disclosure of Invention

The invention aims to provide a semiconductor device to solve the problems of performance reduction and the like of the device caused by a trench isolation structure.

In order to achieve the above object, the present invention provides a semiconductor device comprising:

the semiconductor device comprises a substrate, a plurality of trench isolation structures and a plurality of active regions, wherein the trench isolation structures define the active regions; and the number of the first and second groups,

the gate electrode is provided with a transverse protruding part at the junction of the active region and the trench isolation structure, the transverse protruding direction of the protruding part is perpendicular to the extending direction of the gate electrode, so that the transverse width dimension of the gate electrode at the junction is larger than that of the gate electrode in the middle area of the active region, and the transverse width dimension of the protruding part is gradually reduced from the junction to the center of the active region.

Optionally, an active region and a drain region are formed in the active region, and both the active region and the drain region extend to a boundary of the active region in a direction parallel to an extension direction of the gate electrode, the gate electrode is located between the active region and the drain region to form a transistor, a length of a channel region of the transistor at the active region near the boundary is greater than a length of a channel region of the transistor at a middle region of the active region, and the length of the channel region of the transistor at the active region near the boundary gradually decreases from the boundary toward a center of the active region.

Optionally, the protrusion further extends into the active region and the trench isolation structure at the boundary, so that the protrusion is partially located on the active region and the other part is located on the trench isolation structure.

Optionally, the side wall of the protrusion is inclined or stepped.

Optionally, the side wall of the protrusion forms a step of 2-5 steps.

Optionally, a width dimension of the protrusion in a direction parallel to an extension direction of the gate electrode is between 30nm and 140 nm.

Optionally, the lateral width dimension of the protrusion is between 20nm and 100 nm.

Optionally, the semiconductor device is applied to an integrated circuit memory, and the integrated circuit memory comprises a plurality of transistors.

The semiconductor device provided by the invention comprises a substrate, wherein a trench isolation structure defining an active region is formed in the substrate, a gate electrode is formed on the substrate, the gate electrode is positioned on the active region and extends to the trench isolation structure, a protruding part is arranged at the junction of the active region and the trench isolation structure, so that the transverse width dimension of the gate electrode at the junction is larger than that of the gate electrode at the central region of the active region, the length of a channel region at the junction is further increased, the conduction current is reduced, the capability of the trench isolation structure for capturing electrons is inhibited, the performance of the device is improved, the transverse width dimension of the protruding part is gradually reduced from the junction to the center of the active region, and the length of the channel region at the junction is increased, the on-current does not drop too much, and thus the on-performance of the device is less affected.

Drawings

Fig. 1 is a schematic structural diagram of a first semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1 according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a second semiconductor device according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a third semiconductor device according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a fourth semiconductor device according to an embodiment of the present invention;

in the figures, the reference numbers are:

1-a substrate; 11-trench isolation structures; 12-an active region; a 111-source region; 112-a drain region;

2-a gate electrode; 21-a projection;

the transverse width dimension of the H-gate electrode at the junction of the active region and the trench isolation structure;

h' -the lateral width dimension of the gate electrode in the central region of the active region;

h-the width dimension of the projection along the extension direction of the gate electrode;

h' -the transverse width dimension of the projection.

Detailed Description

The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 1 to fig. 2 are schematic structural views of a semiconductor device provided in this embodiment, the semiconductor device including: the semiconductor device comprises a substrate 1, wherein a plurality of trench isolation structures 11 are formed in the substrate 1, and active regions 12 are defined by the trench isolation structures 11; and a gate electrode 2 formed on the active region 12 and extending to the trench isolation structure 11, wherein the gate electrode 2 has a laterally protruding protrusion 21 at a boundary between the active region 12 and the trench isolation structure 11, and a lateral protruding direction of the protrusion 21 is perpendicular to an extending direction of the gate electrode, so that a lateral width dimension H of the gate electrode 2 at the boundary is greater than a lateral width dimension H 'of the gate electrode 2 in a middle region of the active region 12, and a lateral width dimension H' of the protrusion 21 gradually decreases from the boundary toward a center of the active region 12.

Specifically, referring to fig. 2, a trench isolation structure 11 and an active region 12 are formed in the substrate 1, the trench isolation structure 11 is used for isolating the adjacent active regions 12, the active region 12 includes a source region 111 and a drain region 112, the source region 111 and the drain region 112 both extend to the boundary of the active region 12 in the extending direction parallel to the gate electrode 2, a region between the source region 111 and the drain region 112 forms a channel region, a gate structure is formed above the channel region, and the source region 111 and the drain region 112 are arranged on two sides of the gate structure to form a transistor. The gate structure includes a gate electrode 2 and an isolation layer surrounding the gate electrode, as shown in fig. 1, the gate electrode 2 is strip-shaped, and the gate electrode 2 is located on the active region 12 and extends to the trench isolation structure 11. Further, the active regions 12 are arranged in the substrate 1 in an array, and each column of the active regions 12 intersects with the same gate electrode 2. It is understood that the material of the projection 21 in the present embodiment is the same as the material of the gate electrode 2, the height of the projection 21 is the same as the height of the gate electrode 2, and the projection 21 is electrically connected to the gate electrode 2.

With continued reference to fig. 1 and 2, two sides of the gate electrode 2, one side intersecting the trench isolation structure 11 and the source region 111 and one side intersecting the trench isolation structure 11 and the drain region 112, it can be understood that each gate electrode 2 has 4 intersecting positions (4 intersections) with the corresponding active region 12, and the four intersecting positions are two-by-two symmetric. The protruding portion 21 is located at a boundary between the gate electrode 2 and the active region 12, and the protruding portion 21 further extends into the active region 12 and the trench isolation structure 11 at the boundary, so that the protruding portion 21 is partially located in the active region and the other portion is located in the trench isolation structure 11. Optionally, the protruding portions 21 are disposed at 4 junctions of the gate electrode 2 and each active region 12, so that the 4 protruding portions 21 are arranged two by two symmetrically. The protrusion 21 increases a lateral width dimension H (gate length) of the gate electrode 2 at a boundary between the active region 12 and the trench isolation structure 11, thereby increasing a length of a channel region at the boundary, reducing on-current, and thus suppressing kink and hot electron induced punch-through effects. Further, the transverse width dimension h' of the protruding portion 21 gradually decreases from the boundary to the center of the active region 12, so that the area of the protruding portion 21 increases less while the gate length of the gate electrode 2 at the boundary is increased, and thus the on-state current is not decreased too much, and the influence on the on-state performance of the device is small.

Optionally, the protruding portion 21 may be symmetrical with respect to a boundary line between the active region 12 and the trench isolation structure 11, that is, the protruding portion 21 is an axisymmetric structure, and the symmetry axis is a boundary line between the active region 12 and the trench isolation structure 11, so that the forming process of the protruding portion 21 is simple. It should be understood that the protrusion 21 may not be an axisymmetric structure, and the portion thereof on the trench isolation structure may have any shape.

Alternatively, the width dimension h of the protruding portion 21 in the direction parallel to the extension direction of the gate electrode 2 is between 30nm and 140nm, for example, the width dimension h of the protruding portion 21 in the direction parallel to the extension direction of the gate electrode 2 varies between 30nm and 140nm, or alternatively, the maximum value of the width dimension h of the protruding portion 21 in the direction parallel to the extension direction of the gate electrode 2 may be smaller than 140 nm. The lateral width dimension h' of the protruding portion 21 is between 20nm and 100nm, and the boundary of the protruding portion 21 in the protruding direction is always located in the channel region.

Further, as shown in fig. 1, the sidewall of the protruding portion 21 is stepped, so that the lateral width dimension h' of the protruding portion 21 is reduced in a step shape from the boundary to the center of the active region 12, and this embodiment shows a case where the sidewall of the protruding portion 21 has two steps, but it is understood that the sidewall of the protruding portion 21 in the present invention may also form 2-5 steps, and is not limited to two, and the shape of the protruding portion 21 with the stepped sidewall is relatively regular, and the forming process is simple. Alternatively, as shown in fig. 3, the side wall of the protruding portion 21 may be inclined, so that the cross section of the protruding portion 21 in the direction perpendicular to the height is trapezoidal, that is, the transverse width dimension h' of the protruding portion 21 is continuously and slowly reduced from the boundary toward the center of the active region 12. It is understood that the protrusion 21 may have other shapes, as long as the lateral width h' of the gate electrode 2 at the boundary is gradually decreased from the boundary to the center of the active region 12, which is not illustrated in the present invention.

Optionally, at least one side of the gate electrode 2 has the protruding portion 21 at a boundary between the active region 12 and the trench isolation structure 11, as shown in fig. 1 and 3, the protruding portions 21 are respectively disposed at 4 boundaries between the active region 12 and the trench isolation structure 11 at two sides of the gate electrode 2, so that the length of a channel region at the boundary is uniformly lengthened, the structure of the entire device is more symmetrical, and the performance is stable. In other embodiments, the protruding portion 21 may be formed on only one side of the gate electrode 2 at the boundary between the active region 12 and the trench isolation structure 11, specifically, as shown in fig. 4, one protruding portion 21 is formed on each of the left side and the right side of the gate electrode 2, so as to achieve the effect of increasing the width of the channel region at the boundary between the active region 11 and the trench isolation structure 11, but in fig. 4, the protruding portions 21 corresponding to the same active region 12 are located on different sides of the gate electrode 2, but actually, the protruding portions 21 corresponding to the same active region 12 may also be located on the same side of the gate electrode 2. Alternatively, there may be 3 protruding portions 21 corresponding to the same active region 12, that is, the protruding portions 21 are formed in 4 interfaces of the active region 12 and the trench isolation structure 11, and the invention is not limited thereto.

Further, the active regions 12 in the same column may correspond to one gate electrode 2, or may correspond to a plurality of gate electrodes 2, and the active regions 12 in the same column intersect with the same gate electrode 2. Fig. 5 shows a case where one of the active regions 12 corresponds to two of the gate electrodes 2, in such a structure that the substrate has two source regions and one drain region therein, the two source regions are located between the drain regions, the two gate electrodes 2 separate each of the source regions and the drain regions so that both sides of the gate electrode 2 are the source region and the drain region, and the drain region is shared by the two gate electrodes 2. The number and shape of each gate electrode 2 and the protruding portion 21 at the boundary between the active region 12 and the trench isolation structure 11 may be any combination of the above, which is not illustrated here.

It is understood that the semiconductor structure described in this embodiment may be applied to an integrated circuit memory, the active region 12 is used to form transistors of the integrated circuit memory, and the number of transistors in each integrated circuit memory may be one or more, and the present invention is not limited thereto.

In summary, in the semiconductor device provided in the embodiments of the present invention, the semiconductor device includes a substrate, a trench isolation structure defining an active region is formed in the substrate, a gate electrode is formed on the substrate, the gate electrode is located on the active region and extends to the trench isolation structure, the gate electrode has a protruding portion at a boundary between the active region and the trench isolation structure, so that a lateral width dimension of the gate electrode at the boundary is greater than a lateral width dimension of the gate electrode at a central region of the active region, thereby increasing a length of a channel region at the boundary, reducing an on-state current, and being capable of suppressing an ability of the trench isolation structure to trap electrons, so as to improve a performance of the device, and a lateral width dimension of the protruding portion gradually decreases from the boundary toward a center of the active region, while increasing a length of the channel region at the boundary, the on-current does not drop too much, and thus the on-performance of the device is less affected.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.