阅读说明：本技术 固态成像设备 (Solid-state imaging device ) 是由 田丸雅规 春日繁孝 坂田祐辅 森三佳 香山信三 于 2020-03-03 设计创作，主要内容包括：本公开解决的问题是提供一种适于实现高灵敏度和高集成度的固态成像设备。设置在半导体衬底(100)上并以二维阵列布置的多个像素单元(10)中的至少一个像素单元(10)包括光接收部分(2)、像素电路(30)和第二晶体管(4)。光接收部分(2)接收入射光以产生电荷。像素电路(30)包括沿第一方向并排布置的多个第一晶体管(3)和电荷保持部分(5)。电荷保持部分(5)保持由光接收部分(2)产生的电荷。像素电路(30)输出根据由光接收部分(2)产生的电荷的光接收信号。第二晶体管(4)将电荷保持部分(5)连接到存储电荷的存储器部分(6)。在沿半导体衬底(100)的厚度方向观察的平面图中,像素单元(10)被配置为使得第二晶体管(4)在第二方向上与多个第一晶体管(3)分开,该第二方向与第一方向正交。(The present disclosure addresses the problem of providing a solid-state imaging device suitable for achieving high sensitivity and high integration. At least one pixel unit (10) of a plurality of pixel units (10) provided on a semiconductor substrate (100) and arranged in a two-dimensional array includes a light receiving portion (2), a pixel circuit (30), and a second transistor (4). The light receiving section (2) receives incident light to generate electric charges. The pixel circuit (30) includes a plurality of first transistors (3) and a charge holding portion (5) arranged side by side in a first direction. The charge holding portion (5) holds the charge generated by the light receiving portion (2). The pixel circuit (30) outputs a light reception signal according to the electric charge generated by the light receiving section (2). The second transistor (4) connects the charge holding portion (5) to the memory portion (6) that stores the charge. In a plan view viewed in a thickness direction of the semiconductor substrate (100), the pixel unit (10) is configured such that the second transistor (4) is separated from the plurality of first transistors (3) in a second direction, which is orthogonal to the first direction.)

1. A solid-state imaging device includes a plurality of pixel units formed in a semiconductor substrate and arranged in a two-dimensional array,

at least one pixel cell of the plurality of pixel cells includes:

a light receiving section configured to receive incident light to generate charges;

a pixel circuit including a plurality of first transistors arranged side by side in a first direction and a charge holding portion configured to hold charges generated by the light receiving portion, the pixel circuit being configured to output a light receiving signal according to the charges generated by the light receiving portion; and

a second transistor connecting the charge holding portion to a memory portion configured to store the charge, an

The at least one pixel unit is configured such that the second transistor is separated from the plurality of first transistors in a second direction orthogonal to the first direction in a plan view viewed in a thickness direction of the semiconductor substrate.

2. The solid-state imaging apparatus according to claim 1, wherein the at least one pixel unit is configured such that:

the charge holding portion includes a diffusion region having a floating potential; and

the plurality of first transistors includes:

a transfer transistor configured to transfer charges generated by the light receiving portion to the diffusion region;

a reset transistor configured to reset the charge stored in the diffusion region; and

an amplifier transistor having a gate electrode electrically connected to the diffusion region.

3. The solid-state imaging device according to claim 2, wherein the at least one pixel unit is configured such that:

the diffusion region is a first diffusion region;

the second transistor includes a second diffusion region having a floating potential;

the first diffusion region and the second diffusion region are connected to each other; and

at least a portion of the first diffusion region and at least a portion of the second diffusion region overlap each other when viewed in the second direction.

4. The solid-state imaging device according to claim 3, wherein the at least one pixel unit is configured such that: an entirety of one of the first diffusion region and the second diffusion region overlaps the other of the first diffusion region and the second diffusion region when viewed in the second direction.

5. The solid-state imaging device according to claim 3 or 4, wherein the at least one pixel unit is configured such that: the first diffusion region and the second diffusion region are connected to each other by a metal wiring.

6. The solid-state imaging device according to claim 3 or 4, wherein the at least one pixel unit is configured such that: the first diffusion region and the second diffusion region are connected to each other by a diffusion layer wiring formed in the semiconductor substrate.

7. The solid-state imaging device according to any one of claims 1 to 6, wherein the at least one pixel unit is configured such that:

the plurality of first transistors respectively have gate electrodes, the gate electrodes of the plurality of first transistors are arranged side by side in the first direction,

the plurality of first transistors includes two first transistors located at both ends in the first direction and the remaining first transistors,

the gate electrodes of the remaining first transistors are located at any of virtual points that divide the line segment equally, and

the line segment connects two gate electrodes of the two first transistors located at both ends in the first direction.

8. The solid-state imaging device according to any one of claims 1 to 7, wherein the plurality of pixel units have the same shape as each other in a plan view viewed in a thickness direction of the semiconductor substrate.

9. The solid-state imaging apparatus according to any one of claims 1 to 8, wherein

The plurality of pixel units includes a first pixel unit and a second pixel unit arranged adjacent to each other,

the plurality of first transistors of the first pixel unit have gate electrodes respectively,

the second transistor of the second pixel cell has a gate electrode,

the gate electrodes of the plurality of first transistors of the first pixel unit and the gate electrode of the second transistor of the second pixel unit are arranged side by side in the first direction,

the gate electrodes of the plurality of first transistors of the first pixel unit and the gate electrode of the second transistor of the second pixel unit include two gate electrodes of transistors located at both ends in the first direction and gate electrodes of the remaining transistors,

the gate electrodes of the remaining transistors are located at any of virtual points that divide a line segment equally, and

the line segment connects the two gate electrodes of the transistors located at both ends in the first direction.

10. The solid-state imaging device according to any one of claims 1 to 9, wherein the plurality of pixel units includes two pixel units adjacent in the second direction,

in a plan view viewed in a thickness direction of the semiconductor substrate,

the light receiving portion of one of the two pixel units is adjacent to the light receiving portion of the other of the two pixel units, or

The pixel circuit of one of the two pixel units is adjacent to the pixel circuit of the other of the two pixel units.

Technical Field

The present disclosure relates to a solid-state imaging device, and more particularly, to a solid-state imaging device including a plurality of pixel units.

Background

Patent document 1 discloses a solid-state imaging device. The solid-state imaging device includes: a light receiving element having a photoelectric conversion function; a resetting device that repeatedly resets the light receiving element; and a detection device that detects information on whether or not there is an incident photon during a period between reset pulses that reset the light receiving element. The solid-state imaging device further includes: counter value holding means for counting the number of detection pulses of the detecting means during a predetermined period of time; and reading means for reading out the count value of the counter value holding means every predetermined period.

Reference list

Patent document

Patent document 1: JPH07-67043A

Disclosure of Invention

In some cases, in the technical field of solid-state imaging devices such as the one disclosed in patent document 1, it may be desirable to achieve high sensitivity and high integration of a pixel unit including a light receiving element (light receiving section).

The present disclosure relates to a solid-state imaging device for achieving high sensitivity and high integration.

A solid-state imaging device of an aspect of the present disclosure includes a plurality of pixel units formed on one surface of a semiconductor substrate. At least one pixel unit of the plurality of pixel units includes a light receiving portion, a pixel circuit, and a second transistor. The light receiving portion is configured to receive incident light to generate electric charges. The pixel circuit includes a plurality of first transistors arranged side by side in a first direction and a charge holding portion configured to hold a charge generated by the light receiving portion. The pixel circuit is configured to output a light reception signal according to the electric charge generated by the light receiving section. The second transistor connects the charge holding portion to a memory portion configured to store charge. In a plan view viewed in a thickness direction of the semiconductor substrate, the at least one pixel unit is configured such that the second transistor is separated from the plurality of first transistors in a second direction, the second direction being orthogonal to the first direction.

Drawings

Fig. 1 is a schematic diagram showing an arrangement of a plurality of pixel units of a solid-state imaging device according to an embodiment;

fig. 2 is a schematic diagram showing an arrangement of a light receiving section, a first transistor, and a second transistor included in a pixel unit of a solid-state imaging device according to an embodiment;

FIG. 3 is a circuit diagram of a pixel cell according to an embodiment;

fig. 4 is a schematic diagram showing an arrangement of a plurality of pixel units of the solid-state imaging device according to the embodiment;

fig. 5 is a sectional view taken along line V-V of fig. 4, and shows a plurality of pixel units of the solid-state imaging device according to the embodiment;

fig. 6 is a schematic diagram showing connection of a first circuit and a second circuit in a pixel unit of a solid-state imaging device according to a modification;

fig. 7 is a schematic diagram showing an arrangement of a plurality of pixel units of a solid-state imaging device according to a modification.

Detailed Description

A solid-state imaging device of an embodiment of the present disclosure will be described with reference to the drawings. However, the embodiments described below are merely examples of various embodiments of the present disclosure. The embodiments described below may be modified in various ways according to design or the like as long as the object of the present disclosure can be achieved. The drawings mentioned in the following embodiments are schematic drawings, and it is not guaranteed that the proportions of the size and thickness of the components shown in the drawings reflect actual proportions.

(1) Examples of the embodiments

(1.1) overview

For example, the solid-state imaging device 1 of the present embodiment may be used for a distance measurement system that acquires a distance image of a target space based on a time-of-flight (TOF) method.

For example, the distance measuring system includes: a wave transmitting module that outputs pulsed light; a wave receiving module that receives pulsed light (reflected light) that is output from the wave transmitting module and reflected by an object; and a processor that determines a distance of the object based on the reflected light received by the wave receiving module. The processor may determine the distance of the object based on a timing at which the wave transmitting module outputs the pulsed light and a timing at which the wave receiving module receives the reflected light.

The pulsed light output from the wave transmitting module may be monochromatic, have a relatively short pulse width and a relatively high peak intensity. In view of the use of the distance measuring system in urban areas, the wavelength of pulsed light may be in the wavelength range of the near infrared band, in which the human visual sensitivity is low, and is not easily affected by disturbance light from sunlight.

For example, such a distance measurement system may be used for an object detection system installed on an automobile to detect an obstacle, a surveillance camera or a security camera configured to detect an object (e.g., a person), or the like.

For example, the solid-state imaging device 1 of the present embodiment may be used in the wave receiving module of the distance measuring system described above.

As shown in fig. 1, the solid-state imaging device 1 includes a plurality of pixel units 10. A plurality of pixel cells 10 are formed in a semiconductor substrate 100. A plurality of pixel units 10 are formed in one surface 200 (see fig. 5) in the thickness direction of the semiconductor substrate 100 and arranged in a two-dimensional array.

Specifically, according to the plurality of pixel units 10, two or more pixel units 10 are arranged side by side at equal intervals in one direction (left-right direction in fig. 1) to form a pixel unit group, and two or more pixel unit groups are arranged side by side in another direction (up-down direction in fig. 1) orthogonal to the one direction. For two pixel cell groups adjacent to each other in the other direction, the pixel cells 10 of one pixel cell group are displaced by half the size of one pixel cell 10 in the one direction with respect to the pixel cells 10 of the other pixel cell group. That is, the plurality of pixel units 10 are arranged in a so-called staggered arrangement. For convenience of description, in fig. 1, illustration of the wiring 60 connecting the light receiving portion 2 and the first circuit 30, the wiring 61 connecting the first circuit 30 and the second circuit 40, and the like is omitted.

As shown in fig. 2, at least one pixel unit 10 (each of the plurality of pixel units 10 in the present embodiment) of the plurality of pixel units 10 includes a light receiving section 2, a pixel circuit (hereinafter, also referred to as "first circuit") 30, and a second circuit 40.

The light receiving portion 2 is formed in the semiconductor substrate 100. The light receiving portion 2 functions as a photoelectric converter that receives incident light to generate electric charges. The light receiving section 2 is formed in the first region 12 of the pixel unit 10.

The first circuit (pixel circuit) 30 includes a circuit configured to output a light reception signal according to the electric charge generated by the light receiving section 2. The first circuit 30 is formed in a second region 13 of the pixel unit 10, the second region 13 being different from the first region 12.

The first circuit 30 includes a plurality of first transistors 3. A plurality of first transistors 3 are formed in the semiconductor substrate 100. The plurality of first transistors 3 (specifically, the gate electrodes of the respective plurality of first transistors 3) are arranged side by side in a first direction D1 orthogonal to the thickness direction of the semiconductor substrate 100.

The first circuit 30 includes a charge holding portion 5. The charge holding portion 5 is connected to the light receiving portion 2 through a wiring 60 via a first transistor 3 (a transfer transistor 31 described later). The charge holding portion 5 is configured to hold (store) the charge generated by the light receiving portion 2.

The second circuit 40 is formed in a third region 14 of the pixel unit 10, the third region 14 being different from the first region 12 and the second region 13. The second circuit 40 includes a second transistor 4. The second transistor 4 is formed in the semiconductor substrate 100. The second transistor 4 connects the charge holding portion 5 of the first circuit 30 to the memory portion 6 configured to store electric charges (see fig. 3). The second transistor 4 is connected to the charge holding portion 5 through a wiring 61.

As shown in fig. 2, the second transistor 4 is separated from the plurality of first transistors 3 in a second direction D2, the second direction D2 being orthogonal to each of the first direction D1 and the thickness direction of the semiconductor substrate 100. In other words, at least one pixel unit 10 (in the present embodiment, each of the plurality of pixel units 10) of the plurality of pixel units 10 is configured such that: in a plan view (viewed from a normal direction of the paper of fig. 2) viewed in the thickness direction of the semiconductor substrate 100, the second transistor 4 is separated from the plurality of first transistors 3 in a second direction D2 orthogonal to the first direction D1, and the plurality of first transistors 3 are arranged side by side in the first direction D1. In an embodiment, the second transistor 4 is placed side by side with the first transistor 3 in the second direction D2.

The solid-state imaging device 1 of the present embodiment can shorten the length of the wiring 61 connecting the second transistor 4 and the charge holding portion 5 together, compared with the pixel unit 10 in which the second transistor 4 is not separated from the plurality of first transistors 3 in the second direction D2 (i.e., the second transistor 4 is placed side by side with the plurality of first transistors 3 in the first direction D1). This can reduce the parasitic capacitance of the wiring 61 to achieve high gain and high sensitivity of photoelectric conversion. This can also reduce the parasitic resistance of the wiring 61 to achieve high responsiveness to charge transfer. In addition, the pixel cells 10 may be adjacently disposed such that the first circuit 30 of one pixel cell 10 and the second circuit 40 of another pixel cell 10 are closely disposed, which may achieve a high integration of the pixel cells.

(1.2) details

The solid-state imaging device 1 of the present embodiment will be explained in more detail with reference to fig. 1 to 5.

As shown in fig. 1, the solid-state imaging device 1 includes a semiconductor substrate 100. A plurality of pixel cells 10 are formed in a semiconductor substrate 100. That is, the solid-state imaging device 1 includes a plurality of pixel units 10. A plurality of pixel units 10 are formed in a semiconductor substrate 100 and arranged in a two-dimensional array.

(1.2.1) Circuit configuration of Pixel cell

The circuit configuration of the pixel unit 10 is explained with reference to fig. 3.

As shown in fig. 3, the pixel unit 10 includes a light receiving section 2, a plurality of first transistors 3, a second transistor 4, a charge holding section 5, and a memory section 6. The first circuit 30 includes a plurality of first transistors 3 and a charge holding portion 5. The second circuit 40 includes a second transistor 4.

The light receiving section 2 includes a photodiode formed in a surface region of the semiconductor substrate 100 near the one surface 200. The photodiode may be an avalanche photodiode (hereinafter also referred to as "APD") 20. APD20 includes an n-type diffusion region formed in a p-type semiconductor substrate 100.

APD20 includes a first mode and a second mode as its modes of operation. APD20, when applied with a reverse bias voltage less than its breakdown voltage, collects into the cathode a charge substantially proportional to the number of photons causing photoelectric conversion in response to received light (operating in a first mode). When a reverse bias voltage equal to or greater than the breakdown voltage is applied, APD20 collects the amount of charge corresponding to the saturation level obtained by photoelectric conversion into the cathode in response to light reception of a single photon (operates in the second mode). The operating mode of APD20 can be changed by changing the potential of a bias electrode 101 connected to the anode.

The charge holding portion 5 is configured to hold the charge generated by the light receiving portion 2. The diffusion region 50 (hereinafter, also referred to as "first diffusion region") is a so-called Floating Diffusion (FD).

The plurality of first transistors 3 includes a transfer transistor 31, a first reset transistor 32, and an amplifier transistor 33. In the present embodiment, the plurality of first transistors 3 further includes a second reset transistor 34 and a selection transistor 35.

The transfer transistor 31 includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 310. One impurity diffusion region of the transfer transistor 31 is connected to the cathode of the APD20, and the other impurity diffusion region of the transfer transistor 31 is connected to a diffusion region (first diffusion region) 50.

When a voltage is applied to the gate electrode 310 to turn on, the transfer transistor 31 moves (transfers) the charge collected in the cathode of the APD20 to the first diffusion region 50.

The first reset transistor 32 includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 320. One of the impurity diffusion regions of the first reset transistor 32 is connected to the first reset drain electrode 102. The other of the impurity diffusion regions of the first reset transistor 32 is connected to a diffusion region (first diffusion region) 50.

When a voltage is applied to the gate electrode 320 to turn on, the first reset transistor 32 causes the first diffusion region 50 to discharge the stored charge to the first reset drain electrode 102 (i.e., resets the first diffusion region 50).

The amplifier transistor 33 includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 330. One of the impurity diffusion regions of the amplifier transistor 33 is connected to the amplifier electrode 103, and the other is connected to the signal line 110 via the selection transistor 35. The gate electrode 330 of the amplifier transistor 33 is connected to the first diffusion region 50.

The amplifier transistor 33 outputs a voltage indicating the amount of charge stored in the first diffusion region 50. The output voltage of the amplifier transistor 33 serves as a light receiving signal (i.e., a light receiving signal according to the electric charge generated by the light receiving portion 2) output from the pixel unit 10.

The selection transistor 35 includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 350. One of the impurity diffusion regions of the selection transistor 35 is connected to the impurity diffusion region of the amplifier transistor 33, and the other is connected to the signal line 110.

The selection transistor 35 allows the voltage of the amplifier transistor 33 (i.e., the light reception signal) to be output to the signal line 110 only when a voltage is applied to the gate electrode 350 to be turned on.

The second reset transistor 34 includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 340. One of the impurity diffusion regions of the second reset transistor 34 is connected to the second reset drain electrode 104. The other of the impurity diffusion regions of the second reset transistor 34 is connected to the cathode of the APD 20.

When a voltage is applied to the gate electrode 340 to turn on, the second reset transistor 34 causes the cathode of the APD20 to discharge the stored charge to the second reset drain electrode 104 (i.e., to reset the cathode of the APD 20).

The memory portion 6 may include a capacitor to store charge. The memory portion 6 has a stacked structure including a pair of electrodes and an insulating layer sandwiched therebetween. Alternatively, the memory portion 6 may have a stacked structure including an electrode, a semiconductor layer, and an insulating layer sandwiched therebetween. For example, the memory portion 6 is disposed on one surface 200 of the semiconductor substrate 100 via an insulating layer.

The second transistor 4 (hereinafter, also referred to as "counter transistor 41") includes two impurity diffusion regions formed in the semiconductor substrate 100 and a gate electrode 410.

The counter transistor 41 is connected between the first diffusion region 50 and the memory portion 6. One of the impurity diffusion regions of the counter transistor 41 is connected to the first diffusion region 50, and the other is connected to the memory portion 6.

When no voltage is applied to the gate electrode 410 to turn off, the counter transistor 41 inhibits charge transfer between the first diffusion region 50 and the memory portion 6. When turned on by applying a voltage to the gate electrode 410, the counter transistor 41 allows charge to be transferred between the first diffusion region 50 and the memory portion 6.

(1.2.2) operation

The light receiving operation of the solid-state imaging device 1 will be explained. The solid-state imaging device 1 includes a controller (control circuit) that controls the operation of the pixel unit 10. The controller controls the operation of the pixel cell 10 by controlling the voltage applied to the bias electrode 101, the respective voltages applied to the gate electrode of the first transistor 3 and the voltage applied to the gate electrode of the second transistor 4.

The controller of the solid-state imaging device 1 includes a first reception mode and a second reception mode as its operation modes. When operating in the first receive mode, the controller controls APD20 of pixel cell 10 to operate in the first mode (i.e., adjusts the voltage applied to bias electrode 101 such that APD20 operates in the first mode). When operating in the second reception mode, the solid-state imaging device 1 controls the APD20 of the pixel unit 10 to operate in the second mode (i.e., adjusts the voltage applied to the bias electrode 101 so that the APD20 operates in the second mode). The second reception mode is adapted to detect weak light compared to the first reception mode.

The solid-state imaging device 1 operates in the following manner in the first reception mode.

First, the controller of the solid-state imaging device 1 turns on the first reset transistor 32, the second reset transistor 34, and the counter transistor 41 to reset (release the stored charges thereof) the cathode of the APD20, the charge holding portion 5 (the first diffusion region 50), and the memory portion 6, while keeping the transfer transistor 31 off.

Next, the controller turns off the first reset transistor 32, the second reset transistor 34, and the counter transistor 41. This state is referred to as the exposure state of the pixel unit 10. In response to the received light, APD20 in the exposed state collects into the cathode a charge substantially proportional to the number of photons causing the photoelectric conversion.

Note that the second reset transistor 34 has an off potential lower than the off potential of the transfer transistor 31. Thus, when the amount of charge collected into the cathode of the APD20 reaches the saturation level of the cathode, the excess charge flows over the potential barrier of the second reset transistor 34 to overflow to the second reset drain electrode 104.

Then, the controller turns on the first reset transistor 32 to reset the charge holding portion 5. The controller turns off the first reset transistor 32. The controller then turns on the transfer transistor 31 to connect the cathode of the APD20 to the charge holding portion 5. As a result, the electric charges collected in the APD20 are transferred to the charge holding portion 5 (first diffusion region 50) and stored therein.

The electric charge stored in the charge holding portion 5 is converted into a light receiving signal indicating the amount of stored electric charge by the amplifier transistor 33 whose gate electrode 330 is connected to the charge holding portion 5.

The controller of the solid-state imaging device 1 turns on the selection transistor 35 of the target pixel unit 10 to allow the pixel unit 10 to output the light reception signal to the signal line 110.

The solid-state imaging device 1 operates in the following manner in the second reception mode. Specifically, the controller in the second reception mode divides the predetermined measurement period so that it includes a plurality of exposure periods. The controller determines whether or not a photoelectric conversion phenomenon occurs in each exposure period respectively corresponding to the respective exposure processes, thereby counting the number of photons reaching the light receiving portion 2 during the measurement period.

Specifically, the controller of the solid-state imaging device 1 in the second reception mode causes the pixel unit 10 to operate as follows.

At the start point of the measurement period, the controller of the solid-state imaging device 1 turns on the first reset transistor 32, the second reset transistor 34, and the counter transistor 41 to reset the cathode of the APD20, the charge holding portion 5 (the first diffusion region 50), and the memory portion 6 while keeping the transfer transistor 31 off.

At the start point of each exposure process of the exposure period, the controller turns off the first reset transistor 32, the second reset transistor 34, and the counter transistor 41. This state is the exposure state of the pixel unit 10. When receiving light in an exposure state, the APD20 collects an amount of electric charge corresponding to a saturation level obtained by photoelectric conversion into the cathode in response to a single photon. As described above, the off potential of the second reset transistor 34 is lower than the off potential of the transfer transistor 31. Thus, collected charge that exceeds the cathode saturation level of the APD20 flows through the potential barrier of the second reset transistor 34 to overflow to the second reset drain electrode 104. This means that, in the second mode, the amount of charge stored in the cathode of APD20 (corresponding to the amount of charge stored in the cathode in response to photoelectric conversion by a single photon) may be substantially the same (the amount of charge corresponding to the cathode saturation level) each time.

Next, the controller turns on the transfer transistor 31 to connect the cathode of the APD20 to the charge holding portion 5 (first diffusion region 50). As a result, the electric charges collected in the APD20 are distributed to the cathode of the APD20 and the charge holding portion 5 (first diffusion region 50).

The controller then turns off the transfer transistor 31. As a result, a part of the electric charges collected in the cathode of the APD20, which is distributed to the charge holding portion 5, will remain in the charge holding portion 5.

The controller turns on the counter transistor 41 to redistribute the charge stored in the charge holding portion 5 to the charge holding portion 5 and the memory portion 6. This means that the controller transfers (part of) the charge stored in the charge holding portion 5 to the memory portion 6. Therefore, a part of the electric charges generated by the photoelectric conversion by the light receiving portion 2 is transferred to the memory portion 6 to increase the electric charge storage amount in the memory portion 6.

On the other hand, when APD20 does not receive light during the exposure period, no photoelectric conversion effect occurs and APD20 does not collect charge at the cathode. Therefore, when the controller turns on the transfer transistor 31, no charge is transferred from the cathode of the APD20 to the charge holding portion 5. This means that the amount of charge in the memory portion 6 does not increase when the counter transistor 41 is turned on thereafter.

The controller repeats the above operations by the number of times of the exposure process. As a result, the memory portion 6 stores the amount of electric charges corresponding to the number of exposure processes in which the APD20 receives light among the plurality of exposure processes contained in one measurement period.

It may be noted that in the case where APD20 receives light during a first exposure, a certain amount of charge is already stored in memory portion 6 prior to a second or subsequent exposure. This means that the charge increase amount of the memory portion 6 of the second or subsequent exposure process may be different from the charge increase amount of the first exposure process. It is also noted that the first reset transistor 32 does not have to be turned off at the start point of the second or subsequent exposure process. However, these points are not described in further detail as they are not the purpose of this disclosure.

At the end of the measurement period (i.e., the completion of all of the plurality of exposure processes), the controller turns on the counter transistor 41 to connect the memory portion 6 to the charge holding portion 5, thereby distributing the charges stored in the memory portion 6 to the memory portion 6 and the charge holding portion 5. The electric charge distributed from the memory portion 6 to the charge holding portion 5 is converted into a light reception signal indicating the amount of electric charge (i.e., indicating the number of exposure processes in which the APD20 receives light) by the amplifier transistor 33, and the gate electrode 330 of the amplifier transistor 33 is connected to the charge holding portion 5.

The controller of the solid-state imaging device 1 turns on the selection transistor 35 of the target pixel unit 10 to allow the pixel unit 10 to output the light reception signal to the signal line 110.

(1.2.3) arrangement

The layout of a plurality of pixel cells 10 in the solid-state imaging device 1 and the layout of the pixel cells 10 of the present embodiment will be described with reference to fig. 1, 2, 4, and 5.

As shown in fig. 1, a plurality of pixel units 10 are formed in a two-dimensional array in a semiconductor substrate 100.

The semiconductor substrate 100 may be a p-type silicon substrate. An n-type well region 8 extending in one direction (the left-right direction in fig. 1) is formed in one surface 200 (one surface in the thickness direction) of the semiconductor substrate 100. The p-type well region 9 is formed in the n-type well region 8 to extend in the longitudinal direction of the n-type well region 8.

In each pixel unit 10, the first circuit 30 and the second circuit 40 are formed in the p-type well region 9. In each pixel unit 10, the light receiving portion 2 is formed at a position in a p-type region formed outside the n-type well region 8 and in the semiconductor substrate 100.

Two or more (three in the example of fig. 1) pixel cells 10 (hereinafter, referred to as "first pixel cell group") are arranged side by side along one of the long sides of one p-type well region 9. Another two or more (three in the example of fig. 1) pixel cells 10 (hereinafter, referred to as "second pixel cell group") are arranged side by side along the other of the long sides of the p-type well region 9. The first circuit 30 and the second circuit 40 of each pixel cell 10 in the first pixel cell group, and the first circuit 30 and the second circuit 40 of each pixel cell 10 in the second pixel cell group are formed in the p-type well region 9. In the example of fig. 1, the first circuit 30 and the second circuit 40 of the total six pixel cells 10 of the first pixel cell group and the second pixel cell group are formed in the one p-type well region 9, but are not limited thereto. Alternatively, the first pixel cell group may include one, two, four or more pixel cells 10, and/or the second pixel cell group may include one, two, four or more pixel cells 10. The number of pixel cells 10 of the second pixel cell group may be the same as or different from the number of pixel cells 10 of the first pixel cell group.

As shown in fig. 1, the plurality of pixel cells 10 have the same shape as each other in a plan view viewed in the thickness direction of the semiconductor substrate 100 (viewed in the normal direction of the paper surface of fig. 1). In the example of fig. 1, the plurality of pixel cells 10 of the first pixel cell group have the same shape as each other. The plurality of pixel cells 10 of the second pixel cell group have the same shape as each other. In addition, the pixel cells 10 of the first pixel cell group are the same in shape as the pixel cells 10 of the second pixel cell group. Such a configuration in which the plurality of pixel cells 10 have the same shape as each other enables the wirings 60, 61 of the plurality of pixel cells 10 to have substantially the same shape. This makes it possible to equalize the lengths of the wirings 60, 61 of the plurality of pixel units 10 to equalize the parasitic resistances and parasitic capacitances of the wirings 60, 61. This may further reduce individual fluctuations in the characteristics of the pixel cell 10.

The plurality of pixel cells 10 includes two pixel cells adjacent in the second direction D2 (width direction of p-type well; up-down direction in fig. 1). In a plan view viewed in the thickness direction of the semiconductor substrate 100, the light receiving portion 2 of one of the two pixel units 10 is adjacent to the light receiving portion 2 of the other of the two pixel units 10, or the first circuit (pixel circuit) 30 of one of the two pixel units 10 is adjacent to the first circuit (pixel circuit) 30 of the other of the two pixel units 10.

As shown in fig. 2, the light receiving section 2 is formed in the first region 12, the first circuit 30 is formed in the second region 13, and the second circuit 40 is formed in the third region 14. The first region 12, the second region 13, and the third region 14 are arranged in this order along the second direction D2.

As shown in fig. 2, 4 and 5, the first circuit 30 of each pixel unit 10 includes: a plurality of (six in the present embodiment) diffusion regions 50 to 55 arranged side by side in the first direction D1; and a plurality of gate electrodes 310 to 350 arranged side by side along the first direction D1.

Each of the plurality of diffusion regions 50 to 55 is an n-type diffusion region formed in the p-type well region 9. As shown in fig. 2, the diffusion regions 51, 52, 50, 53, 54, and 55 are arranged in this order along the first direction D1.

Each of the plurality of gate electrodes 310 to 350 extends in a second direction D2 orthogonal to the first direction D1 and the thickness direction of the semiconductor substrate 100. The plurality of gate electrodes 310 to 350 have the same width (a dimension in the first direction D1) and have the same length (a dimension in the second direction D2). The gate electrodes 340, 310, 320, 330, and 350 are arranged in this order along the first direction D1.

Each of the plurality of gate electrodes 310 to 350 is formed on one surface 200 of the semiconductor substrate 100 via a gate insulating film (not shown) made of silicon oxide or the like. Each of the plurality of gate electrodes 310 to 350 is formed on one surface 200 of the semiconductor substrate 100 to bridge ends of two diffusion regions adjacent in the first direction D1. These two adjacent diffusion regions constitute the first transistor 3 together with a gate electrode bridging them and a gate insulating film. Therefore, the plurality of first transistors 3 are arranged side by side in the first direction D1.

Specifically, the plurality of first transistors 3 includes a second reset transistor 34, a transfer transistor 31, a first reset transistor 32, an amplifier transistor 33, and a selection transistor 35.

The second reset transistor 34 includes a gate electrode 340 and diffusion regions 51, 52. That is, the diffusion regions 51, 52 function as two impurity diffusion regions of the second reset transistor 34.

Transfer transistor 31 includes a gate electrode 310 and diffusion regions 52, 50. That is, the diffusion region 52 functions as one of the impurity diffusion regions of the transfer transistor 31, and doubles as an impurity diffusion region of the second reset transistor 34. The diffusion region (first diffusion region) 50 serves as the other of the impurity diffusion regions of the transfer transistor 31.

The first reset transistor 32 includes a gate electrode 320 and diffusion regions 50, 53. That is, the diffusion region 53 serves as one of the impurity diffusion regions of the first reset transistor 32. The diffusion region (first diffusion region) 50 serves as the other of the impurity diffusion regions of the first reset transistor 32 and doubles as an impurity diffusion region of the transfer transistor 31.

The amplifier transistor 33 includes a gate electrode 330 and diffusion regions 53, 54. That is, the diffusion region 53 serves as one of the impurity diffusion regions of the amplifier transistor 33 and doubles as an impurity diffusion region of the first reset transistor 32. The diffusion region 54 serves as the other of the impurity diffusion regions of the amplifier transistor 33.

The selection transistor 35 includes a gate electrode 350 and diffusion regions 54, 55. That is, the diffusion region 54 serves as one of the impurity diffusion regions of the selection transistor 35 and doubles as an impurity diffusion region of the amplifier transistor 33. The diffusion region 55 serves as the other of the impurity diffusion regions of the selection transistor 35.

The plurality of gate electrodes 310 to 350 are arranged along the first direction D1 and are equally spaced apart in the first direction D1. Specifically, the gate electrode 340 of the second reset transistor 34, the gate electrode 310 of the transfer transistor 31, the gate electrode 320 of the first reset transistor 32, the gate electrode 330 of the amplifier transistor 33, and the gate electrode 350 of the selection transistor 35 are arranged along the first direction D1 and are equally spaced in the first direction D1 (see fig. 4 and 5).

In other words, the gate electrodes of the plurality of first transistors 3 are arranged side by side in the first direction D1. Further, two first transistors 3 of the plurality of first transistors 3 are located at both ends in the first direction D1, and the gate electrodes of the remaining first transistors 3 of the plurality of first transistors 3 are located at any of virtual points that equally divide a line segment connecting the two gate electrodes (gate electrodes 340, 350) of the two first transistors 3 located at both ends in the first direction D1.

As shown in fig. 4, the diffusion region 51 (impurity diffusion region of the second reset transistor 34) is connected to the second reset drain electrode 104. The diffusion region 53 (the impurity diffusion region of the first reset transistor 32 and the impurity diffusion region of the amplifier transistor 33) is connected to the first reset drain electrode 102 and the amplifier electrode 103.

The first reset drain electrode 102 and the amplifier electrode 103 may be shared with each other. The second reset drain electrode 104 may be shared with at least one of the first reset drain electrode 102 and the amplifier electrode 103. In the present embodiment, the first reset drain electrode 102, the amplifier electrode 103, and the second reset drain electrode 104 are shared (connected) with each other, and are connected to a common power supply.

The diffusion region 52 is connected to the light receiving portion 2 through a wiring 60. For example, the wiring 60 is a metal wiring. The gate electrode 330 of the amplifier transistor 33 is connected to the first diffusion region 50 through a wiring 61. The wiring 61 is, for example, a metal wiring.

As shown in fig. 2, 4 and 5, the second transistor 4 of the second circuit 40 of each pixel cell 10 includes two diffusion regions 56, 57 arranged along the first direction D1, and a gate electrode 410. That is, the diffusion region 56 serves as one of the impurity diffusion regions of the second transistor 4, and the diffusion region 57 serves as the other of the impurity diffusion regions thereof.

Each of the two diffusion regions 56, 57 is an n-type diffusion region formed in the p-type well region 9. The two diffusion regions 56, 57 of the second circuit 40 are arranged in a direction parallel to a direction (first direction D1) in which the plurality of diffusion regions 50 to 55 of the first circuit 30 are arranged side by side.

The gate electrode 410 has the same width (a dimension in the first direction D1) as that of each of the plurality of gate electrodes 310 to 350, and has the same length (a dimension in the second direction D2) as that of each of the plurality of gate electrodes 310 to 350. A gate electrode 410 is formed on one surface 200 of the semiconductor substrate 100 via a gate insulating film (not shown) made of silicon oxide or the like. A gate electrode 410 is formed on one surface 200 of the semiconductor substrate 100 to bridge the ends of the two diffusion regions 56, 57. The two diffusion regions 56, 57 constitute the second transistor 4 (counter transistor 41) together with the gate electrode 410 and the gate insulating film that bridge them.

One diffusion region (hereinafter, referred to as "second diffusion region") 56 of the diffusion regions of the second transistor 4 of the second circuit 40 is connected to the diffusion region (first diffusion region) 50 (charge holding portion 5) of the first circuit 30 through a wiring 61. That is, the second transistor 4 (counter transistor 41) includes a diffusion region (second diffusion region) 56 connected to the first diffusion region 50. The second diffusion region 56 is a floating diffusion region. The second diffusion region 56 has a potential floating with respect to the semiconductor substrate 100. The second diffusion region 56 is connected to the first diffusion region 50 through a wiring 61 (e.g., a metal wiring).

As shown in fig. 4, when viewed in the second direction D2 orthogonal to the first direction D1 in which the plurality of first transistors 3 are arranged side by side, at least a part of the diffusion region (second diffusion region) 56 overlaps at least a part of the first diffusion region 50 of the first circuit 30. Specifically, the width of the first diffusion region 50 (the dimension in the first direction D1) is the same as the width of the second diffusion region 56. Further, when viewed in the second direction D2: the entirety of one of the first diffusion region 50 and the second diffusion region 56 overlaps the other of the second diffusion region 56 and the first diffusion region 50.

Therefore, in the pixel unit 10, the portion of the first circuit 30 connected to the second circuit 40 (i.e., the first diffusion region 50) and the portion of the second circuit 40 connected to the first circuit 30 (i.e., the second diffusion region 56) face each other in the second direction D2. This can reduce the length of the wiring 61 connecting the first circuit 30 and the second circuit 40. Further, this can increase the width (the size in the first direction D1) of the connection portion of the wiring 60 connected to the first circuit 30 and the second circuit 40, which can reduce the resistance of the wiring 61.

As shown in fig. 4, in two pixel units 10 (hereinafter, referred to as "first pixel unit" and "second pixel unit") adjacent (in the up-down direction in fig. 4), the gate electrodes of the plurality of first transistors 3 of the first pixel unit and the gate electrode of the second transistor 4 of the second pixel unit are arranged side by side in the first direction D1 (see the arrangement of the gate electrodes 340, 310, 320, 330, 350, and 410 shown in fig. 4). The gate electrodes of the plurality of first transistors 3 of the first pixel unit and the gate electrode of the second transistor 4 of the second pixel unit include: two gate electrodes (gate electrodes 340, 410) of the transistor located at both ends in the first direction D1; and gate electrodes of the remaining transistors. The gate electrodes of the remaining transistors are located at any of virtual points that divide a line segment connecting the two gate electrodes of the transistors located at both ends in the first direction D1 equally. With this arrangement, the first pixel cell and the second pixel cell can be formed such that the diffusion regions 50 to 55 of the first circuit 30 of the first pixel cell and the diffusion regions 56, 57 of the second circuit 40 of the second pixel cell are arranged side by side in the first direction D1. Further, the gate electrodes of the plurality of first transistors 3 of the first pixel unit and the gate electrode of the second transistor 4 of the second pixel unit may be arranged side by side in the first direction D1.

Further, in the example shown in fig. 4, the gate electrodes of the plurality of first transistors 3 of the second pixel unit are arranged side by side with the gate electrode of the second transistor 4 of the first pixel unit along the first direction D1. The gate electrodes of the plurality of first transistors 3 of the second pixel unit and the gate electrode of the second transistor 4 of the first pixel unit include: two gate electrodes (gate electrodes 340, 410) of the transistor located at both ends in the first direction D1; and gate electrodes of the remaining transistors. The gate electrodes of the remaining transistors are located at any of virtual points that divide a line segment connecting the two gate electrodes of the transistors located at both ends in the first direction D1 equally. With this arrangement, the first pixel cell and the second pixel cell can be formed such that the diffusion regions 50 to 55 of the first circuit 30 of the second pixel cell and the diffusion regions 56, 57 of the second circuit 40 of the first pixel cell are arranged side by side in the first direction D1. Further, the gate electrodes of the plurality of first transistors 3 of the second pixel unit and the gate electrode of the second transistor 4 of the first pixel unit may be arranged side by side in the first direction D1. This makes it possible to arrange the first circuit 30 and the second circuit 40 of the first pixel unit close to the second circuit 40 and the first circuit 30 of the second pixel unit, and to arrange the first circuit 30 and the second circuit 40 of the first pixel unit and the first circuit 30 and the second circuit 40 of the second pixel unit in a small area.

In the embodiment, the gate electrodes 310 to 350 of the plurality of first transistors 3 of the first pixel unit are equally spaced in the first direction D1. When the length of the interval between the centers of the gate electrodes of the first transistors 3 adjacent in the first direction D1 is defined as "a 1", the length of the interval between the center of the gate electrode 410 of the second transistor 4 of the second pixel unit and the center of the gate electrode (340 or 350) of the first transistor 3 of the first pixel unit adjacent in the first direction D1 in the first direction D1 is twice the above-described interval length "a 1" (i.e., 2 × a 1).

Further, the gate electrodes 310 to 350 of the plurality of first transistors 3 of the second pixel unit are arranged at equal intervals in the first direction D1. When the length of the interval between the centers of the gate electrodes of the first transistors 3 adjacent in the first direction D1 is defined as "a 2", the length of the interval between the center of the gate electrode 410 of the second transistor 4 of the first pixel unit and the center of the gate electrode (340 or 350) of the first transistor 3 of the second pixel unit adjacent in the first direction D1 in the first direction D1 is twice the above-described interval length "a 2" (i.e., 2 × a 2). In an embodiment, length "a 1" and length "a 2" are equal to each other.

In a modification, a dummy member made of, for example, a gate electrode material may be provided on a region surrounded by a dotted line shown in fig. 4 or 5.

(2) Modification examples

The above-described embodiments are merely examples of various embodiments of the present disclosure. The above-described embodiments may be modified in various ways according to design and the like as long as the object of the present disclosure can be achieved.

As shown in fig. 6, in the solid-state imaging device 1 of one modification, the first diffusion region 50 and the second diffusion region 56 in the pixel unit 10 may be connected by a diffusion layer wiring 58 formed in the semiconductor substrate 100. The diffusion layer wiring 58 includes an n-type diffusion region formed in the p-type well region 9. The diffusion layer wiring 58 has a first end connected to the first diffusion region 50 and a second end connected to the second diffusion region 56. Specifically, the first diffusion region 50, the second diffusion region 56, and the diffusion layer wiring 58 may be integrally formed.

As shown in fig. 7, in the solid-state imaging device 1 of one modification, two pixel cells 10 may be arranged to face each other with the p-type well region 9 interposed therebetween such that the ends of the light receiving portions 2 of the respective two pixel cells 10 in the first direction D1 are located on the same straight line extending in the second direction D2. In this case, the light receiving sections 2 of the plurality of pixel units 10 may be arranged in a matrix arrangement.

The pixel cell 10 may not include the second reset transistor 34. The pixel cell 10 may not include the selection transistor 35.

The pixel cell 10 may be configured such that the second diffusion region 56 does not face the first diffusion region 50 in the second direction D2. Such an arrangement that the second diffusion region 56 is separated from the plurality of first transistors 3 in the second direction D2 without facing the first diffusion region 50 can reduce the length of the wiring 61 (or the diffusion layer wiring 58) connecting the first diffusion region 50 and the second diffusion region 56, as compared with the case where the second transistor 4 is arranged side by side with the plurality of first transistors 3 in the first direction D1.

The controller of the solid-state imaging device 1 may be configured to control the pixel unit 10 to operate only in the second reception mode, and not to operate in the first reception mode.

The impurity diffusion regions of the first transistor 3 and the second transistor 4 may be p-type conductivity characteristics. For example, the impurity diffusion regions of the first transistor 3 and the second transistor 4 may be p-type diffusion regions formed in an n-type well region.

(3) Summary of the invention

As is apparent from the above-described embodiments and modifications, the present invention discloses the following aspects.

A solid-state imaging device (1) of a first aspect includes a plurality of pixel units (10) formed in a semiconductor substrate (100) and arranged in a two-dimensional array. At least one pixel unit (10) of the plurality of pixel units (10) includes a light receiving section (2), a pixel circuit (30), and a second transistor (4). The light receiving section (2) is configured to receive incident light to generate electric charges. The pixel circuit (30) includes a plurality of first transistors (3) and a charge holding portion (5) arranged side by side in a first direction (D1). The charge holding portion (5) is configured to hold a charge generated by the light receiving portion (2). The pixel circuit (30) is configured to output a light reception signal according to the electric charge generated by the light receiving section (2). The second transistor (4) connects the charge holding portion (5) to a memory portion (6) configured to store charge. In a plan view viewed in a thickness direction of the semiconductor substrate (100), the pixel unit (10) is configured such that the second transistor (4) is separated from the plurality of first transistors (3) in a second direction, the second direction (D2) being orthogonal to the first direction (D1).

This aspect can reduce the length of the wiring (61) connecting the second transistor (4) to the charge holding portion (5) as compared with the case where the second transistor (4) is placed side by side with the plurality of first transistors (3) in the first direction (D1). This can reduce the parasitic capacitance of the wiring (61) to achieve high gain and high sensitivity of photoelectric conversion. This can also reduce the parasitic resistance of the wiring (61) to achieve high responsiveness to charge transfer. Further, the adjacent pixel cells (10) are arranged such that the first circuit (30) of one pixel cell (10) and the second circuit (40) of the other pixel cell (10) are disposed close to each other, which can achieve high integration.

The solid-state imaging device (1) of the second aspect is based on the first aspect. In a second aspect, a pixel unit (10) is configured as follows. The charge holding portion (5) includes a diffusion region (50) having a floating potential. The plurality of first transistors (3) include a transfer transistor (31) configured to transfer charges generated by the light receiving portion (2) to the diffusion region (50), a reset transistor (32) configured to reset the charges stored in the diffusion region (50), and an amplifier transistor (33) having a gate electrode (330) electrically connected to the diffusion region (50).

According to this aspect, a pixel circuit (30) including a transfer transistor (31), a reset transistor (32), and an amplifier transistor (33) can generate a light receiving signal according to light received by a light receiving portion (2).

The solid-state imaging device (1) of the third aspect is based on the second aspect. In a third aspect, a pixel unit (10) is configured as follows. The diffusion region (50) is a first diffusion region (50). The second transistor (4) includes a second diffusion region (56) having a floating potential. The first diffusion region (50) and the second diffusion region (56) are connected to each other. At least a portion of the first diffusion region (50) and at least a portion of the second diffusion region (56) overlap each other when viewed along the second direction (D2).

This aspect can reduce the direct distance between the first diffusion region (50) and the second diffusion region (56), thereby reducing the length of the wiring (61) connecting the first diffusion region (50) and the second diffusion region (56) to reduce the parasitic capacitance of the wiring (61).

The solid-state imaging device (1) of the fourth aspect is based on the third aspect. In a fourth aspect, the pixel cell (10) is configured such that the entirety of one of the first diffusion region (50) and the second diffusion region (56) overlaps the other of the first diffusion region (50) and the second diffusion region (56) when viewed in the second direction (D2).

According to this aspect, the entire length of the side of one diffusion region of the first diffusion region (50) and the second diffusion region (56) can be connected to the side of the other diffusion region. This can increase the width of the wiring connecting the first diffusion region (50) and the second diffusion region (56) to reduce the resistance of the wiring.

The solid-state imaging device (1) of the fifth aspect is based on the third or fourth aspect. In a fifth aspect, a pixel unit (10) is configured such that a first diffusion region (50) and a second diffusion region (56) are connected to each other by a metal wiring (61).

According to this aspect in which the first diffusion region (50) and the second diffusion region (56) are connected by the wiring layer, each of the first diffusion region (50) and the second diffusion region (56) can be shaped into a simple rectangle, which can reduce individual fluctuations in characteristics caused by the manufacturing process.

The solid-state imaging device (1) of the sixth aspect is based on the third or fourth aspect. In a sixth aspect, a pixel cell (10) is configured such that a first diffusion region (50) and a second diffusion region (56) are connected to each other through a diffusion layer wiring (58) formed in a semiconductor substrate (100).

According to this aspect in which the first diffusion region (50) and the second diffusion region (56) are connected by the diffusion layer wiring (58), the parasitic capacitance per unit length of the connection portion is reduced as compared with the case of connecting using the wiring layer.

The solid-state imaging device (1) of the seventh aspect is based on any one of the first to sixth aspects. In a seventh aspect, a pixel unit (10) is configured as follows. Each of the first transistors (3) has a gate electrode. The gate electrodes of the plurality of first transistors 3 are arranged side by side in the first direction (D1). The plurality of first transistors (3) includes first transistors (3) located at both ends in the first direction (D1), and the remaining first transistors (3). The gate electrodes of the remaining first transistors (3) are located at any of virtual points that equally divide a line segment connecting the two gate electrodes of the two first transistors (3) located at both ends in the first direction (D1).

According to this aspect, the gate electrodes of the plurality of first transistors (3) are located at equally spaced virtual points. This can realize an arrangement in which the gate electrodes of the plurality of first transistors (3) are substantially equally spaced, which enables individual fluctuations in characteristics caused by the manufacturing process to be reduced.

The solid-state imaging device (1) of the eighth aspect is based on any one of the first to seventh aspects. In an eighth aspect, a plurality of pixel cells (10) have the same shape as each other in a plan view viewed in a thickness direction of a semiconductor substrate (100).

This aspect allows the wirings (60, 61) of the plurality of pixel cells (10) to have the same shape, which can equalize the lengths of the wirings (60, 61) of the plurality of pixel cells (10) to equalize the parasitic resistances and the parasitic capacitances of the wirings (60, 61).

The solid-state imaging device (1) of the ninth aspect is based on any one of the first to eighth aspects. In a ninth aspect, the plurality of pixel cells (10) includes a first pixel cell and a second pixel cell arranged adjacent to each other in the first direction (D1). The plurality of first transistors (3) of the first pixel unit have gate electrodes, respectively. The second transistor (4) of the second pixel cell has a gate electrode. The gate electrodes of the plurality of first transistors (3) of the first pixel unit and the gate electrode of the second transistor (4) of the second pixel unit are arranged side by side in the first direction. The gate electrodes of the plurality of first transistors (3) of the first pixel unit and the gate electrode of the second transistor (4) of the second pixel unit include two gate electrodes located at both ends in the first direction (D1) and gate electrodes of the remaining transistors. The gate electrodes of the remaining transistors are located at any of virtual points that divide a line segment connecting the two gate electrodes of the transistors located at both ends in the first direction (D1) equally.

According to this aspect, the gate electrodes of the plurality of first transistors (3) of the first pixel unit and the gate electrode of the second transistor (4) of the second pixel unit are located at equally spaced virtual points. This can realize a substantially equally spaced arrangement of the gate electrodes, which enables individual fluctuations in characteristics caused by the manufacturing process to be reduced.

The solid-state imaging device (1) of the tenth aspect is based on any one of the first to ninth aspects. In the tenth aspect, the plurality of pixel units (10) includes two pixel units (10). In a plan view viewed in a thickness direction of the semiconductor substrate (100), the light receiving portion (2) of one of the two pixel units (10) is adjacent to the light receiving portion (2) of the other of the two pixel units (10), or the pixel circuit (30) of one of the two pixel units (10) is adjacent to the pixel circuit (30) of the other of the two pixel units (10).

For example, this aspect may allow the pixel circuits (30) of two pixel cells (10) adjacently arranged in the second direction (D2) to be located in a common well region. For example, this may allow sharing of a well layer between a plurality of pixel cells (10) to achieve high integration, as compared with a case where two pixel cells (10) are arranged in the second direction (D2) such that the light receiving portion (2) of one of the pixel cells (10) and the pixel circuit (30) of the other pixel cell (10) are adjacent to each other.

List of reference numerals

1 solid-state imaging device

10 pixel unit

2 light-receiving part

3 first transistor

30 pixel circuit

31 transfer transistor

32 reset transistor

33 amplifier transistor

330 gate electrode

4 second transistor

5 Charge retention portion

50 diffusion region (first diffusion region)

56 second diffusion region

58 diffusion layer wiring

100 semiconductor substrate

D1 first direction

D2 second direction.