阅读说明：本技术 一种eeprom上电读写保护电路 (EEPROM power-on read-write protection circuit ) 是由 王珊珊 李翔宇 张晓伟 于 2019-11-04 设计创作，主要内容包括：本发明公开了一种EEPROM上电读写保护电路，所述电路包括上电复位电路、基准电压产生电路、比较器、电阻R1、电阻R2、振荡器、计时器、二输入与门1、二输入与门2、反相器等模块。本发明在传统的上电复位电路基础上增加了振荡器、计时器以及一些逻辑电路，不但能够灵活的设定上电延时时间，而且会避免上电过程中反复的掉电带来的EEPROM读写操作风险。本发明可任意控制电源上电过程中EEPROM的读写等待时间，上电过程中和正常供电时的任何异常掉电都能够快速响应，避免EEPROM的异常读写。(The invention discloses an EEPROM power-on read-write protection circuit which comprises a power-on reset circuit, a reference voltage generating circuit, a comparator, a resistor R1, a resistor R2, an oscillator, a timer, a two-input AND gate 1, a two-input AND gate 2, a phase inverter and the like. The invention adds the oscillator, the timer and some logic circuits on the basis of the traditional power-on reset circuit, not only can flexibly set the power-on delay time, but also can avoid the EEPROM read-write operation risk caused by repeated power failure in the power-on process. The invention can arbitrarily control the read-write waiting time of the EEPROM in the power-on process of the power supply, and any abnormal power failure in the power-on process and the normal power supply can quickly respond, thereby avoiding the abnormal read-write of the EEPROM.)

1. A kind of EEPROM powers on and reads and writes the protective circuit, characterized by that the said circuit includes the power on reset circuit, reference voltage generating circuit, comparator, resistance R1, resistance R2, oscillator, timer, two-input AND gate 1, two-input AND gate 2, inverter, wherein:

the power-on reset circuit is connected with a power supply VDD, one output end of the power-on reset circuit is respectively connected with an input end EN _ ref of the reference voltage generating circuit and an input end EN _ cp of the comparator, and the other output end of the power-on reset circuit is connected with one input end of the two-input AND gate 2;

the reference voltage generating circuit is connected with a power supply VDD, and an output voltage port Vr is connected with the input end of the comparator Vin;

one end of the resistor R1 is connected with a power supply VDD, and the other end of the resistor R1 is respectively connected with one end of a resistor R2 and an input end Vip of the comparator;

the other end of the resistor R2 is grounded;

the output end EN of the comparator is respectively connected with one input end of the timer and one input end of the two-input AND gate 1;

the other input end of the two-input AND gate 1 is connected with the output end of the inverter, and the output end of the two-input AND gate 1 is connected with the input end of the oscillator;

the output end clk of the oscillator is connected with the other input end of the timer;

one output end of the timer is connected with the input end of the inverter, and the other output end of the timer is connected with the other input end of the two-input AND gate 2;

and the output end of the two-input AND gate 2 is connected with the EN _ EEPROM.

2. The EEPROM power-on read/write protection circuit of claim 1, wherein the power-on reset circuit is composed of a comparator, an inverter and an RC delay circuit.

3. The EEPROM power-on read/write protection circuit according to claim 1, wherein the reference voltage generating circuit is composed of a bandgap reference and a resistance voltage dividing circuit.

4. The EEPROM power-on read/write protection circuit of claim 1, wherein the comparator is a simple single-stage open-loop op-amp.

5. The EEPROM power-on read/write protection circuit of claim 1, wherein the oscillator circuit is implemented in the form of an RC oscillator or an active crystal oscillator.

6. The EEPROM power-on read/write protection circuit of claim 1, wherein the timer is implemented by a digital register.

Technical Field

The invention belongs to the technical field of integrated circuit design and manufacture, and relates to an EEPROM power-on read-write protection circuit.

Background

The EEPROM power-on read-write protection circuit is generally applied to read-write protection in the power-on and power-off processes of important components such as an EEPROM in a digital-analog hybrid circuit and is commonly used for a power management unit. The power-on abnormity detection device has the functions of identifying power-on abnormity in the power-on process and outputting a power-on abnormity alarm signal to modules such as an EEPROM (electrically erasable programmable read-only memory) and the like in time, so that the read-write protection function is realized. In the normal power-on process, even if the condition of intermediate power failure does not occur, the read-write operation of the EEPROM module should be delayed for a certain time, and corresponding read-write operation is carried out after the power supply voltage is stabilized, so that the accidental damage of the unit is avoided.

The traditional power-on reset and protection circuit has short delay time, and the difference of the reset time along with the process deviation and the change of the power supply voltage temperature is larger. For the situation that the power supply is heavily loaded, the power-on process is slow, and the possibility of power failure due to burst conditions exists in the power-on process, so that the traditional power-on reset and protection circuit is not applicable any more.

Disclosure of Invention

Aiming at the problems in the prior art, the invention provides an EEPROM power-on read-write protection circuit with a simple circuit structure.

The purpose of the invention is realized by the following technical scheme:

a kind of EEPROM is electrified to read and write the protective circuit, including powering on the reset circuit, reference voltage generating circuit, comparator, resistance R1, resistance R2, oscillator, timer, two-input AND gate 1, two-input AND gate 2, inverter, wherein:

the power-on reset circuit is connected with a power supply VDD, one output end of the power-on reset circuit is respectively connected with an input end EN _ ref of the reference voltage generating circuit and an input end EN _ cp of the comparator, and the other output end of the power-on reset circuit is connected with one input end of the two-input AND gate 2;

the reference voltage generating circuit is connected with a power supply VDD, and an output voltage port Vr is connected with the input end of the comparator Vin;

one end of the resistor R1 is connected with a power supply VDD, and the other end of the resistor R1 is respectively connected with one end of a resistor R2 and an input end Vip of the comparator;

the other end of the resistor R2 is grounded;

the output end EN of the comparator is respectively connected with one input end of the timer and one input end of the two-input AND gate 1;

the other input end of the two-input AND gate 1 is connected with the output end of the inverter, and the output end of the two-input AND gate 1 is connected with the input end of the oscillator;

the output end clk of the oscillator is connected with the other input end of the timer;

one output end of the timer is connected with the input end of the inverter, and the other output end of the timer is connected with the other input end of the two-input AND gate 2;

and the output end of the two-input AND gate 2 is connected with the EN _ EEPROM.

The working principle is as follows:

the enabling signal generated by the power-up reset circuit in the power-on process enables the reference voltage generating circuit and the comparator module at the same time, the comparator outputs to control the timer and the oscillator to work, when a certain condition is met, the EEPROM enabling starts to be effective, and the oscillator stops working at the same time.

Compared with the prior art, the invention has the following advantages:

1. the invention adds the oscillator, the timer and some logic circuits on the basis of the traditional power-on reset circuit, not only can flexibly set the power-on delay time, but also can avoid the EEPROM read-write operation risk caused by repeated power failure in the power-on process.

2. The invention can arbitrarily control the read-write waiting time of the EEPROM in the power-on process of the power supply, and any abnormal power failure in the power-on process and the normal power supply can quickly respond, thereby avoiding the abnormal read-write of the EEPROM.

Drawings

FIG. 1 is a schematic block diagram of an EEPROM power-on read-write protection circuit of the present invention.

Detailed Description

The technical solution of the present invention is further described below with reference to the accompanying drawings, but not limited thereto, and any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the protection scope of the present invention.

The invention provides an EEPROM power-on read-write protection circuit, as shown in figure 1, the circuit comprises a power-on reset circuit, a reference voltage generating circuit, a comparator, a resistor R1, a resistor R2, an oscillator, a timer, a two-input AND gate 1, a two-input AND gate 2, an inverter and other modules, wherein:

the power-on reset circuit is connected with a power supply VDD, one output end of the power-on reset circuit is respectively connected with an input end EN _ ref of the reference voltage generating circuit and an input end EN _ cp of the comparator, and the other output end of the power-on reset circuit is connected with one input end of the two-input AND gate 2;

the reference voltage generating circuit is connected with a power supply VDD, and an output voltage port Vr is connected with the input end of the comparator Vin;

one end of the resistor R1 is connected with a power supply VDD, and the other end of the resistor R1 is respectively connected with one end of a resistor R2 and an input end Vip of the comparator;

the other end of the resistor R2 is grounded;

the output end EN of the comparator is respectively connected with one input end of the timer and one input end of the two-input AND gate 1;

the other input end of the two-input AND gate 1 is connected with the output end of the inverter, and the output end of the two-input AND gate 1 is connected with the input end of the oscillator;

the output end clk of the oscillator is connected with the other input end of the timer;

one output end of the timer is connected with the input end of the inverter, and the other output end of the timer is connected with the other input end of the two-input AND gate 2;

and the output end of the two-input AND gate 2 is connected with the EN _ EEPROM.

In the invention, the power-on reset circuit generally comprises a comparator, an inverter and an RC delay circuit.

In the invention, the reference voltage generating circuit consists of a band gap reference and a resistance voltage dividing circuit.

In the present invention, the comparator is typically a simple single-stage open-loop op-amp.

In the invention, the oscillator circuit is realized in the forms of an RC oscillator, an active crystal oscillator and the like.

In the present invention, the timer is generally implemented by a digital register.

The working principle of the circuit is described below with reference to specific examples:

when the power supply voltage VDD is electrified, the power-on reset circuit generates a pulse signal EN _ ref from a low level to a high level, and at the moment, the reference voltage generating circuit starts to work to generate the reference voltage Vr. Meanwhile, the power supply voltage VDD is divided through the resistor R1 and the resistor R2, and the divided voltage Vip is compared with the reference voltage Vr. For example, when the Vr voltage is 1.2V, the power-on stable voltage of the power supply voltage VDD is 5V, and R1/R2 is designed to be 5:3, when the power-on VDD rises to exceed 3.2V, the comparator enable EN signal is high, and the timer starts to count time. When the timing meets the condition set by the user (such as 10 ms), and the VDD is always maintained above 3.2V in the process, the timer outputs high level. At this time, two input signals of the two-input AND gate 2 are both high level, the EN _ EEPROM output is pulled high, the system considers that the power supply is electrified and completed, and the modules such as the EEPROM and the like can normally carry out read-write operation. And meanwhile, the enable output of the timer is processed by the two-input AND gate 1 after being inverted by the inverter, a low-level signal is output, and the oscillator stops working at the moment. Therefore, certain system power consumption can be reduced, and signal interference of pulse signals output by the oscillator on other circuits can be avoided. When abnormal power failure occurs in the power-on process or power failure occurs during stable work after power-on is completed, the output of the power-on reset circuit is pulled down, the output EN signal of the comparator is also pulled down, the output of the timer is pulled down, the output signal EN _ EEPROM of the two-input AND gate 2 is pulled down, modules such as the EEPROM and the like start read-write protection, and the processes are maintained until the power supply is normally powered on next time.

The invention can be applied to a typical heavy-load power supply unit, is used for monitoring and managing the power supply state in a complex electromagnetic environment, can effectively monitor repeated power failure in the power supply electrifying process and abnormal power failure in the normal working process, and plays a real-time read-write protection role for modules such as an EEPROM and the like.