阅读说明：本技术 像素结构 (Pixel structure ) 是由 吴扬 郁飞霞 张宇轩 于 2019-05-30 设计创作，主要内容包括：本发明涉及一种影像传感器的像素结构，包括：基底；结晶层，具有第一掺杂类型且形成在基底之上；光二极管区域，形成在结晶层之中；源极跟随器的栅极，形成在结晶层的上表面上；复位栅极，形成在结晶层的上表面之上；掺杂区，具有第二掺杂类型，形成在结晶层中且形成在复位栅极与源极跟随器的栅极之间。其中第一掺杂类型不同于第二掺杂类型，并且光二极管区域在结晶层的上表面之下连接至掺杂区以形成防渲染路径。(The invention relates to a pixel structure of an image sensor, which comprises: a substrate; a crystallization layer having a first doping type and formed on the substrate; a photodiode region formed in the crystallization layer; a gate of the source follower formed on an upper surface of the crystallization layer; a reset gate formed on the upper surface of the crystallization layer; and a doped region having a second doping type, formed in the crystallization layer and formed between the reset gate and the gate of the source follower. Wherein the first doping type is different from the second doping type, and the photodiode region is connected to the doped region below the upper surface of the crystallization layer to form an anti-render path.)

1. A pixel structure, comprising:

a substrate;

a crystallization layer having a first doping type and formed on the substrate;

a photodiode region formed in the crystalline layer;

a gate of a source follower formed on an upper surface of the crystallization layer;

a reset gate formed on the upper surface of the crystallization layer; and

a doped region having a second doping type formed in the crystallization layer and formed between the reset gate and the gate of the source follower,

wherein the first doping type is different from the second doping type, and the photodiode region is connected to the doped region below the upper surface of the crystallization layer to form an anti-render path.

2. The pixel structure of claim 1, further comprising:

an insulating structure extending from the upper surface of the crystallization layer and formed between the photodiode region and the doped region, wherein the photodiode region is connected to the doped region under the insulating structure.

3. The pixel structure of claim 2, wherein the photodiode region has a first portion having the second doping type and extending below the insulating structure to the doped region, the doped region has a second portion having the second doping type and extending below the insulating structure to the photodiode region, the first portion is connected to the second portion.

4. The pixel structure of claim 3, wherein said doped region comprises a heavily doped region having said second doping type, a lightly doped drain having said second doping type and located under said heavily doped region, and said second portion extending toward said photodiode region.

5. The pixel structure of claim 4, wherein the second portion has a doping concentration less than a doping concentration of the low-concentration doped drain.

6. The pixel structure of claim 3, further comprising:

a well region having the first doping type and formed in the crystalline layer,

wherein the well region has a recess to at least partially surround the first portion and the second portion.

7. The pixel structure of claim 6, wherein said well region is vertically spaced a distance from a connecting interface between said first portion and said second portion.

8. The pixel structure of claim 6, wherein the width of the recess is less than the distance between the reset gate and the gate of the source follower.

9. The pixel structure of claim 1, wherein said first doping type is P-type and said second doping type is N-type.

10. The pixel structure of claim 1 wherein said doped region is connected to a power supply voltage.

Technical Field

The invention relates to a pixel structure with an anti-rendering path.

Background

CMOS (complementary metal-oxide-semiconductor) image sensors are widely used in mobile applications. CMOS image sensors may also be used in other applications, such as automotive and security systems, where the requirements are not the same as those for mobile applications. For example, in automotive and security applications, the rendering (blooming) is highly unacceptable, which occurs when a pixel is exposed, the pixel is filled with photon carriers and the hole collection can no longer be continued, when a bright pixel is spread to several other pixels in the neighborhood.

Road scenes, especially at night, have a high dynamic range. Therefore, the CMOS image sensor needs to have good rendering control in the super bright area to ensure that the adjacent dark area is not affected by rendering charge to become white, otherwise much detail is lost and it becomes difficult to extract information from the scene. In addition, in high temperature operation such as automotive, one hot pixel is easily filled with dark current even in the dark, so that the adjacent good pixels may become hot due to receiving a render charge.

Since the conventional CMOS image sensor cannot solve the rendering problem, a new CMOS image sensor having better anti-rendering capability is required.

Disclosure of Invention

An embodiment of the invention provides a pixel structure, which includes a substrate, a crystallization layer, a photodiode region, a gate of a source follower, a reset gate, and a doped region. The crystallization layer has a first doping type and is formed on the substrate. The photodiode region is formed in the crystalline layer. The gate of the source follower is formed on the upper surface of the crystallization layer. The reset gate is formed on the upper surface of the crystallization layer. The doped region has a second doping type, is formed in the crystallization layer and is formed between the reset gate and the gate of the source follower. The first doping type is different from the second doping type, and the photodiode region is connected to the doping region below the upper surface of the crystallization layer to form a rendering-preventing path.

In some embodiments, the pixel structure further includes an insulating structure extending from the upper surface of the crystallization layer and formed between the photodiode region and the doped region, wherein the photodiode region is connected to the doped region under the insulating structure.

In some embodiments, the photodiode region has a first portion having the second doping type and extending below the insulating structure to the doped region. The doped region has a second portion with a second doping type extending below the insulating structure to the photodiode region, the first portion being connected to the second portion.

In some embodiments, the doped region includes a heavily doped region, a lightly doped drain, and a second portion. The heavily doped region has a second doping type, the lightly doped drain has the second doping type and is located under the heavily doped region, and the second portion extends toward the photodiode region.

In some embodiments, the doping concentration of the second portion is less than the doping concentration of the low-concentration doped drain.

In some embodiments, the pixel structure further includes a well region having the first doping type and formed in the crystallization layer. The well region has a recess to at least partially surround the first portion and the second portion.

In some embodiments, the well region is vertically spaced apart from the connection interface between the first portion and the second portion.

In some embodiments, the width of the recess is less than the distance between the reset gate and the gate of the source follower.

In some embodiments, the first doping type is a P-type and the second doping type is an N-type.

In some embodiments, the doped region is connected to a power supply voltage.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 shows a circuit schematic of a pixel circuit according to an embodiment.

Fig. 2A illustrates a top view of a pixel structure according to an embodiment.

Fig. 2B shows a cross-sectional view along the cross-sectional line AA' in fig. 2A.

FIG. 3A illustrates a cross-sectional view of a portion of a pixel structure according to one embodiment.

Fig. 3B is a top view of a portion of the pixel structure shown along a tangent line BB' in fig. 3A.

Fig. 3C is a top view of a portion of the pixel structure shown along the tangent line CC' in fig. 3A.

Fig. 3D is a top view of a portion of the pixel structure shown along a cut line DD' in fig. 3A.

Fig. 4 shows a top view of a pixel structure according to an embodiment.

Fig. 5A-5C illustrate cross-sectional views of portions of pixel structures according to some embodiments.

Detailed Description

Fig. 1 shows a circuit schematic of a pixel circuit according to an embodiment. Referring to fig. 1, the image sensor 100 can be applied to Front Side Illumination (FSI) or Back Side Illumination (BSI) image sensors. The image sensor 100 includes a photodiode 110, a conversion transistor TX, a reset transistor RES, a source follower SF, and a selection transistor SEL. The anode of the photodiode 110 is grounded, and the cathode is electrically connected to the first terminal of the converting transistor TX. A second terminal of the transfer transistor TX is electrically connected to the first terminal of the reset transistor RES and the gate of the source follower SF. The second terminal of the reset transistor RES is electrically connected to the power voltage VDD. The first terminal of the source follower SF is electrically connected to the power voltage VDD, and the second terminal is electrically connected to the first terminal of the selection transistor SEL. The second terminal of the selection transistor SEL is electrically connected to the bias current source 130 and outputs to the sensing circuit 140. In this embodiment, an anti-render path 120 is provided from the photodiode 110 to the power supply voltage VDD, and a pixel structure will be described in detail below.

Fig. 2A shows a top view of a pixel structure according to an embodiment, and fig. 2B shows a cross-sectional view along a cross-sectional line AA' in fig. 2A. Referring to fig. 2A and 2B, the image sensor 100 includes a substrate 201, wherein the substrate 201 has a first doping type (e.g., P-type). A crystalline layer 202 is formed on the substrate 201, and the crystalline layer 202 has a first doping type, such as a P-type epitaxial layer. The photodiode regions 203 and 214 and a well PW are formed in the crystallization layer 202, wherein the well PW has a first doping type. The photodiode region 203 belongs to one pixel in the image sensor 100, and the photodiode region 214 belongs to another pixel adjacent to the pixel. The upper surface 202a of the crystallization layer 202 is further provided with a surface pinning layer (210) and a gate insulating layer 211, and the gate insulating layer 211 includes an oxide, for example. Insulating structures 212, 213 are disposed in the crystalline layer 202, wherein the insulating structure 212 is disposed between the photodiode region 203 and the photodiode region 214. For example, the isolation structures 212 and 213 are Shallow Trench Isolations (STI). In some embodiments, the insulating structure 212 further has a deeper well region 215 having the first doping type.

A gate TX _ G (also referred to as a transfer gate) of the transfer transistor TX, a gate RES _ G (also referred to as a reset gate) of the reset transistor RES, a gate SF _ G of the source follower SF, and a gate SEL _ G (also referred to as a select gate) of the select transistor SEL are disposed over the gate insulating layer 211, and these gates are not shown in fig. 2B. The gate TX _ G covers a portion of the photodiode region 203. Doped regions 204, 206, 207 are formed in the crystallization layer 202. The doped region 204 is disposed between the transfer gate TX _ G and the reset gate RES _ G and serves as a source/drain of the transfer transistor TX and the reset transistor RES, and the doped region 204 is also electrically connected to the gate SF _ G through the conductive structure 205. The doped region 206 is disposed between the reset gate RES _ G and the gate SF _ G, and serves as a source/drain of the reset transistor RES and the source follower SF. The doped region 207 is disposed between the gate SF _ G and the select gate SEL _ G, and serves as a source/drain of the source follower SF and the select transistor SEL. The doped regions 204, 206, 207 have a second doping type (e.g., N-type), which is different from the first doping type.

Specifically, the photodiode region 203 and the doped region 206 are connected to each other under the upper surface 202a of the crystallization layer 202, thereby providing the anti-rendering path 120. Specifically, the insulating structure 213 extends downward from the upper surface 202a of the crystallization layer 202 and is formed between the photodiode region 203 and the doped region 206. The photodiode region 203 has a first portion 221, the first portion 221 having a second doping type (e.g. N-type) and extending below the insulating structure 213 in a direction of the doped region 206. On the other hand, the doped region 206 has a second portion 222, and the second portion 222 has the second doping type and extends below the insulating structure 213 toward the photodiode region 203. The first portion 221 and the second portion 222 are connected to each other under the insulating structure 213, in other words, the photodiode region 203 and the doped region 206 are connected to each other under the insulating structure 213. It is noted that the first portion 221 and the second portion 222 are shielded by the insulating structure 213 in fig. 2A, and thus are depicted as dashed lines.

In some embodiments, the doped region 206 has a highly doped region 224, a low-doped drain 223 below the highly doped region 224, and the second portion 222, and the low-doped drain 223, the highly doped region 224, and the highly doped region 224 all have the second doping type. In some embodiments, the second portion 222 is formed by thermal diffusion, such that the doping concentration of the second portion 222 is lower than that of the heavily doped region 224, and the doping concentration of the second portion 222 is lower toward the photodiode region 203. Thus, it can be appreciated that in some embodiments there is no clear boundary between the low-doped drain 223 and the second portion 222. Since the first portion 221 and the second portion 222 have the same doping type and are connected to each other, the energy barrier between the photodiode region 203 and the doped region 206 is lower than the energy barrier between the photodiode region 203 and the photodiode region 214. Referring to fig. 1 and 2B, the doped region 206 is connected to the power voltage VDD, and when the photodiode region 203 is over-exposed, the excess charges can flow to the power voltage VDD through the anti-blooming path 120 and not flow to the adjacent photodiode region 214. In some embodiments, the depth of the heavily doped region 224 can be controlled, and as the depth is larger, the energy barrier between the first portion 221 and the second portion 222 is also reduced. In some embodiments, the depth of the insulating structure 213 can also be controlled, and as the depth is larger, the energy barrier between the first portion 221 and the second portion 222 is increased.

Fig. 3A is a cross-sectional view illustrating a partial pixel structure according to an embodiment, where fig. 3A and fig. 2B are the same but some symbols are replaced for the sake of illustration, fig. 3B is a top view of the partial pixel structure illustrated along a tangent line BB ' in fig. 3A, fig. 3C is a top view of the partial pixel structure illustrated along a tangent line CC ' in fig. 3A, and fig. 3D is a top view of the partial pixel structure illustrated along a tangent line DD ' in fig. 3A. Referring to fig. 3A, in some embodiments, the well PW has a recess surrounding the first portion 221 and the second portion 222. Specifically, in the prior art, the well region PW occupies the space under the insulating structure 213 (similar to the deep well region 215), but in this embodiment, the well region PW is designed with a recess 320, the recess 320 has a height H, and the well region PW is vertically separated from the connection interface 310 between the first portion 221 and the second portion 222 by a distance D1. Referring to fig. 3B, from the top view, the recess 320 of the well PW partially surrounds the first portion 221 and the second portion 222 on three sides, i.e., above, right, and below, and the recess 320 has a width W and a length L. Referring to fig. 3C, from the top view, the recess 320 of the well PW is filled with the crystalline layer 202. Referring to fig. 3D, the groove 320 is not visible in fig. 3D.

It is understood that the height H, width W, and length L of the groove 320, as well as the distance D1, can be designed to have different values according to the needs. Generally, the larger the height H, width W, and length L, as well as the distance D1, the lower the energy barrier formed by the first portion 221 and the second portion 222, thereby creating a more efficient anti-render path 120.

Fig. 4 shows a top view of a pixel structure according to an embodiment. Fig. 4 is substantially the same as fig. 2A, but for illustrative purposes the extent of well region PW is shown in fig. 4, and it is noted that well region PW is buried in crystalline layer 202 and is "hidden" from view in a top view. In fig. 4, recess 320 of well PW has width W and length L. This width W is smaller than the distance D2 between the reset gate RES _ G and the gate SF _ G, but if a stronger anti-rendering capability is required, the groove 320 may extend down into the channel region between the reset gate RES _ G and the gate SF _ G as long as the operation of the reset gate RES _ G and the gate SF _ G is not affected.

In some embodiments, in addition to forming the first portion 221 and the second portion 222 in the photodiode 203 and the doped region 206, respectively (mainly by thermal diffusion), an implanted region of the second doping type may also be formed in the crystallization layer 202, thereby adjusting the anti-rendering capability. For example, referring to fig. 5A, the implantation region 510 is formed under the insulation structure 213, and between the photodiode region 203 and the doped region 206, the implantation region 510 also contacts the photodiode region 203 and the doped region 206, thereby providing an anti-rendering path. Referring to fig. 5B, an implant region 520 is formed under the isolation structure 213, but unlike fig. 5A, the implant region 520 extends toward the photodiode region 203 and mixes with the implantation of the photodiode 203 region. In some embodiments, the implanted region 520 is in contact with the crystallized layer 202. Referring to fig. 5C, an implantation region 530 is partially formed in the recess 320 and simultaneously contacts the doped region 206 and the well region PW, and the implantation region 530 is an additional region outside the doped region 206. It is noted that the length, width, height, and forming position of the implantation regions 510, 520, 530 can be adjusted according to the requirement, and the invention is not limited thereto.

In another aspect, some embodiments also provide an electronic device having the image sensor 100 and the pixel structure. The electronic device may be a smart phone, various types of computers, a digital camera, etc., and the invention is not limited thereto.

In some embodiments, the first doping type may also be an N type, and the second doping type may also be a P type.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.