阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 马书英 郑凤霞 刘轶 金韶 万石保 于 2019-11-15 设计创作，主要内容包括：本发明提供一种半导体器件及其制造方法，其中，所述半导体器件制造方法包括如下步骤：S1、在硅基片的正面开设需求数量的槽体；S2、将第一芯片、第二芯片的晶圆减薄到需求厚度；S3、将第一芯片、第二芯片分别固定于开设的槽体中；S4、在第一芯片、第二芯片表层的阻焊层上设置焊点；S5、将硅基片的背面进行减薄，再第三芯片以倒装方式焊接于设置的焊点上。本发明的半导体器件制造方法中，将第一芯片和第二芯片通过硅基片进行封装，并通过倒装方式实现第三芯片与第一芯片和第二芯片之间互连，最终封装厚度小于600um，实现了超薄、更小体积的封装，且实现三维互连，信号传输距离更远、更快。(The invention provides a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: s1, arranging a required number of groove bodies on the front surface of the silicon substrate; s2, thinning the wafers of the first chip and the second chip to the required thickness; s3, fixing the first chip and the second chip in the groove respectively; s4, arranging welding spots on the solder mask layers on the surface layers of the first chip and the second chip; and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the arranged welding points in a flip-chip mode. According to the manufacturing method of the semiconductor device, the first chip and the second chip are packaged through the silicon substrate, the third chip is connected with the first chip and the second chip in an inverted mode, the final packaging thickness is smaller than 600 micrometers, ultrathin packaging with smaller volume is achieved, three-dimensional interconnection is achieved, and the signal transmission distance is longer and faster.)

1. A semiconductor device manufacturing method, characterized by comprising the steps of:

s1, arranging a required number of groove bodies on the front surface of the silicon substrate;

s2, thinning the wafers of the first chip and the second chip to the required thickness;

s3, fixing the first chip and the second chip in the groove respectively;

s4, arranging welding spots on the solder mask layers on the surface layers of the first chip and the second chip;

and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the arranged welding points in a flip-chip mode.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step S2 specifically includes: firstly, the wafers of the first chip and the second chip are thinned to the required thickness, and then the thinned wafers are cut to form single chips.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the step S2 specifically includes: cutting to form a single chip, and thinning the wafer of the single first chip and the single second chip to the required thickness.

4. The method for manufacturing a semiconductor device according to claim 1, wherein in the step S3, the first chip and the second chip are adhered to the bottom surface of the groove body by means of adhesive.

5. The semiconductor device manufacturing method according to any one of claims 1 to 4, wherein in step S3, a passivation layer is formed on the surfaces of the first chip and the second chip and the gaps between the first chip and the groove, and the bonding positions of the chips are formed on the passivation layer.

6. The semiconductor device manufacturing method according to any one of claims 1 to 4, further comprising, between the steps S3 and S4: and the signals of the first chip and the second chip are led out in a rewiring mode.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the rewiring is a metal rewiring including: and depositing a seed layer at the welding position of the first chip and the second chip, photoetching a circuit, and thickening the metal circuit to the required thickness.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the rewiring is a multilayer metal rewiring comprising: and depositing a seed layer by layer at the welding position of the first chip and the second chip, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode.

9. The semiconductor device manufacturing method according to claim 1, further comprising:

and S6, cutting the product obtained in the step S5 to obtain single packaging bodies, and welding the single packaging bodies to the PCB in a routing mode.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the first chip is an ISP chip, the second chip is a DDR chip, and the third chip is a CMOS chip.

11. A semiconductor device obtained by the semiconductor device manufacturing method according to any one of claims 1 to 10, characterized in that the overall package thickness of the semiconductor device is less than 600 um.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.

Background

The image sensor utilizes the photoelectric conversion function of the photoelectric device. The light image on the light sensing surface is converted into an electric signal in corresponding proportion to the light image. In contrast to the photosensitive elements of "point" light sources such as photodiodes, phototransistors, etc., image sensors are functional devices that divide the light image on their light-receiving surface into many small cells and convert it into usable electrical signals.

The chip related to the image sensing technology includes: CMOS chips, ISP chips and DDR chips. At present, the image sensor package is to place the CMOS chip, the ISP chip and the DDR chip on the PCB. However, in the above-mentioned packaging method, the signal is led out by a wire bonding method, and the conventional packaging method of the image sensor has the problems of large packaging volume and thick packaging thickness. Therefore, it is necessary to provide a further solution to the above-mentioned problems.

Disclosure of Invention

The present invention is directed to a semiconductor device and a method for manufacturing the same to overcome the disadvantages of the prior art.

In order to solve the technical problems, the technical scheme of the invention is as follows:

a semiconductor device manufacturing method, comprising the steps of:

s1, arranging a required number of groove bodies on the front surface of the silicon substrate;

s2, thinning the wafers of the first chip and the second chip to the required thickness;

s3, fixing the first chip and the second chip in the groove respectively;

s4, arranging welding spots on the solder mask layers on the surface layers of the first chip and the second chip;

and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the arranged welding points in a flip-chip mode.

As a manufacturing method of the semiconductor device manufacturing method of the present invention, the step S2 specifically includes: firstly, the wafers of the first chip and the second chip are thinned to the required thickness, and then the thinned wafers are cut to form single chips.

As a manufacturing method of the semiconductor device manufacturing method of the present invention, the step S2 specifically includes: cutting to form a single chip, and thinning the wafer of the single first chip and the single second chip to the required thickness.

In the manufacturing method of the semiconductor device manufacturing method according to the present invention, in step S3, the first chip and the second chip are adhered to the bottom surface of the groove by using an adhesive.

As a manufacturing method of the semiconductor device manufacturing method of the present invention, in step S3, a passivation layer is formed on the surfaces of the first chip and the second chip and the gaps between the first chip and the groove, and the bonding position of the chip is formed on the passivation layer.

As a manufacturing method of the semiconductor device manufacturing method of the present invention, between the steps S3 and S4, the method further includes: and the signals of the first chip and the second chip are led out in a rewiring mode.

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, wherein the rewiring is a metal rewiring, the method including: and depositing a seed layer at the welding position of the first chip and the second chip, photoetching a circuit, and thickening the metal circuit to the required thickness.

The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device, wherein the rewiring is a multilayer metal rewiring including: and depositing a seed layer by layer at the welding position of the first chip and the second chip, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode.

As a manufacturing method of a semiconductor device manufacturing method of the present invention, the semiconductor device manufacturing method further includes:

and S6, cutting the product obtained in the step S5 to obtain single packaging bodies, and welding the single packaging bodies to the PCB in a routing mode.

In the method for manufacturing a semiconductor device according to the present invention, the first chip is an ISP chip, the second chip is a DDR chip, and the third chip is a CMOS chip.

In order to solve the technical problems, the technical scheme of the invention is as follows:

a semiconductor device obtained by the semiconductor device manufacturing method as described above, the semiconductor device having an overall package thickness of less than 600 um.

Compared with the prior art, the invention has the beneficial effects that: according to the manufacturing method of the semiconductor device, the first chip and the second chip are packaged through the silicon substrate, the third chip is connected with the first chip and the second chip in an inverted mode, the final packaging thickness is smaller than 600 micrometers, ultrathin packaging with smaller volume is achieved, three-dimensional interconnection is achieved, and the signal transmission distance is longer and faster.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 to 4 are process diagrams illustrating a method for manufacturing a semiconductor device according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The semiconductor device manufacturing method of the present invention can be applied to packaging of a semiconductor device having three or more chips. For example, it is applicable to an ultra-thin package of an image sensor. Wherein the image sensor includes: the CMOS chip, the ISP chip and the DDR chip realize ultrathin packaging with smaller volume, three-dimensional interconnection and longer and faster signal transmission distance by the manufacturing method of the semiconductor device.

The semiconductor device manufacturing method of the present invention includes the steps of:

s1, arranging a required number of groove bodies on the front surface of the silicon substrate;

s2, thinning the wafers of the first chip and the second chip to the required thickness;

s3, fixing the first chip and the second chip in the groove respectively;

s4, arranging welding spots on the solder mask layers on the surface layers of the first chip and the second chip;

and S5, thinning the back surface of the silicon substrate, and then welding the third chip on the arranged welding points in a flip-chip mode.

With respect to the above steps, the following description is made of the technical solution of the package of the image sensor in combination with the embodiment of the image sensor.

As shown in fig. 1, step S1 is directed.

A groove body 11 is etched on the front surface of the silicon substrate 1 in an etching mode, and the groove depth can be etched to different depths according to the packaging requirements. The number of the troughs 11 is determined by the number of the embedded ISP chips and DDR chips.

As shown in fig. 2, step S2 is addressed.

The wafers of the ISP chip 2 and the DDR chip 3 are thinned to a required thickness, and two parallel embodiments can be specifically adopted.

In one embodiment, the ISP chip 2 and the DDR chip 3 are thinned to a required thickness, and then the thinned wafer is cut into single chips. In another embodiment, a single chip is formed by cutting, and then the wafer of the single ISP chip 2 and the single DDR chip 3 is thinned to a required thickness. Through the processing mode of above-mentioned attenuate, cutting, be favorable to realizing that final encapsulation thickness is less than 600 um.

Step S3 is directed.

The ISP chip 2 and the DDR chip 3 are adhered to the bottom surface of the groove body 11 in an adhesive way. The above-mentioned bonding can be achieved, for example, by means of a DAF film or a stamp,

the step S3 further includes: and forming a passivation layer 4 on the surfaces of the ISP chips 2 and the DDR chips 3 and the gaps between the ISP chips 2 and the DDR chips 3 and the groove bodies 11, and forming a welding position of the chips on the passivation layer 4. For example, the passivation layer 4 is formed on the chip surface by vacuum lamination, the gap between the chip and the slot 11 is filled, and the bonding position of the chip is opened by exposure and development.

Further, between the steps S3 and S4, the method further includes: signals of the ISP chip 2 and the DDR chip 3 are led out in a rewiring mode.

In one embodiment, the rewiring is a metal rewiring, which includes: and depositing a seed layer 5, such as Ti/Cu, Al and the like, at the welding position of the ISP chip 2 and the DDR chip 3, photoetching a circuit, and thickening the metal circuit to the required thickness.

In another embodiment, for a product with a high density of I/O interfaces, a multi-layer wiring scheme may be used. In this case, the rewiring method is a multilayer metal rewiring including: and depositing a seed layer 5 layer by layer at the welding position of the ISP chip 2 and the DDR chip 3, photoetching a circuit while depositing, and forming a protective layer on the last layer of circuit by adopting a chemical plating mode to prevent the corrosion of the metal circuit.

Step S4 is directed. The solder resist layer 6 is formed on the surface layer of the chip for the purpose of preventing moisture from entering.

As shown in fig. 3, step S5 is addressed. When the CMOS chip 7 is welded on the arranged welding point in an inverted mode, the ultra-thin glass 100 and 200um are used for bonding, ultra-thin packaging is realized through the TSV technology, and the total packaging thickness is smaller than 600 um.

As shown in fig. 4, the semiconductor device manufacturing method further includes:

and S6, cutting the product obtained in the step S5 to obtain single packages, and welding the single packages to the PCB 8 in a routing manner.

The invention also provides a semiconductor device based on the manufacturing method of the semiconductor device.

At this time, the semiconductor device is obtained by the semiconductor device manufacturing method as described above, and the overall package thickness of the semiconductor device is less than 600 um. When the first chip is an ISP chip, the second chip is a DDR chip, the third chip is a CMOS chip, and the semiconductor device is an image sensor.

In summary, in the manufacturing method of the semiconductor device of the present invention, the first chip and the second chip are packaged by the silicon substrate, and the third chip and the first chip and the second chip are interconnected by the flip chip, and the final package thickness is smaller than 600um, so that the ultrathin and smaller package is realized, the three-dimensional interconnection is realized, and the signal transmission distance is longer and faster.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.