Thyristor and manufacturing method thereof
阅读说明:本技术 晶闸管及其制造方法 (Thyristor and manufacturing method thereof ) 是由 张环 朱迺茜 周继峰 于 2019-11-29 设计创作,主要内容包括:公开了一种晶闸管及其制造方法,该晶闸管包括N型衬底,所述N型衬底具有第一表面和与所述第一表面相反的第二表面;P型掺杂层,所述P型掺杂层形成于所述N型衬底的所述第一表面和/或第二表面上;沟槽,所述沟槽从所述P型掺杂层的远离所述N型衬底的表面贯穿所述P型掺杂层并延伸到所述衬底内;以及玻璃钝化保护层,所述玻璃钝化保护层形成在所述沟槽内;其中,所述P型掺杂层、所述N型衬底和所述玻璃钝化保护层之间形成有薄氧层,所述薄氧层和所述玻璃钝化保护层之间形成有半绝缘多晶硅层。(A thyristor and a method of manufacturing the same are disclosed, the thyristor comprising an N-type substrate having a first surface and a second surface opposite the first surface; the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate; the groove penetrates through the P-type doping layer from the surface, far away from the N-type substrate, of the P-type doping layer and extends into the substrate; the glass passivation protective layer is formed in the groove; and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.)
1. A thyristor comprising
An N-type substrate having a first surface and a second surface opposite the first surface;
the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate;
the groove penetrates through the P-type doping layer from the surface, far away from the N-type substrate, of the P-type doping layer and extends into the substrate; and
the glass passivation protective layer is formed in the groove;
and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.
2. The thyristor of claim 1, wherein the semi-insulating polysilicon layer has a thickness of
3. The thyristor of claim 2, wherein the thin oxygen layer has a thickness less than
4. A thyristor according to claim 3, wherein the thin oxide layer and the semi-insulating polysilicon layer are annealed.
5. The thyristor of claim 4, wherein the annealing temperature is 800 to 850 °.
6. A thyristor according to claim 5, wherein the annealing is for a period of 20-60 minutes.
7. A thyristor according to any one of claims 1 to 6, wherein the P-type doped layer is formed only on a first surface of the N-type substrate, and a second surface of the N-type substrate is formed with an N + -type emitter region.
8. The thyristor of claim 7, wherein the P-doped layer is formed on both the first and second surfaces of the N-type substrate, and two N + -type emitter regions are formed in the P-doped layer on the first surface.
9. A thyristor according to any one of claims 1 to 6, wherein the P-doped layers are formed on both a first and a second surface of the N-type substrate, and N + -type emitter regions are formed within the P-doped layers on both the first and the second surface.
10. A method of fabricating a thyristor, the method comprising the steps of:
providing an N-type substrate;
forming a P-type doped layer on the N-type substrate;
forming a groove;
growing a thin oxygen layer in the groove;
depositing a semi-insulating polysilicon layer on the thin oxide layer;
and forming a glass passivation protective layer on the semi-insulating polycrystalline silicon layer.
11. The method of manufacturing of claim 10, wherein the semi-insulating polysilicon layer has a thickness of
12. The manufacturing method according to claim 10, wherein the thin oxygen layer has a thickness smaller than that of the thin oxygen layer
13. The method of manufacturing of claim 10, further comprising the step of annealing the thin oxide layer and the semi-insulating polysilicon layer prior to forming a glass passivation protection layer on the semi-insulating polysilicon layer.
14. The manufacturing method according to claim 13, wherein the annealing temperature is 800 to 850 °.
15. The manufacturing method according to claim 14, wherein the time of the annealing treatment is 20 to 60 minutes.
16. The method of manufacturing of claim 10, further comprising the step of cleaning the trench prior to forming a thin oxygen layer within the trench.
17. The method of manufacturing of claim 10, further comprising the step of observing through a transmission electron microscope to determine the structure of the thin oxide layer and the semi-insulating polysilicon layer after forming the semi-insulating polysilicon layer on the thin oxide layer.
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a thyristor and a method for manufacturing the same.
Background
Thyristors (thyristors) are short for thyristors and may also be called silicon controlled rectifiers; the thyristor has the characteristics of a silicon rectifier device, can work under the conditions of high voltage and large current, can control the working process, and is widely applied to electronic circuits such as controllable rectification, alternating current voltage regulation, contactless electronic switches, inversion, frequency conversion and the like.
However, existing series of dual-mesa thyristors, e.g. with junction temperatures of 125 ℃, typically use glass as passivation protection layer to ensure proper voltage blocking capability and long-term reliability, however, at 150 ℃, the glass formed passivation protection layer will greatly increase high temperature leakage, which easily leads to drift and reliability problems.
Disclosure of Invention
An object of the present disclosure is to solve at least one aspect of the above problems and disadvantages in the related art.
According to an embodiment of an aspect of the present disclosure, there is provided a thyristor including
An N-type substrate having a first surface and a second surface opposite the first surface;
the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate;
the groove penetrates through the P-type doping layer from the surface, far away from the N-type substrate, of the P-type doping layer and extends into the substrate; and
the glass passivation protective layer is formed in the groove;
and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.
In at least one embodiment, the semi-insulating polysilicon layer has a thickness of
ToIn at least one embodiment, the thin oxygen layer has a thickness less than
In at least one embodiment, the thin oxide layer and the semi-insulating polysilicon layer are annealed.
In at least one embodiment, the annealing temperature is 800 to 850 °.
In at least one embodiment, the annealing treatment time is 20-60 minutes.
In at least one embodiment, the P-type doped layer is formed only on the first surface of the N-type substrate, and the second surface of the N-type substrate is formed with an N + -type emitter region.
In at least one embodiment, the P-type doped layer is formed on both the first surface and the second surface of the N-type substrate, and two N + -type emitter regions are formed in the P-type doped layer on the first surface.
In at least one embodiment, the P-type doped layers are formed on both the first surface and the second surface of the N-type substrate, and N + -type emitter regions are formed in the P-type doped layers on both the first surface and the second surface.
There is also provided, in accordance with an embodiment of another aspect of the present disclosure, a method of manufacturing a thyristor, the method including the steps of:
providing an N-type substrate;
forming a P-type doped layer on the N-type substrate;
forming a groove;
forming a thin oxide layer in the groove;
forming a semi-insulating polysilicon layer on the thin oxide layer;
and forming a glass passivation protective layer on the semi-insulating polycrystalline silicon layer.
In at least one embodiment, the semi-insulating polysilicon layer has a thickness of
ToIn at least one embodiment, the thin oxygen layer has a small thicknessIn that
In at least one embodiment, the method of manufacturing further comprises the step of annealing the thin oxide layer and the semi-insulating polysilicon layer prior to forming a glass passivation protection layer on the semi-insulating polysilicon layer.
In at least one embodiment, the manufacturing method has an annealing temperature of 800 to 850 °.
In at least one embodiment, the manufacturing method includes the annealing treatment time being 20-60 minutes.
In at least one embodiment, the method of manufacturing further comprises the step of cleaning the trench before forming a thin oxygen layer within the trench.
In at least one embodiment, the method further comprises the step of observing through a transmission electron microscope to determine the structures of the thin oxide layer and the semi-insulating polysilicon layer after forming the semi-insulating polysilicon layer on the thin oxide layer.
The thyristor and the manufacturing method thereof provided by the above embodiments of the present disclosure may help balance charge distribution near the junction depletion region by adding the thin TSIPOS layer below the glass passivation protective layer, so as to facilitate voltage stabilization, so as to further increase junction temperature while ensuring good reliability.
Drawings
Fig. 1 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure; and
fig. 4 is a flow chart of a method of manufacturing a thyristor according to an example embodiment of the present disclosure.
Detailed Description
While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it should be understood, prior to this description, that one of ordinary skill in the art can modify the inventions described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.
Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.
According to the general inventive concept of the present disclosure, there is provided a thyristor including an N-type substrate having a first surface and a second surface opposite to the first surface; the P-type doped layer is formed on the first surface and/or the second surface of the N-type substrate; the surface of the P-type doped layer, which is far away from the N-type substrate, penetrates through the P-type doped layer and extends into the substrate, and the glass passivation protective layer is formed in the groove; and a semi-insulating polycrystalline silicon layer is formed between the thin oxygen layer and the glass passivation protective layer.
Fig. 1 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.
In one exemplary embodiment, as shown in fig. 1, the thyristor includes an N-
Fig. 2 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.
In one exemplary embodiment, as shown in fig. 2, the thyristor includes an N-
Fig. 3 is a schematic structural diagram of a thyristor according to an exemplary embodiment of the present disclosure.
In one exemplary embodiment, as shown in fig. 3, the thyristor includes an N-
In one exemplary embodiment, as shown in fig. 1-3, the thin oxygen layer 4 has a thickness, for example, less than
It should be noted, however, that in other embodiments of the present disclosure, the thickness of the thin oxygen layer 4 may take other values, such asIn one exemplary embodiment, as shown in fig. 1-3, the
In an exemplary embodiment, the thin layer of TSIPOS is annealed as shown in FIGS. 1-3. The annealing temperature may be, for example, 800 to 850 °. The annealing time may be, for example, 20 to 60 minutes, preferably 30 minutes. According to the thyristor, the TSIPOS thin layer is annealed, so that leakage between the TSIPOS thin layer and the N-
According to another aspect of the present disclosure, as shown in fig. 4, there is also provided a method of manufacturing a thyristor, comprising the steps of: at
In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at
In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at
In an exemplary embodiment, as shown in fig. 4, the manufacturing method further includes: at
The thyristor and the manufacturing method thereof provided by the above embodiments of the present disclosure may help balance charge distribution near the junction depletion region by adding the TSIPOS thin layer below the glass passivation protection layer, so as to be beneficial to voltage stabilization, and prevent leakage between the TSIPOS thin layer and the N-
It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.
Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.
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