阅读说明：本技术 包括作为吸收层的超晶格的半导体装置和方法 (Semiconductor device and method including superlattice as absorption layer ) 是由 武内英树 于 2018-05-16 设计创作，主要内容包括：半导体装置可以包括：半导体衬底(102)，具有正面和与正面相对的背面；以及在半导体衬底的正面上的超晶格吸收层(104)。所述超晶格吸收层可以包括堆叠的层组，每个层组包括限定基础半导体部分的多个堆叠的基础半导体单层和约束在相邻的基础半导体部分的晶格内的至少一个非半导体单层。装置可以进一步包括：在与所述半导体衬底(102)相对的所述超晶格吸收层(104)上的有源半导体层(106)；在所述有源半导体层中的至少一个半导体电路(108)；在有源层上的至少一个金属互连层(113、114)，以及从所述至少一个金属互连层延伸到所述半导体衬底的背面的至少一个金属通孔(112)。所述超晶格吸收层还可以包含吸收的金属离子。(The semiconductor device may include: a semiconductor substrate (102) having a front side and a back side opposite the front side; and a superlattice absorber layer (104) on the front side of the semiconductor substrate. The superlattice absorber layer may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The apparatus may further comprise: an active semiconductor layer (106) on the superlattice absorber layer (104) opposite the semiconductor substrate (102); at least one semiconductor circuit (108) in the active semiconductor layer; at least one metal interconnect layer (113, 114) on the active layer, and at least one metal via (112) extending from the at least one metal interconnect layer to the backside of the semiconductor substrate. The superlattice absorber layer may also contain absorbed metal ions.)

1. A semiconductor device, comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a superlattice absorber layer on the front side of the semiconductor substrate, the superlattice absorber layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

an active semiconductor layer on the superlattice absorber layer opposite the semiconductor substrate;

at least one semiconductor device in the active semiconductor layer; and

at least one metal interconnect layer on the active layer, and at least one metal via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate;

the superlattice absorber layer also includes absorbed metal ions.

2. The semiconductor device according to claim 1, wherein a thickness of the semiconductor substrate is less than 200 μm.

3. The semiconductor device according to claim 1, wherein a thickness of the semiconductor substrate is less than 70 μm.

4. The semiconductor device according to claim 1, wherein a thickness of the active semiconductor layer is in a range of 2 μm to 5 μm.

5. The semiconductor device of claim 1, wherein the metal of at least one metal interconnect comprises copper.

6. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

7. The semiconductor device of claim 1, wherein the at least one non-semiconductor layer comprises oxygen.

8. The semiconductor device of claim 1, wherein the active semiconductor layer comprises an epitaxial silicon layer.

9. The semiconductor device of claim 1, wherein the at least one semiconductor device comprises at least one Field Effect Transistor (FET).

10. A semiconductor device, comprising:

a semiconductor substrate having a front surface and a back surface opposite the front surface;

a superlattice absorber layer on the front side of the semiconductor substrate, the superlattice absorber layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

an active semiconductor layer on the superlattice absorber layer opposite the semiconductor substrate;

at least one semiconductor device in the active semiconductor layer; and

at least one metal interconnect layer on the active layer, and at least one metal via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate;

the superlattice absorber layer also includes absorbed metal ions.

11. The semiconductor device according to claim 10, wherein a thickness of the semiconductor substrate is less than 200 μm.

12. The semiconductor device according to claim 10, wherein a thickness of the semiconductor substrate is less than 70 μm.

13. The semiconductor device according to claim 10, wherein a thickness of the active semiconductor layer is in a range of 2 μm to 5 μm.

14. The semiconductor device of claim 10, wherein the metal of at least one metal interconnect comprises copper.

15. The semiconductor device of claim 10, wherein the active semiconductor layer comprises an epitaxial silicon layer.

16. The semiconductor device of claim 10, wherein the at least one semiconductor device comprises at least one Field Effect Transistor (FET).

17. A semiconductor processing method, comprising:

forming a superlattice absorber layer on a front side of a semiconductor substrate having a first thickness, the superlattice absorber layer comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

epitaxially growing an active semiconductor layer on the superlattice absorber layer opposite the semiconductor substrate;

forming at least one semiconductor device in the active semiconductor layer;

forming at least one metal interconnect layer on the active layer and at least one metal via extending from the at least one metal interconnect layer into the semiconductor substrate; and

thinning the semiconductor substrate from its backside to a second thickness less than the first thickness;

the superlattice absorber layer is configured to absorb metal ions released by forming the at least one metal interconnect layer and at least one metal via and thinning the semiconductor substrate.

18. The method of claim 17, wherein the second thickness is less than 200 μ ι η.

19. The method of claim 17, wherein the second thickness is less than 70 μ ι η.

20. The method of claim 17, wherein the thickness of the active semiconductor layer is in a range of 2 μ ι η to 5 μ ι η.

21. The method of claim 17, wherein the metal of at least one metal interconnect comprises copper.

22. The method of claim 17 wherein each base semiconductor portion comprises silicon.

23. The method of claim 17, wherein the at least one non-semiconductor layer comprises oxygen.

24. The method of claim 17, wherein epitaxially growing the active semiconductor layer comprises epitaxially growing a silicon layer.

25. The method of claim 17, wherein forming the at least one semiconductor device comprises forming at least one Field Effect Transistor (FET) in the active semiconductor layer.

Technical Field

The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor wafer processing and device fabrication.

Background

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by enhancing the mobility of charge carriers. For example, U.S. patent application No.2003/0057416 to Currie et al discloses a strained material layer of silicon, silicon-germanium and relaxed silicon and also includes impurity-free regions that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters carrier mobility, allowing higher speed and/or lower power devices. Published U.S. patent application No.2003/0034529 to Fitzgerald et al discloses a CMOS inverter that is also based on similar strained silicon technology.

U.S. patent No.6,472,685b2 to Takagi discloses a semiconductor device including a silicon carbon layer sandwiched between silicon layers such that the conduction and valence bands of the second silicon layer are tensile strained. Electrons having a smaller effective mass and which have been induced by an electric field applied to the gate electrode are confined in the second silicon layer, and therefore, it is certain that the n-channel MOSFET has a higher mobility.

U.S. patent No.4,937,204 to Ishibashi et al discloses a superlattice in which multiple layers (less than 8 monolayers and containing partial or binary compound semiconductor layers) are alternately and epitaxially grown. The main current flow direction is perpendicular to the superlattice layer.

U.S. patent No.5,357,119 to Wang et al discloses a silicon-germanium short period superlattice having a higher mobility obtained by reducing alloy scattering in the superlattice. In accordance with these principles, U.S. patent No.5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material substitutionally present in the silicon lattice at a ratio that places the channel layer under tensile stress.

U.S. patent No.5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region comprises alternating layers of SiO2/Si typically in the range of 2 to 6 monolayers thick. A thicker portion of silicon is sandwiched between the barriers.

Also, Tsu published online at page 391-402 of Applied Physics and Materials Science & Processing at 9/6/2000 under the title "Phenomena in silicon nanostructured devices" discloses a semiconductor-atomic superlattice (SAS) of silicon and oxygen. Si/O superlattices are disclosed as being useful in silicon quantum and light emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, i.e. perpendicular to the SAS layers. The disclosed SAS may include semiconductor layers separated by adsorbates (such as oxygen atoms, and CO molecules). The growth of silicon on the absorbed oxygen monolayer is described as epitaxial with a rather low defect density. One SAS structure included a 1.1nm thick silicon portion (i.e., about 8 atomic layers of silicon) and another structure having twice this silicon thickness. An article entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published by Luo et al, Physics Review Letters, Vol.89, No.7 (8/12 2002) further discusses the Light Emitting SAS structure of Tsu.

Published international application WO 02/103,767a1 by Wang, Tsu and Lofgren discloses that thin barriers of silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen constitute blocks, thereby reducing the current flowing vertically through the lattice by more than four orders of magnitude. The insulating layer/barrier layer allows low defect epitaxial silicon to be subsequently deposited to the insulating layer.

Published british patent application 2,347,520 to Mears et al discloses that the principles of Aperiodic Photonic Bandgap (APBG) structures may be suitable for electronic bandgap engineering. In particular, the application discloses that material parameters (e.g., location of band minima, effective mass, etc.) can be set to produce new aperiodic materials with desirable band-structure characteristics. Other parameters (such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability) for which the material can be designed are also disclosed.

Furthermore, Wang et al, U.S. patent No.6,376,337, discloses a method of producing an insulating or barrier layer for a semiconductor device, the method comprising depositing layers of silicon and at least one additional element on a silicon substrate, whereby the deposited layers are substantially defect-free, so that epitaxial silicon substantially defect-free can be deposited on the deposited layers. Alternatively, a monolayer of one or more elements (preferably comprising oxygen) is absorbed on the silicon substrate. A plurality of insulating layers sandwiched between the epitaxial silicon form a barrier composite.

Disclosure of Invention

The semiconductor device may include: a semiconductor substrate having a front surface and a back surface opposite the front surface; and a superlattice absorber layer on the front side of the semiconductor substrate. The superlattice absorber layer may include a plurality of stacked groups of layers, each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The apparatus may further comprise: an active semiconductor layer on the superlattice absorber layer opposite the semiconductor substrate; at least one semiconductor circuit in the active semiconductor layer; at least one metal interconnect layer on the active layer; and at least one metal via extending from the at least one metal interconnect layer to the back side of the semiconductor substrate. The superlattice absorber layer may further comprise absorbed metal ions.

For example, the thickness of the semiconductor substrate may be less than 200 μm, and in some configurations may be less than 70 μm. Also by way of example, the thickness of the active semiconductor layer may be in the range of 2 to 5 μm.

In one example embodiment, the metal in the at least one metal interconnect may include copper. For example, each base semiconductor portion may include silicon, and at least one non-semiconductor layer may include oxygen. Also by way of example, the active semiconductor layer may comprise an epitaxial silicon layer. Further, the at least one semiconductor circuit may include at least one Field Effect Transistor (FET).

A semiconductor processing method may include forming a superlattice absorber layer on a front side of a semiconductor substrate having a first thickness. The superlattice absorber layer may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include epitaxially growing an active semiconductor layer on the superlattice absorber layer opposite the semiconductor substrate; forming at least one semiconductor device in the active semiconductor layer; and forming at least one metal interconnect layer on the active layer and at least one metal via extending from the at least one metal interconnect layer into the semiconductor substrate. The method may further include thinning the semiconductor substrate from its backside to a second thickness less than the first thickness. In addition, the superlattice absorber layer absorbs metal ions released by forming at least one metal interconnection layer and at least one metal via and thinning the semiconductor substrate.

According to an example embodiment, the second thickness may be less than 200 μm, and in another embodiment, less than 70 μm. Also by way of example, the thickness of the active semiconductor layer may be in the range of 2 to 5 μm.

Furthermore, the at least one metal interconnect may for example comprise copper. Also by way of example, each base semiconductor portion may include silicon and at least one non-semiconductor layer may include oxygen. Epitaxially growing the active semiconductor layer may include epitaxially growing a silicon layer. In addition, forming at least one semiconductor device may include forming at least one Field Effect Transistor (FET) in the active semiconductor layer.

Drawings

Fig. 1 is a highly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.

Fig. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in fig. 1.

Fig. 3 is a highly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.

Fig. 4A is a graphical representation of the calculated band structure from the gamma point (G) for both bulk silicon in the prior art and the 4/1Si/O superlattice shown in fig. 1-2.

Fig. 4B is a graphical representation of the calculated band structure from the Z point for both bulk silicon in the prior art and the 4/1Si/O superlattice shown in fig. 1-2.

Fig. 4C is a graphical representation of the calculated band structure from both the gamma point and the Z point for both bulk silicon in the prior art and the 5/1/3/1Si/O superlattice shown in fig. 3.

Fig. 5-19 are a series of schematic cross-sectional views illustrating a method for fabricating a semiconductor device including a superlattice absorber layer in accordance with example embodiments.

Detailed Description

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

In general, the present disclosure relates to semiconductor wafer processing and device fabrication techniques that utilize an enhanced semiconductor superlattice as an absorber layer to prevent metal contamination in device layers of the chip. In the present disclosure, the enhanced semiconductor superlattice is also referred to as a "MST" layer or "MST technique". Further background regarding the use of MST technology may be found in U.S. patent No.9,275,996 to Mears et al, which is incorporated herein by reference in its entirety.

More particularly, MST technology relates to advanced semiconductor materials, such as the superlattice 25 as further described below. Applicants theorize, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this in turn leads to higher charge carrier mobilities. In the literature, effective masses are described with various definitions. As an improved measure of effective mass, applicants used a "conductivity reciprocal effective mass tensor" M for electrons and holes, respectively_e ^-1And M_h ^-1For electrons, the definition is:

and for holes defined as:

where f is the Fermi Dirac distribution, E_FIs the fermi level, T is the temperature, E (k, n) is the energy of the electron in the state corresponding to the wavevector k and the nth band, the indices i and j refer to the cartesian coordinate systems x, y, z, are integrated in the brillouin zone (B.Z.), and are summed for energy bands where the energy of the electron and hole is above or below the fermi level, respectively.

Applicants' definition of the reciprocal effective mass conductivity tensor is such that a tensor component of the electrical conductivity of the material is greater than a greater value for the corresponding component of the reciprocal effective mass conductivity tensor. Again, applicants theorize, without wishing to be bound thereto, that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material (such as generally for a preferred direction of charge carrier transport). The inverse of the appropriate tensor parameter (conductivity effective mass) is also referred to as the conductivity effective mass. In other words, to characterize the semiconductor material structure, the conductivity effective mass of electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish the improved materials.

Applicants have identified improved materials or structures for use in semiconductor devices. More specifically, applicants have identified materials or structures having band structures with suitable conductivity effective masses for electrons and/or holes that are much smaller than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a way that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are beneficial for use in many different types of devices, as will be discussed further below.

Referring now to fig. 1 and 2, the material or structure is in the form of a superlattice 25, the structure of the superlattice 25 being controlled at the atomic or molecular level and may be formed using known techniques for atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation, perhaps best understood with specific reference to the schematic cross-sectional view of fig. 1.

Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a respective base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. For clarity of illustration, the energy band-modifying layers 50 are indicated by stippling in fig. 1.

The energy band-modifying layer 50 illustratively comprises a non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. "constrained within the crystal lattice of adjacent base semiconductor portions" means: at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bound together by a non-semiconductor monolayer 50 therebetween, as shown in fig. 2. As will be discussed further below, in general, such a configuration may be achieved by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques such that not all available semiconductor bonding sites (i.e., less than full or 100% coverage) are occupied by bonds to non-semiconductor atoms. Thus, as additional monolayers 46 of semiconductor material are deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining vacancy bonding sites of the semiconductor atoms beneath the non-semiconductor monolayer.

In other embodiments, there may be more than one such non-semiconductor monolayer. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means: the material for the monolayer may then be non-semiconductor or semiconductor in the form of a body. That is, one skilled in the art will appreciate that a single monolayer of a material such as silicon may not necessarily exhibit the same properties as if it were formed as a bulk or relatively thick layer.

The applicant theorizes (but without wishing to be bound thereto): the energy band-modifying layer 50 and the adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for charge carriers in the parallel layer direction than would otherwise occur. Considered another way, the parallel direction is orthogonal to the stacking direction. The energy band-modifying layers 50 may also cause the superlattice 25 to have a common energy band structure while also beneficially acting as an insulator between layers or regions vertically above and below the superlattice.

In addition, the superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice 25. Those skilled in the art will appreciate that these properties may thus beneficially allow the superlattice 25 to provide an interface for the high-K dielectric that not only reduces diffusion of the high-K material into the channel region, but may also beneficially reduce undesirable scattering effects and improve device mobility.

It is also theorized that the semiconductor device including the superlattice 25 may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, the superlattice 25 may further have a substantially direct bandgap as a result of the energy band engineering achieved by the present invention, which may be particularly beneficial for optoelectronic devices, for example.

The superlattice 25 also illustratively includes a cap layer 52 on an upper group of layers 45 n. The cap layer 52 may comprise a plurality of base semiconductor monolayers 46. The cap layer 52 may have 2 to 100 monolayers of the base semiconductor, and more preferably 10 to 50 monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, those skilled in the art will appreciate that the term "group IV semiconductor" also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

For example, each energy band-modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The deposition of the non-semiconductor through the next layer is still desirably thermally stable, thereby facilitating manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with a given semiconductor process, as will be appreciated by those skilled in the art. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

It should be noted that the term "monolayer" is intended to include monolayers as well as monolayers. It is also noted that the energy band-modifying layer 50 provided by a single monolayer is also intended to include a monolayer in which not all of the possible sites are occupied (i.e., less than all or 100% coverage). For example, referring particularly to the atomic diagram of fig. 2, an 4/1 repeating structure is illustrated for silicon as the base semiconductor material and oxygen as the energy band-modifying material. In the illustrated example, only half of the possible sites for oxygen are occupied.

In other embodiments and/or with different materials, such a half occupation would not necessarily be the case as would be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram that the individual oxygen atoms in a given monolayer are not precisely aligned along a plane as one of ordinary skill in the art of atomic deposition will appreciate. For example, preferred occupancy ranges from about one-eighth to one-half of the possible oxygen sites being occupied, although other numbers may be used in some embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and therefore, manufacturers are readily able to use these materials described herein. Atomic or monolayer deposition is now also widely used. Accordingly, those skilled in the art will appreciate that semiconductor devices incorporating the superlattice 25 in accordance with the invention may be readily adopted and implemented.

Applicants theorize, without wishing to be bound thereto, that for superlattices such as Si/O superlattices, for example, the number of silicon monolayers should desirably be 7 or less so that the energy band of the superlattice is consistently or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure of the Si/O shown in fig. 1 and 2 has been modeled to indicate enhanced mobility of electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and it is 0.12 in the X direction for the 4/1Si/O superlattice, resulting in a ratio of 0.46. Similarly, for the calculation of holes, a value of 0.36 was generated for bulk silicon and a value of 0.16 for the 4/1Si/O superlattice, resulting in a ratio of 0.44.

While such directionally preferential characteristics may be desirable in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. Those skilled in the art will appreciate that it may also be beneficial to have an increase in mobility for both electrons and holes, or just one of these types of charge carriers.

The lower conductivity effective mass for the 4/1Si/O embodiment of the superlattice 25 may be less than 2/3 of the conductivity effective mass that would otherwise occur, and this applies to both electrons and holes. Of course, those skilled in the art will appreciate that the superlattice 25 may further comprise at least one type of conductivity dopant.

In fact, referring now additionally to fig. 3, another embodiment of a superlattice 25' in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More specifically, the lowermost base semiconductor portion 46a 'has three monolayers, and the second lowermost base semiconductor portion 46 b' has 5 monolayers. Repeating in this pattern throughout the superlattice 25'. The energy band-modifying layers 50' may each comprise a single monolayer. For such superlattices 25' comprising Si/O, the enhancement of charge carrier mobility is independent of the orientation at the layer plane. Those other items not specifically mentioned in fig. 3 are similar to those discussed above with reference to fig. 1 and need not be discussed further herein.

In some device embodiments, all of the base semiconductor portions of the superlattice may be as thick as the same number of monolayers. In other embodiments, at least some of the base semiconductor portions may be as thick as a different number of monolayers. In still other embodiments, all of the base semiconductor portions may be as thick as a different number of monolayers.

In fig. 4A-4C, the band structure calculated using Density Functional Theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. All bands above the band gap can therefore be shifted by an appropriate "scissors correction". However, the shape of the energy bands is known to be much more reliable. The vertical energy axis should be interpreted in view of this.

Fig. 4A shows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and the 4/1Si/O superlattice 25 (represented by dashed lines) shown in fig. 1. The directions refer to the unit cell of the 4/1Si/O structure rather than the conventional silicon unit cell, although the (001) direction in the figure does correspond to the (001) direction of the conventional silicon unit cell and, therefore, shows the expected location of the silicon conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of a conventional silicon unit cell. Those skilled in the art will appreciate that the bands of silicon are folded in the figure to show them in the appropriate inverted lattice orientation of the 4/1Si/O structure.

It can be seen that the conduction band minimum of the 4/1Si/O structure is located at the gamma point, in contrast to bulk silicon (Si), while the valence band minimum occurs at the edge of the brillouin zone in the (001) direction (we refer to as the Z point). It should also be noted that the curvature of the conduction band minimum of the 4/1Si/O structure is greater compared to the curvature of the silicon conduction band minimum due to band splitting caused by the perturbation introduced by the additional oxygen layer.

Fig. 4B shows the calculated band structure from the Z point for both bulk silicon (continuous lines) and the 4/1Si/O superlattice 25 (dashed lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

Fig. 4C shows the calculated band structure from both the gamma point and the Z point for both bulk silicon (continuous lines) and the 5/1/3/1Si/O structure of the superlattice 25' of fig. 3 (dashed lines). The calculated band structures in the (100) and (010) directions are equivalent due to the symmetry of the 5/1/3/1Si/O structure. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers (i.e., perpendicular to the (001) stacking direction). Note that in the 5/1/3/1Si/O example, both the conduction band minimum and the valence band maximum are at or near the Z point.

Although increased curvature is an indication of decreased effective mass, appropriate contrast and discrimination can also be achieved by calculation of the conductivity reciprocal effective mass tensor. This has led the applicant to further elucidate theoretically: 5/1/3/1 the superlattice 25' should be substantially direct bandgap. Those skilled in the art will appreciate that a suitable matrix element for optical transitions is another indicator of the difference between direct and indirect bandgap behavior.

Referring now to fig. 5-19, according to one advantageous embodiment, the MST superlattice structure (e.g., Si/O structure) described above may be used as an absorber layer for a Si epitaxial wafer. As background, stacked chip structures integrated with different chip functions (e.g., image sensors, DRAMs, logic, etc.) using TSV (through silicon vias) connections in a single package have recently gained popularity. For stacked chip structures, each chip is typically ground much thinner (70 μm) than the silicon wafers used for conventional packaging (200-.

Conventional silicon wafers typically have an absorber layer on the back side of the wafer. The metal used in BEOL, such as Cu, that diffuses into the silicon substrate is trapped in the absorber layer during wafer processing. During wafer backgrinding and CMP processes, when the absorber layer is ground or polished, the trapped metal is released into the water or CMP slurry. Although the front side of the wafer typically has a SiN passivation layer that protects against metal diffusion, the back side of the wafer is not protected after the absorber layer is removed. As a result, with the massive thinning of stacked chips, yield loss due to metal contamination during the packaging process can be problematic.

According to an example embodiment of a Si/O implementation for a Si wafer, the MST superlattice 104 may be formed on a "front" side of the starting wafer or substrate 102 using blanket deposition. For example, the starting substrate 102 may be cut from a CZ (Czochralski process) silicon wafer block. A-2 to 5 μm thick layer of regular epitaxial silicon (i.e., cap layer) is then grown on the superlattice 104. Notably, the 2 to 5 μm epitaxial growth is isolated from the underlying starting substrate 102 by the superlattice 104. The entire wafer structure 100 may then be used in downstream or manufacturing processes.

More specifically, one or more circuits 108, such as including Field Effect Transistors (FETs), for example, followed by a nitride layer 110 (fig. 6), may then be formed in the epitaxial semiconductor layer 106 during Front End (FEOL) processing. A middle-end (MOL) process is then performed to form the contacts 111 (fig. 7). Next, formation of through-silicon vias (TSVs) (fig. 8) may be performed to form metal (e.g., copper) vias 112 through the epitaxial (active) layer 106 and the superlattice absorber layer 104 and into the substrate 102.

Back end of line (BEOL) processing may then be performed to form metal interconnect layers 113, 114 coupled to the contacts 111 and vias 112, respectively. The interconnect layers 112 are separated by an intermediate insulator 115 (e.g., metal oxide) (fig. 9). A passivation layer 116 (e.g., oxide) may then be formed with an opening 130, the opening 130 being configured to expose the desired interconnect layer (here, metal layer 113) (fig. 10).

The middle-end (MEOL) process may then begin forming conductive contact "bumps" 117 at the location of the openings, i.e., Under Bump Metallization (UBM) formation. Thereafter, a temporary carrier 119 may be bonded to the TSV structure with an adhesive 118 (fig. 12). Carrier 119 may then be used to flip the TSV structure so that backgrinding may be performed on substrate 102 (fig. 13).

More specifically, the backside of the substrate 102 is thinned (e.g., using backside grinding and/or dry etching), while the MST absorbing superlattice 104 remains between the thinned bulk silicon and the epitaxial silicon layer 106. Thinning typically occurs to within a few microns of the tip of the TSV 112. After thinning to a desired thickness (e.g., 200 μm or less, and more particularly about 70 μm or less for stacked chip devices), the superlattice non-semiconductor (e.g., oxygen) monolayer captures or absorbs the metals and prevents them from diffusing into the circuit device active regions formed in the epitaxial layer 106 on the front side of the superlattice 104, thereby helping to keep yield losses at an acceptable level. The applicant theorizes (but without wishing to be bound thereto): the MST superlattice has a higher thermal stability than conventional single oxygen layers and, given the higher number of oxygen atoms provided in the superlattice, the MST superlattice has a significantly higher number of absorption sites. This may be particularly advantageous for applications such as the stacked chip arrangement described above, without the above-mentioned disadvantages associated with conventional absorption layers.

The device produced according to this method will typically include metal trapped in the bulk silicon 102 near the MST superlattice 104, and the superlattice absorber layer 104 will therefore also include absorbed metal ions in the final device, as will be appreciated by those skilled in the art. In addition to the Si/O superlattice and Si wafer described above, the method may also be used with other types of semiconductor substrates and superlattices, as will be appreciated by those skilled in the art.

Further processing steps may include etching the thinned substrate 102 to expose the TSVs 112 and form a passivation layer 120 over the TSVs and substrate (fig. 14). An opening 121 may then be formed in passivation layer 120 to expose TSV 112 (fig. 15), followed by formation of UBM pad 122 (fig. 16).

Assembly and testing operations may then be formed, including coupling UBM pad 122 to chip 123 using conductive UBM "micro" bumps 124 (fig. 17). The carrier 119 may then be separated and the adhesive layer 118 removed (fig. 18), followed by dicing and coupling the bumps 117 to the package substrate 125 with conductive bumps or contacts 126 to form the final device 150 (fig. 19). Tests may then be performed as needed.

Many modifications and other embodiments will come to mind to one skilled in the art having the benefit of the teachings presented herein. Therefore, it is to be understood that the disclosure is not limited to the specific exemplary embodiments disclosed herein.