阅读说明：本技术 微型超低电容固体放电管及其制备方法 (Miniature ultra-low capacitance solid discharge tube and preparation method thereof ) 是由 陈俊标 苏亮 沈一舟 于 2019-11-22 设计创作，主要内容包括：一种微型超低电容固体放电管及其制备方法,该固体放电管的上面设有硼基区P,该硼基区P单侧设置有部分交叠的磷扩散埋层N-,在所述硼基区P内布置有第一磷扩散区N+,在所述第一磷扩散区N+内布置有若干个短路孔形成元胞式阴极；在所述固体放电管的下面布置有一个硼区P和一个第二磷扩散区N+,前述硼区P和第二磷扩散区N+间隔设置,形成单向芯片阳极结构。本发明在原低电容结构设计基础上,在阴极增加了N-埋层,使每个元胞阴极的热沉增长,从而在相同芯片面积的基础上增加通流能力。下面采用硼区和第二磷扩散区N+对称式布局,消除了单项放电管的反向压降,基于该设计,原芯片面积可进行缩减,进而减小PN结面积,大幅度降低结电容。(A miniature ultra-low capacitance solid discharge tube and its preparation method, there are boron base regions P on the solid discharge tube, the boron base region P unilateral has phosphorus diffusion buried layer N-of some overlap, there are first phosphorus diffusion regions N + in the said boron base region P, there are several cell cathodes of short circuit hole formation in the said first phosphorus diffusion region N +; and a boron region P and a second phosphorus diffusion region N + are arranged below the solid discharge tube at intervals to form a unidirectional chip anode structure. On the basis of the original low-capacitance structure design, the N-buried layer is added on the cathode, so that the heat sink of the cathode of each unit cell is increased, and the through-current capacity is increased on the basis of the same chip area. The N + symmetrical layout of the boron region and the second phosphorus diffusion region is adopted, the reverse voltage drop of the single discharge tube is eliminated, and based on the design, the area of an original chip can be reduced, so that the area of a PN junction is reduced, and the junction capacitance is greatly reduced.)

1. A preparation method of a miniature ultra-low capacitance solid discharge tube is provided, wherein a boron base region P (1) is arranged on the solid discharge tube, and is characterized by comprising the following steps:

s1, pre-arranging a phosphorus diffusion buried layer N- (2) partially overlapped with one side of a boron base region P (1) before preparing the boron base region P (1), wherein the depth of the phosphorus diffusion buried layer N- (2) is greater than that of the boron base region P (1);

s2, preparing a boron base region P (1) and a boron region P (5), wherein the boron region P (5) is arranged below the solid discharge tube;

s3, arranging a first phosphorus diffusion region N + (3) in the boron-based region P (1), and arranging a plurality of short circuit holes (4) in the first phosphorus diffusion region N + (3) to form a cellular cathode;

s4, arranging a second phosphorus diffusion region N + (6) under the solid discharge tube, wherein the second phosphorus diffusion region N + (6) and the boron region P (5) are arranged at intervals to form the solid discharge tube.

2. A boron base region P (1) is arranged on the solid discharge tube, and the solid discharge tube is characterized in that a phosphorus diffusion buried layer N- (2) which is partially overlapped is arranged on one side of the boron base region P (1), a first phosphorus diffusion region N + (3) is arranged in the boron base region P (1), and a plurality of short circuit holes (4) are arranged in the first phosphorus diffusion region N + (3) to form a cellular cathode; and a boron region P (5) and a second phosphorus diffusion region N + (6) are arranged below the solid discharge tube, and the boron region P (5) and the second phosphorus diffusion region N + (6) are arranged at intervals to form a unidirectional chip anode structure.

3. The miniature ultra-low capacitance solid discharge lamp of claim 2, wherein the solid discharge lamp has a chip area of 0.5mm x 0.5mm to 0.6mm x 0.6mm and a junction capacitance of less than 6 pF.

4. The miniature ultra-low capacitance solid discharge lamp of claim 3, wherein the chip area is 0.56mm by 0.56 mm.

5. The miniature ultra-low capacitance solid discharge tube of claim 2, wherein the junction depths of the boron base region P (1) and the boron region P (5) are both 20-25 μm; the junction depth of the first phosphorus diffusion region N + (3) and the junction depth of the second phosphorus diffusion region N + (6) are both 10-15 micrometers; .

6. The miniature ultra-low capacitance solid discharge tube of claim 2, wherein the buried junction depth of the phosphorus diffusion buried layer N- (2) is 40um to 45 um.

7. The miniature ultra-low capacitance solid discharge tube of claim 2, wherein the first phosphorus diffusion region N + (3) and the boron base region P (1) are shaped identically and concentrically, and the first phosphorus diffusion region N + (3) is 3/4-4/5 of the area of the boron base region P (1).

8. The miniature ultra-low capacitance solid discharge tube of claim 2, wherein the shorting holes (4) are arranged in a plurality of rows at regular intervals in the first phosphorus diffusion region N + (3), a plurality of shorting holes are arranged in each row at regular intervals, and the shorting holes (4) in adjacent rows are arranged in a staggered manner.

9. The ultra-low capacitance micro solid discharge tube of claim 2, wherein the buried phosphorous diffusion layer N- (2) is disposed on the upper side, the lower side, the left side or the right side of the boron base region P (1).

10. The ultra-low capacitance micro solid discharge tube of claim 2, wherein the boron base region P (1) and the boron region P (5) are provided with metal layers on the outer sides.

Technical Field

The invention relates to semiconductor chip design and manufacture, in particular to a miniature ultralow-capacitance solid discharge tube.

Background

At present, the consistency of the voltage-resistant control of a conventional low-voltage solid discharge tube (below 64V) can be within 5V, and the line requirements of a current client can be completely met, however, along with the fact that the data transmission rate of a client application line is higher and higher, the design power consumption of a circuit board is lower and lower, the application of a low-voltage small-volume high-integration solid protection device is wider and wider, the junction capacitance of the low-voltage solid protection device with the same lightning stroke level is generally higher by 25-30 pF, the higher junction capacitance influences the data transmission quality, and the junction capacitance causes the packet loss phenomenon in the transmission of digital signals, so that the data transmission rate is reduced. The junction capacitance is mainly influenced by the diffusion concentration of a P region and the resistivity of a substrate, and generally, the lower the doping concentration at two ends of a PN junction of a semiconductor is, the wider the potential barrier broadening is, and the smaller the junction parasitic capacitance is. The conventional structure device controls voltage by using P-region diffusion concentration and substrate resistivity, as shown in fig. 1, so that parasitic junction capacitance is closely related to voltage value, while the solid discharge tube application uses voltage as the most important characteristic parameter, so that the capacitance in the structure is a fixed parameter when material resistivity and boron diffusion concentration are fixed. The minimum area of the device is 0.9 x 0.9 at present, and the packaging appearance is mainly SMA packaging. The capacitance value is usually 25-30 pF (breakdown voltage 64V, 1500V lightning stroke resistance). With the continuous improvement of the integration level of a client circuit board, in order to comply with the development of the application field, a signal level protection device integrated with a micro-area low-capacitance structure is produced. As shown in FIG. 2, the structure uses the N-buried layer to form a region with higher doping concentration in the silicon substrate with high resistivity, so that the breakdown voltage is ensured and the parasitic capacitance of the region except the buried layer is greatly reduced when the same P diffusion concentration is achieved. The capacitance value of the device under a fixed area is usually between 5 and 7pF (breakdown voltage is 24V, and 600V lightning stroke resistance is achieved).

With the development of 5G networks, including the trend of high integration of circuit board design, customers propose products with parasitic capacitance below 15pF since 2018, and the external dimensions of devices are required to be as small as possible (0.6mm by 0.6mm) or less, so that the integrated packaging is limited to the surface mount packaging of SOT-23, and the packaging requirements and the application requirements of customers cannot be met according to the current low-capacitance structure and area.

Disclosure of Invention

The invention aims to solve the problems that the parasitic capacitance of the conventional low-capacitance structure cannot be below 15pF, the area of a chip cannot meet the requirement of micro SOT-23 integrated packaging, 4 chips are required to be integrated and packaged in the SOT-23 by a product required by a customer, and the maximum chip mounting area of a main chip base island is 0.6um to 0.6um, so that the micro ultra-low-capacitance solid discharge tube is provided according to the requirement.

The technical scheme of the invention is as follows:

a preparation method of a miniature ultra-low capacitance solid discharge tube is provided, the upper surface of the solid discharge tube is provided with a boron base region P, and the preparation method comprises the following steps:

s1, pre-arranging a phosphorus diffusion buried layer N-overlapped with the single side part of the boron base region P before preparing the boron base region P, wherein the depth of the phosphorus diffusion buried layer N-is greater than that of the boron base region P;

s2, preparing a boron base region P and a boron region P, wherein the boron region P is arranged below the solid discharge tube;

s3, arranging a first phosphorus diffusion region N + in the boron base region P, and arranging a plurality of short-circuit hole forming cell type cathodes in the first phosphorus diffusion region N +;

s4, a second phosphorus diffusion region N + is disposed under the solid discharge tube, the second phosphorus diffusion region N + being spaced apart from the boron region P, thereby forming a solid discharge tube.

A miniature ultra-low capacitance solid discharge tube is provided with a boron base region P on which a phosphorus diffusion buried layer N & lt- & gt is arranged on one side of the boron base region P, a first phosphorus diffusion region N & lt + & gt is arranged in the boron base region P, and a plurality of cell cathodes formed by short circuit holes are arranged in the first phosphorus diffusion region N & lt + & gt; and a boron region P and a second phosphorus diffusion region N + are arranged below the solid discharge tube at intervals to form a unidirectional chip anode structure.

Further, the solid discharge tube has a chip area of 0.5mm x 0.5mm to 0.6mm x 0.6mm and a junction capacitance of less than 6 pF.

Further, the chip area was 0.56mm by 0.56 mm.

Furthermore, the junction depths of the boron base region P and the boron region P are both 20-25 μm; the junction depth of the first phosphorus diffusion region N + and the junction depth of the second phosphorus diffusion region N + are both 10-15 microns; .

Furthermore, the junction depth of the buried layer of the phosphorus diffusion buried layer N-is 40-45 um.

Further, the first phosphorus diffusion region N + and the boron base region P are in the same shape and are concentrically arranged, and the first phosphorus diffusion region N + is 3/4-4/5 of the area of the boron base region P.

Furthermore, the short circuit holes are arranged in a plurality of rows in the first phosphorus diffusion region N + at fixed intervals, a plurality of short circuit holes are arranged in each row at fixed intervals, and the short circuit holes in adjacent rows are arranged in a staggered manner.

Further, the phosphorus diffusion buried layer N-is arranged on the upper side edge, the lower side edge, the left side edge or the right side edge of the boron base region P.

Furthermore, metal layers are arranged on the outer sides of the boron base region P and the boron region P.

The invention has the beneficial effects that:

the micro ultra-low capacitance solid discharge tube ensures the through-current capacity (PN junction area) of the device, reduces the area of the device to 0.56mm x 0.56mm, reduces the junction capacitance to below 6pF, and meets the integration requirement of customers.

On the basis of the original low-capacitance structure design, the N-buried layer is added on the cathode, so that the through-current capacity on the basis of the area of the micro chip is increased. Based on the design, the area of the original chip can be greatly reduced, so that the area of a PN junction is reduced, and the junction capacitance is reduced.

Drawings

Figure 1 is a schematic diagram of a conventional device of the same type.

FIG. 2 is a schematic longitudinal view of a miniature ultra-low capacitance solid discharge tube of the present invention.

FIG. 3 is a front layout of a miniature ultra-low capacitance solid discharge tube of the present invention.

In the figure: 1. a boron base region P; 2. a phosphorus diffusion buried layer N-; 3. a first phosphorus diffusion region N +; 4. a short circuit hole; 5. a boron region P; 6. and a second phosphorus diffusion region N +.

Detailed Description

The invention is further described below with reference to the figures and examples.

A miniature ultra-low capacitance solid discharge tube, the area of the miniature chip is 0.56mm, as shown in figure 2, 3, it includes upper boron base region P1 and lower boron region P5, a phosphorus diffusion region N +3 is arranged in upper boron base region P1 separately, form the cellular cathode; the junction depths of the boron base region P1 and the boron region P5 are both 20-25 μm. A boron region P5 and a second phosphorus diffusion region N +6 are disposed below, both regions being located at a junction depth of 20-25 μm for independent layout of the boron regions.

In the invention, the junction capacitance of the ultra-low capacitance is less than 6 pF.

In the invention, metal layers are arranged at the outer sides of the upper boron base region P1 and the lower boron base region P5; the boron region P and the second phosphorus diffusion region N + below the boron region P are independently and symmetrically distributed; the junction depth of the second phosphorus diffusion region N + is 10-15 μm.

In the present invention, as shown in fig. 3, the position of the upper phosphorus diffusion buried layer N-2 may be a symmetrical position at the present position, or may be an adjacent position or a symmetrical position at the adjacent position.

The positions of the underlying boron region P5 and the second phosphorus diffusion region N +6 may be interchanged.

The voltage-resistant parameter range of the device can cover the conventional voltage range, namely the range from 6V to 400V, and the layout shape covers different geometric shapes such as rectangle, square, circle, ellipse and the like.

The following table is a parameter comparison table of one sample manufactured after the design is used, and it can be seen from the following table that under the condition that other process conditions of a conventional low capacitance plate are not changed, a buried layer N-structure and a back boron region and phosphorus region symmetrical structure are newly added, so that the parasitic junction capacitance is reduced to 6pF, 100% of current impact of 8/20 mu s waveform 30A is guaranteed to pass through, the requirement of a client on the micro high density of 3 chips packaged and integrated in the SOT-23 is completely met, and the application of the chip in a high-speed data communication environment is met. At present, the technological level of the miniature ultra-low parasitic capacitance is advanced in the industry, reaches the same level at home and abroad, and fills the blank in the technical field of integrated packaging of miniature ultra-low capacitance solid discharge tubes at home and abroad.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.