阅读说明：本技术 半导体元件的制造方法 (Method for manufacturing semiconductor element ) 是由 张开泰 李东颖 于 2019-04-15 设计创作，主要内容包括：在一半导体元件的制造方法中,蚀刻半导体基材以形成沟渠,借此沟渠定义出通道部。沉积硬罩幕层于通道部的侧壁上。非等向性地蚀刻半导体基材,以加深沟渠,借此加深的沟渠进一步定义出位于通道部与硬罩幕层下方的基部。将硬罩幕层从通道部的侧壁移除。以隔离材料填充加深的沟渠。凹入隔离材料以形成隔离结构,其中通道部凸出于隔离结构。(In a method of manufacturing a semiconductor device, a semiconductor substrate is etched to form a trench, whereby the trench defines a channel portion. Depositing a hard mask layer on the sidewall of the channel portion. The semiconductor substrate is anisotropically etched to deepen the trench, whereby the deepen trench further defines a base portion below the channel portion and the hard mask layer. The hard mask layer is removed from the sidewall of the channel portion. The deepened trenches are filled with an isolation material. The isolation material is recessed to form an isolation structure, wherein the channel portion protrudes from the isolation structure.)

1. A method of fabricating a semiconductor device, the method comprising:

etching a semiconductor substrate to form a trench, thereby defining a channel portion;

depositing a hard mask layer on the sidewalls of the channel portion;

anisotropically etching the semiconductor substrate to deepen the trench, whereby the deepen trench further defines a base portion below the channel portion and the hard mask layer;

removing the hard mask layer from the sidewalls of the channel portion;

filling the deepened trench with an isolation material; and

recessing the isolation material to form an isolation structure, wherein the channel portion protrudes from the isolation structure.

Technical Field

The disclosed embodiments relate to a semiconductor device and a method for manufacturing the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the course of the development of integrated circuits, the functional density (defined as the number of interconnected elements per chip area) has generally increased as the geometry, i.e., the smallest component (or line) that can be formed using a process, has decreased. The micronization process generally provides many benefits by increasing production efficiency and reducing associated costs. However, such scaling has increased the complexity of processing and manufacturing integrated circuits. To realize these advances, similar developments in integrated circuit fabrication are needed.

For example, as the semiconductor integrated circuit industry has evolved into the nano-technology process node for higher device density, higher performance and lower cost, manufacturing and design related challenges have led to the development of three-dimensional (3D) devices, such as fin field effect transistors (FinFETs).

Disclosure of Invention

According to one embodiment, the present disclosure provides a method. In the method, a semiconductor substrate is etched to form a trench, whereby the trench defines a channel portion. Depositing a hard mask layer on the sidewall of the channel portion. The semiconductor substrate is anisotropically etched to deepen the trench, whereby the deepen trench further defines a base portion below the channel portion and the hard mask layer. The hard mask layer is removed from the sidewall of the channel portion. The deepened trenches are filled with an isolation material. The isolation material is recessed to form an isolation structure, wherein the channel portion protrudes from the isolation structure.

Drawings

Aspects of the present disclosure may be better understood from the following detailed description when considered in conjunction with the accompanying drawings. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure;

FIGS. 4A-4I are schematic cross-sectional views illustrating intermediate stages in a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

FIGS. 5A-5H are schematic cross-sectional views illustrating intermediate stages in a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

FIGS. 6A-6G are schematic cross-sectional views illustrating intermediate stages in a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

FIG. 7 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 9 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify the present disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features, such that the first and second features may not be in direct contact.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the appended claims. For example, the singular forms "a", "an" and "the" may represent the plural forms as well, unless expressly limited otherwise. For example, the terms "first" and "second" are used herein to describe various elements, regions or layers, but these terms are only used to distinguish one element, region or layer from another element, region or layer. Thus, a first region may also be referred to as a second region, a swap of one term for another may occur similarly, and so on, without departing from the spirit of the claimed subject matter. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning (double-patterning) or multi-patterning (multi-patterning) processes. Generally, double patterning or multiple patterning processes combine lithography and self-aligned (self-aligned) processes so that patterns can be created with, for example, a pitch that is smaller than that achievable with a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. A self-aligned process is used to form spacers that close up the patterned sacrificial layer. Next, the sacrificial layer is removed, and then the remaining spacers can be used to pattern the fins.

In the process of patterning a convex structure of a semiconductor device, such as a fin and a nanowire structure, the shape control of the convex structure is very important. However, profile control such as convex structure is difficult to achieve. For example, when a hard mask is used to etch a semiconductor substrate to form a bump structure, the bump structure has a substantially flat profile. If the ratio of the etching rate of the hard mask to the etching rate of the semiconductor substrate is too high, most of the hard mask may be removed, thereby reducing the process window of the subsequent polishing process for manufacturing the isolation structure surrounding the convex structure. If the ratio of the hard mask etch rate to the semiconductor substrate etch rate is too small, etch back (etch back) problems may occur on the sidewalls of the bump structures, and thus the bump structures may not have a substantially flat profile.

Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, in which a bump structure is formed by two etching operations, and a hard mask layer is formed to cover a sidewall of the bump structure after a channel of the bump structure is formed in a first etching operation, so that a profile of the channel is protected during the second etching operation. Thus, a channel portion having a substantially straight profile can be obtained.

Fig. 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 is a finfet device. The semiconductor device 100 may include a semiconductor substrate 110, a plurality of bump structures 120, a plurality of Shallow Trench Isolation (STI) structures 130, at least one gate dielectric layer 150, and at least one gate structure 160. The semiconductor substrate 110 may comprise a single crystal semiconductor material or a compound semiconductor material. Silicon, germanium, silicon germanium tin (SiGeSn), III-V compound, silicon germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like, as a material of the semiconductor substrate 110. In some exemplary embodiments, the semiconductor substrate 110 comprises silicon.

As shown in fig. 1, the convex structure 120 is disposed above the semiconductor substrate 110. The bump structures 120 may be fins of a finfet device. In some embodiments, the convex structures 120 are formed by etching the semiconductor substrate 120, so that the convex structures 120 protrude from the surface 110a of the semiconductor substrate 110. There are a plurality of trenches 140, each trench 140 is located between two corresponding adjacent convex structures 120, so that the convex structures 120 can be separated from each other. Each convex structure 120 includes a base portion 122 and a channel portion 124. The base portion 122 is disposed above the surface 110a of the semiconductor substrate 110. Each base portion 122 has a central portion 122c and two edge portions 122e, wherein the edge portions 122e are located on opposite sides of the central portion 122 c. Each base 122 has a width W1 and a length L1. In some exemplary embodiments, the width W1 of each base 122 ranges from about 2nm to about 30nm, and the length L1 of each base 122 ranges from about 5nm to about 200 nm.

In each convex structure 120, the channel portion 124 is provided above the central portion 122c of the base portion 122, and thus each convex structure 120 has a stepped sidewall. Channel portion 124 is joined to gate structure 160. Each channel portion 124 may have a substantially straight profile 124 p. Each channel portion 124 has a width W2 and a length L2, wherein the width W1 of each base portion 122 is greater than the width W2 of each channel portion 124. Each convex structure 120 has a discontinuous portion between the channel portion 124 and the base portion 122. The difference between the width W1 of each base portion 122 and the width W2 of each channel portion 124 ranges from about 0.2nm to about 20 nm. The width W2 of each channel section 124 may range from about 2nm to about 30nm, and the length L2 of each channel section 124 may range from about 5nm to about 200 nm. In some embodiments, the length L1 of each base portion 122 is greater than the length L2 of each channel portion 124. If the width W1 of each base 122 is less than about 0.2nm, leakage current may occur. If the width W2 of each channel portion 124 is less than about 0.2nm, carrier mobility may be degraded. If the length L1 of each base portion 122 and/or the length L2 of each channel portion 124 is greater than about 200nm, the convex structures 120 may collapse.

In some embodiments, the base portion 122 and the channel portion 124 of the bump structure 120 are formed by etching the semiconductor substrate 110, so that the base portion 122 and the channel portion 124 of the bump structure 120 and the semiconductor substrate 110 are made of the same material. For example, the base portion 122 and the channel portion 124 of the bump structure 120 may comprise silicon, germanium, tin-silicon-germanium, iii-v compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

With continued reference to FIG. 1, STI structures 130 are formed over the surface 110a of the semiconductor substrate 110 between the bases 122 of the protrusions 120. The trench 140 is filled with an isolation material to form the shallow trench isolation structure 130. The STI structures 130 are respectively located between the bases 122 of adjacent pairs of the convex structures 120 and cover the sidewalls of the bases 122. In some illustrative embodiments, the isolation material of the shallow trench isolation structure 130 comprises silicon dioxide, silicon nitride, silicon oxynitride, or the like.

The gate dielectric layer 150 is disposed over the channel portion 124 and the base portion 122 of the ridge structure 120 and the STI 130. The gate dielectric layer 150 covers the sidewalls and upper surface of the channel portion 124, the upper surface of the base portion 122, and the upper surface of the shallow trench isolation structure 130. In thatIn some embodiments, the gate dielectric layer 150 may comprise a high-k dielectric material. For example, hafnium oxide (HfO) may be utilized ₂) Zirconium dioxide (ZrO) ₂) Titanium dioxide (TiO) ₂) Or the like, as the material of the gate dielectric layer 150.

The gate structure 160 is disposed above the gate dielectric layer 150. In some embodiments, the gate structure 160 includes a work function metal layer and an additional conductive layer, such as aluminum, tungsten, other suitable materials, or combinations thereof. The work function metal layer of an n-channel metal oxide semiconductor field effect transistor (NMOSFET) may comprise tantalum, titanium aluminum nitride, other suitable materials, or combinations thereof. The work function metal layer of a p-channel metal oxide semiconductor field effect transistor (PMOSFET) may comprise titanium nitride, tantalum nitride, other suitable materials, or combinations thereof.

The Gate All Around (GAA) transistor structure may be patterned using any suitable method. For example, these structures may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine lithography and self-aligned processes so that patterns can be created with, for example, pitches that are smaller than those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. A self-aligned process is used to form spacers that close up the patterned sacrificial layer. Next, the sacrificial layer is removed, and then the remaining spacers can be used to pattern the gate-all-around structure.

Fig. 2 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 200 includes a nanowire structure. The semiconductor device 200 may comprise a semiconductor substrate 210, a plurality of ridge structures 220, a plurality of shallow trench isolation structures 230, a plurality of gate dielectric layers 250, and at least one gate structure 260. The semiconductor substrate 210 may comprise a single crystal semiconductor material or a compound semiconductor material. For example, the semiconductor substrate 210 may comprise silicon, germanium, tin-silicon-germanium, or a combination of three or five elementsSubstance, silicon germanium (Si) _xGe _1-x) In which 1 is>x>0. Or an analog thereof. In some exemplary embodiments, the semiconductor substrate 210 comprises silicon.

As shown in fig. 2, the convex structures 220 are disposed above the semiconductor substrate 210 and protrude from the surface 210a of the semiconductor substrate 210. There are a plurality of trenches 240, each trench 240 is located between two corresponding adjacent convex structures 220 to separate the convex structures 220 from each other. Each convex structure 220 includes a base portion 222 and a channel portion 224. The base 222 is disposed above the surface 210a of the semiconductor substrate 210. In some embodiments, the base 222 is formed by etching the semiconductor substrate 210, such that the base 222 protrudes from the surface 210a of the semiconductor substrate 210, and the base 222 of the bump structure 220 is made of the same material as the semiconductor substrate 210. For example, the base 222 may comprise silicon, germanium, silicon germanium tin, group III-V compounds, silicon germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like. Each base portion 222 has a central portion 222c and two edge portions 222e, wherein the edge portions 222e are located on opposite sides of the central portion 222 c. Each base 222 has a width W1 and a length L1. In some exemplary embodiments, the width W1 of each base 222 ranges from about 2nm to about 30nm, and the length L1 of each base 222 ranges from about 5nm to about 200 nm.

In each convex structure 220, the channel portion 224 is disposed above the central portion 222c of the base portion 222, and may be spaced apart from the base portion 222. Each channel portion 224 has a width W2, wherein the width W1 of each base portion 222 is greater than the width W2 of each channel portion 224. The difference between the width W1 of each base portion 222 and the width W2 of each channel portion 224 ranges from about 0.2nm to about 20 nm. The width W2 of each channel portion 224 may range from about 2nm to about 30 nm. In some embodiments, the channel portion 224, the base portion 222, and the semiconductor substrate 210 are made of the same material. In some other embodiments, the material of the channel portion 224 is different from the material of the base portion 222 and/or the material of the semiconductor substrate 210. For example, the channel portion 224 and the base portion 222 may comprise silicon, germanium, tin-silicon-germanium, iii-v compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or itAnd the like.

As shown in FIG. 2, the STI 230 is disposed over the surface 210a of the semiconductor substrate 210 between the bases 222 of the protrusions 220. The trench 240 is filled with an isolation material to form a shallow trench isolation structure 230. Shallow trench isolation structures 230 are respectively located between the bases 222 of adjacent pairs of the convex structures 220. The isolation material of the shallow trench isolation structure 230 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or the like.

The gate dielectric layer 250 correspondingly surrounds the channel portion 224. In some embodiments, one gate dielectric layer 250 is in contact with the upper surface of the base 222. In some embodiments, the gate dielectric layer 250 may comprise a high-k dielectric material. For example, the gate dielectric layer 250 may comprise hafnium dioxide, zirconium dioxide, titanium dioxide, or the like.

The gate structure 260 covers the gate dielectric layer 250 and is located above the upper surface of the base portion 222 and the upper surface of the shallow trench isolation structure 230. A portion of the gate structure 260 is interposed between the channel portion 224 and the base portion 222. The material of gate structure 260 is similar to the material of gate structure 160 of fig. 1 and is not repeated here.

Fig. 3 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 300 is a finfet device. The semiconductor device 300 may comprise a semiconductor substrate 310, a plurality of ridge structures 320 and 330, a plurality of shallow trench isolation structures 340, at least one gate dielectric layer 370, and a first gate structure 380 and a second gate structure 385. The semiconductor substrate 310 may comprise a single crystal semiconductor material or a compound semiconductor material. For example, the semiconductor substrate 310 may comprise silicon, germanium, tin-silicon-germanium, group III-V compounds, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like. In some embodiments, the semiconductor substrate 310 comprises silicon.

As shown in fig. 3, the convex structures 320 and 330 are disposed above the semiconductor substrate 310 and protrude from the surface 310a of the semiconductor substrate 310. The bump structures 320 and 330 may be fins of a finfet device. In some embodiments, the convex structures 320 and 330 are divided into a first group 350 and a second group 352, wherein the convex structure 320 belongs to the first group 350 and the convex structure 330 belongs to the second group 352. The convex structures 320 in the first group 350 may be adjacent to each other and the convex structures 330 in the second group 352 may be adjacent to each other. There are a plurality of trenches 360, each trench 360 is located between two corresponding adjacent convex structures 320 and 330 to separate the convex structures 320 and 330 from each other. In some embodiments, the convex structures 320 are formed by etching the semiconductor substrate 310, such that the convex structures 320 protrude from the surface 310a of the semiconductor substrate 310. Each convex structure 320 includes a base portion 322 and a channel portion 324. The base 322 is disposed above the surface 310a of the semiconductor substrate 310. Each base portion 322 has a central portion 322c and two edge portions 322e, wherein the edge portions 322e are located on opposite sides of the central portion 322 c. Each base 322 has a width W1 and a length L1. For example, the width W1 of each base 322 ranges from about 2nm to about 30nm, and the length L1 of each base 322 ranges from about 5nm to about 200 nm.

In each convex structure 320, the channel portion 324 is provided above the central portion 322c of the base portion 322. The channel portion 324 is joined with the second gate structure 385. Each channel portion 324 may have a substantially straight profile 324 p. Each convex structure 320 has a discontinuous portion between the channel portion 324 and the base portion 322. Each channel portion 324 has a width W2 and a length L2, wherein the width W1 of each base portion 322 is greater than the width W2 of each channel portion 324. The difference between the width W1 of each base portion 322 and the width W2 of each channel portion 324 ranges from about 0.2nm to about 20 nm. The width W2 of each channel section 324 may range from about 2nm to about 30nm, and the length L2 of each channel section 324 may range from about 5nm to about 200 nm. In some embodiments, the bump structure 320 is formed by etching the semiconductor substrate 310, so that the semiconductor substrate 310 and the base 322 and the channel 324 of the bump structure 320 are made of the same material. For example, the base 322 and the channel 324 of the bump structure 320 may comprise silicon, germanium, tin-silicon-germanium, iii-v compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

Each convex structure 330 includes a base portion 332 and a channel portion 334. The base 332 is disposed above the surface 310a of the semiconductor substrate 310. In some embodiments, the base 332 is formed by etching the semiconductor substrate 310, such that the base 332 protrudes from the surface 310a of the semiconductor substrate 310, and the base 332 of the convex structure 330 and the semiconductor substrate 310 are made of the same material. For example, the base 332 may comprise silicon, germanium, tin-silicon-germanium, group III-V compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like. Each base portion 332 has a central portion 332c and two edge portions 332e, wherein the edge portions 332e are located on opposite sides of the central portion 332 c. Each base 332 has a width W3 and a length L3. In some exemplary embodiments, the width W3 of each base 332 ranges from about 2nm to about 30nm, and the length L3 of each base 332 ranges from about 5nm to about 200 nm.

In each convex structure 330, the channel portion 334 is provided above the central portion 332c of the base portion 332. Channel portion 334 is joined to first gate structure 380. Each channel portion 334 may have a substantially flat profile 334 p. Each convex structure 330 has a discontinuous portion between the channel portion 334 and the base portion 332. Each channel portion 334 has a width W4 and a length L4, wherein the width W3 of each base 332 is greater than the width W4 of each channel portion 334. The difference between the width W3 of each base portion 332 and the width W4 of each channel portion 334 ranges from about 0.2nm to about 20 nm. The width W4 of each channel portion 334 may range from about 2nm to about 30nm, and the length L4 of each channel portion 334 may range from about 5nm to about 200 nm. In some embodiments, channel portion 334 comprises a different material than base portion 332. In some exemplary embodiments, the channel portion 324 and the base portion 322 of the convex structure 320 and the base portion 332 of the convex structure 330 are made of a first material, and the channel portion 334 of the convex structure 330 comprises a second material different from the first material. For example, the first material and the second material may comprise silicon, germanium, tin-silicon-germanium, III-V compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

With continued reference to FIG. 3, a STI structure 340 is formed over the surface 310a of the semiconductor substrate 310 between the protrusions 320 and 330. The trench 360 is filled with an isolation material to form a shallow trench isolation structure 340. Shallow trench isolation structures 340 are located between adjacent pairs of the bases 322 and 332 of the convex structures 320 and 330, respectively. The shallow trench isolation structure 340 may comprise silicon dioxide, silicon nitride, silicon oxynitride, or the like.

Gate dielectric 370 is disposed over channel portions 324 and 334, base portions 322 and 332, and STI structure 340. Gate dielectric layer 370 covers the sidewalls and top surfaces of channel portions 324 and 334, the top surfaces of base portions 322 and 332, and the top surfaces of shallow trench isolation structures 340. In some embodiments, gate dielectric layer 370 may comprise a high-k dielectric material. For example, the gate dielectric layer 370 may comprise hafnium dioxide, zirconium dioxide, titanium dioxide, or the like. In some other embodiments, two gate dielectric layers with different materials may be disposed over the channel portions 324 and 334, respectively.

The first gate structure 380 and the second gate structure 385 are respectively disposed above the channel portion 334 and the channel portion 324. Each of the first and second gate structures 380 and 385 may include a work function metal layer and an additional conductive layer, such as aluminum, tungsten, other suitable materials, or combinations thereof. The workfunction metal layer of an n-channel mosfet may comprise tantalum, titanium aluminum nitride, other suitable materials, or combinations thereof. The workfunction metal layer of the p-channel mosfet may comprise titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. In some embodiments, the first gate structure 380 includes a p-type work function metal layer and the second gate structure 385 includes an n-type work function metal layer. That is, the first gate structure 380 is configured to produce a p-channel mosfet, and the second gate structure 385 is configured to produce an n-channel mosfet.

Fig. 4A-4I are schematic cross-sectional views illustrating intermediate stages of a method of fabricating a semiconductor device according to some embodiments of the present disclosure. As shown in fig. 4A, a semiconductor substrate 400 is provided. The semiconductor substrate 400 may comprise a single crystal semiconductorBulk material, compound semiconductor material, or the like. For example, the semiconductor substrate 400 may comprise silicon, germanium, tin-silicon-germanium, group III-V compounds, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

In some embodiments, a patterned hard mask 410 is formed over the semiconductor substrate 400. The patterned hard mask 410 is used to define the semiconductor substrate 400. The patterned hard mask 410 and the semiconductor substrate 400 comprise different materials, and the patterned hard mask 410 has an etch selectivity to the semiconductor substrate 400. For example, the patterned hard mask 410 may comprise aluminum oxide (Al) ₂O ₃) Silicon carbide nitride (SiCN), silicon nitride (SiN) _xWherein x is>0) Or the like.

With continued reference to fig. 4A, in some embodiments, a patterned buffer layer 412 is formed on the semiconductor substrate 400. In these embodiments, the patterned hard mask 410 is formed over the patterned buffer layer 412, and thus the patterned buffer layer 412 is sandwiched between the patterned hard mask 410 and the semiconductor substrate 400 to increase the adhesion between the patterned hard mask 410 and the semiconductor substrate 400. In some embodiments, a patterned protection layer 414 is formed over the patterned hard mask 410 to protect the patterned hard mask 410. The patterned protection layer 414 and the patterned hard mask 410 comprise different materials. For example, the patterned protection layer 414 may comprise aluminum oxide (Al) ₂O ₃) Silicon carbide nitride, silicon nitride (SiN) _xWherein x is>0) Or the like.

In some illustrative embodiments, a buffer layer is blanket formed over the semiconductor substrate 400 using, for example, thermal oxidation, Chemical Vapor Deposition (CVD), or the like. The hard mask is formed over the buffer layer by, for example, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like. A protective layer is formed over the hard mask by, for example, chemical vapor deposition, physical vapor deposition, or the like. Next, a patterning process, such as a photolithography and etching operation, is performed to remove portions of the passivation layer, the hard mask, and the buffer layer, thereby forming a patterned buffer layer 412, a patterned hard mask 410, and a patterned passivation layer 414 sequentially stacked on the semiconductor substrate 400. Such an etch operation may be any acceptable etch operation, such as a Reactive Ion Etch (RIE) operation, a Neutral Beam Etching (NBE) operation, the like, or combinations thereof. In some embodiments, the etching may be anisotropic. In some exemplary embodiments, the patterned hard mask 410 is thicker than the patterned buffer layer 412 and the patterned protection layer 414.

As shown in fig. 4B, a first etch operation 420 is performed on the semiconductor substrate 400. The first etching operation 420 removes a portion of the semiconductor substrate 400 to form a plurality of first trenches 430 in the semiconductor substrate 400 to define a plurality of channel portions 440. The first etching operation 420 may be any acceptable etching operation, such as a reactive ion etching operation, a neutral beam etching operation, the like, or combinations thereof. In some embodiments, the first etch operation 420 may be an anisotropic etch operation.

As shown in fig. 4C, a hard mask layer 450 is conformally formed over the patterned passivation layer 414, the patterned hard mask 410, the patterned buffer layer 412, and the semiconductor substrate 400, such that the hard mask layer 450 is located over the bottom of each first trench 430. The hard mask layer 450 is formed on the sidewalls of the channel portion 440 to protect the sidewalls of the channel portion 440 from being etched by the subsequent second etching operation 422 (see fig. 4D). In some embodiments, the hard mask layer 450 can be formed using Atomic Layer Deposition (ALD). In some alternative embodiments, the hard mask layer 450 may also be formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), remote plasma enhanced chemical vapor deposition (RPCVD), or the like. The process temperature for forming the hard mask layer 450 may be controlled to be substantially in the range of 0 ℃ to 500 ℃. The hard mask layer 450 may be formed in an ex-situ manner, i.e., the hard mask layer 450 may be formed in a chamber different from the chamber in which the first etch operation 420 is performed. In some embodiments, the hard mask layer 450 may be formed in-situ, i.e., the first etch operation 420 and the hard mask layer 450 may be performed in the same chamber. In some exemplary embodiments, the thickness t1 of the hard mask layer 450 may range from about 0.1nm to about 10 nm. If the thickness t1 of the hard mask layer 450 is less than about 0.1nm, the hard mask layer 450 may be too thin to protect the sidewalls of the channel portion 440 from etching. If the thickness t1 of the hard mask layer 450 is greater than about 10nm, the first trench 430 may be closed by the hard mask layer 450.

In some exemplary embodiments, the hard mask layer 450 has an etch selectivity to the patterned hard mask 410. The etch rate of the hard mask layer 450 during the subsequent second etch operation 422 (see fig. 4D) is lower than the etch rate of the patterned hard mask 410 during the subsequent second etch operation 422 (see fig. 4D). For example, the hard mask layer 450 may comprise silicon dioxide, metal oxide, or the like.

As shown in fig. 4D, a second etching operation 422 is performed on the hard mask layer 450 and the bottom of the first trenches 430 to remove a portion of the hard mask layer 450 and a portion of the semiconductor substrate 400, thereby deepening the first trenches 430 to form a plurality of second trenches 432, respectively. In the second etching operation 422, the hard mask layer 450 over the bottom of the first trench 430 is etched before etching the semiconductor substrate 400. After the second etching operation 422, the semiconductor substrate 400 is formed to have a plurality of bases 442, wherein the second trenches 432 separate the bases 442 from each other. Since the semiconductor substrate 400 is etched, the upper surface of each base 442 is in contact with the bottom surface of the hard mask layer 450.

Each base 442 has a central portion 442c and two edge portions 442e, wherein the edge portions 442e are located on opposite sides of the central portion 442 c. The channel portions 440 are respectively disposed above the central portions 442c of the base portions 442 to correspondingly form convex structures 444. The remaining portions of the hard mask layer 450 are respectively located above the edge portions 442e of the bases 442. Therefore, in each convex structure 444, the width W1 of the base 442 is greater than the width W2 of the channel portion 440, and the difference between the width W1 of the base 442 and the width W2 of the channel portion 440 is substantially 2 times the thickness t1 of the hard mask layer 450. That is, the difference between the width W1 of the base 442 and the width W2 of the channel portion 440 is from about 0.2nm to about 20 nm.

For example, the width W1 of each base 442 may range from about 2nm to about 30nm, and the width W2 of each channel portion 440 may range from about 2nm to about 30 nm. Each base 442 has a length L1, and each channel portion 440 has a length L2. For example, the length L1 of each base 442 may range from about 5nm to about 200nm, and the length L2 of each channel portion 440 may range from about 5nm to about 200 nm. In some embodiments, the convex structures 444 are formed by etching the semiconductor substrate 400, such that the convex structures 444 protrude from the surface 400a of the semiconductor substrate 400. In some exemplary embodiments, the semiconductor substrate 400 has a single-layer structure, and thus the channel 440 and the base 442 of the semiconductor substrate 400 and the convex structure 444 are made of the same material.

The patterned protection layer 414 may be removed during the second etch operation 422 (see fig. 4C), thereby exposing the top of the patterned hard mask 410. In some specific embodiments, portions of the patterned hard mask 410 may be removed during the second etch operation 422. The remaining portions of the hard mask layer 450 cover the sidewalls of each channel portion 440, and the sidewalls of the patterned hard mask 410 and the patterned buffer layer 412 corresponding to each channel portion 440, respectively.

The second etch operation 422 may be any acceptable etch operation, such as a reactive ion etch operation, a neutral beam etch operation, the like, or combinations thereof. In some embodiments, the second etch operation 422 may be an anisotropic etch operation. The second etch operation 422 may be performed in a non-in-situ manner, i.e., the second etch operation 422 may be performed in a chamber that is different from the chamber in which the hard mask layer 450 is formed. The second etching operation 422 may be performed in-situ, i.e., the second etching operation 422 and the hard mask layer 450 may be performed in the same chamber.

In some embodiments, the etch rate of the hard mask layer 450 during the second etch operation 422 is lower than the etch rate of the patterned hard mask 410 during the second etch operation 422. Since the hard mask layer 450 is more difficult to etch by the second etch operation 422 than the patterned hard mask 410, the sidewalls of the channel portions 440 are well protected by the hard mask layer 450 during the second etch operation 422, so that the profile 440p of each channel portion 440 remains intact, thereby forming each channel portion 440 with a substantially flat profile 440 p. In addition, the rate of the second etching operation 422 may be increased without fear of damaging the sidewalls of the channel portion 440, thereby reducing the operation time of the second etching operation 422.

In some embodiments, as shown in fig. 4E, the remaining portions of the hard mask 450 are removed to expose the channel portions 440 and the sidewalls of the patterned hard mask 410 and the patterned buffer layer 412 corresponding to each channel portion 440. The remaining portions of the hard mask 450 may be removed using, for example, a dry etch technique or a wet etch technique.

After the convex structures 444 are formed, shallow trench isolation structures 460 are formed in the second trenches 432 and cover the sidewalls of the bases 442 (see fig. 4H). In some embodiments, referring to fig. 4F-4H, during the formation of the shallow trench isolation structure 460, a layer of isolation material 462 is formed on the semiconductor substrate 400, the ridge structure 444, the patterned hard mask 410, and the patterned buffer layer 412 by, for example, cvd, pecvd, or the like. As shown in fig. 4F, the second trench 432 is filled with a layer of isolation material 462. The isolation material layer 462 comprises a dielectric material such as silicon dioxide, silicon nitride, silicon oxynitride, or the like. In some exemplary embodiments, the isolation material layer 462 may be tempered.

As shown in fig. 4G, a planarization process may be performed on the isolation material layer 462 to remove a portion of the isolation material layer 462, the patterned hard mask 410, and the patterned buffer layer 412, thereby exposing the upper surface 440t of the channel portion 440. After the planarization process is performed, the upper surface 462t of the isolation material layer 462 and the upper surface 440t of the channel portion 440 are substantially at the same height. In some illustrative embodiments, the planarization process may be performed using a polishing method, such as a Chemical Mechanical Polishing (CMP) method.

As shown in fig. 4H, the isolation material layer 462 is recessed to expose the sidewalls of the channel portion 440, thereby forming a shallow trench isolation structure 460. In some embodiments, the isolation material layer 462 is recessed using, for example, a dry etch.

After the shallow trench isolation structure 460 is formed, various operations are performed to form a semiconductor device. In some embodiments, the operations include forming a dummy (dummy) gate stack over the channel 440, forming Lightly Doped Drain (LDD) regions in the convex structures 444, forming gate spacers beside the dummy gate stack, forming source and drain structures adjacent to the gate spacers, forming a Contact Etch Stop Layer (CESL), and forming an inter-layer dielectric (ILD) layer.

After the formation of the interlayer dielectric layer, the dummy gate stack is removed. As shown in fig. 4I, a gate dielectric layer 470 is formed on the sidewalls and the upper surface of the channel portion 440 of the convex structure 444. In some embodiments, forming the gate dielectric layer 470 includes thermal oxidation, chemical vapor deposition, plasma enhanced chemical vapor deposition, Low Pressure Chemical Vapor Deposition (LPCVD), the like, or combinations thereof. In some illustrative embodiments, the gate dielectric layer 470 may comprise a high-k dielectric material. For example, the gate dielectric layer 470 may comprise hafnium dioxide, zirconium dioxide, titanium dioxide, the like, or combinations thereof.

A gate structure 480 is formed over the gate dielectric layer 470 to substantially complete the semiconductor device 490. In some embodiments, forming the gate structure 480 may include chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, and/or combinations thereof. In some embodiments, the gate structure 480 may include a work function metal layer and an additional conductive layer, such as aluminum, tungsten, other suitable materials, or combinations thereof. The workfunction metal layer of an n-channel mosfet may comprise tantalum, titanium aluminum nitride, other suitable materials, or combinations thereof. The workfunction metal layer of the p-channel mosfet may comprise titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. After the formation of the work function metal layer and the conductive layer, a chemical mechanical polishing process may be performed to planarize the semiconductor device 490.

FIGS. 5A-5H illustrate some implementations consistent with the present disclosureA cross-sectional view of each intermediate stage of a method of manufacturing a semiconductor device according to the above aspect. As shown in fig. 5A, a semiconductor substrate 500 is provided. The semiconductor substrate 500 may comprise a single crystal semiconductor material or a compound semiconductor material. For example, the semiconductor substrate 500 may comprise silicon, germanium, tin-silicon-germanium, group III-V compounds, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

In some exemplary embodiments, a plurality of first films 504a and second films 504b are sequentially stacked alternately over the semiconductor substrate 500. For example, the first film 504a and the second film 504b may be epitaxially grown over the semiconductor substrate 500. The first film 504a and the second film 504b comprise different materials. For example, the first film 504a may comprise silicon germanium (SiGe) _x) Germanium, or the like, and the second film 504b may comprise silicon or the like. In some embodiments, the first film 504a and the semiconductor substrate 500 comprise different materials, and the second film 504b and the semiconductor substrate 500 are made of the same material. In some embodiments, the second film 504b and the semiconductor substrate 500 also comprise different materials. For example, the first film 504a and the second film 504b may comprise silicon, germanium, tin-silicon-germanium, iii-v compound, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

In some embodiments, a patterned buffer layer 512, a patterned hard mask 510, and a patterned passivation layer 514 are formed on the uppermost one of the first film 504a and the second film 504 b. The fabrication of the patterned buffer layer 512, the patterned hard mask 510, and the patterned passivation layer 514 is similar to the fabrication of the patterned buffer layer 412, the patterned hard mask 410, and the patterned passivation layer 414 of FIG. 4A, and thus is not repeated here.

As shown in fig. 5B, a first etching operation 520 is performed on the first film 504a, the second film 504B, and the semiconductor substrate 500. A first etching operation 520 is performed to remove portions of the first film 504a, the second film 504b, and the semiconductor substrate 500, thereby forming a plurality of first trenches 530 to define a plurality of channel portions 540. Each channel part 540 includes a first film 504a and a second film 504b alternately stacked over the semiconductor substrate 500. The first etch operation 520 may be performed in a manner similar to that described in the first etch operation 420 of fig. 4B and is not repeated here.

As shown in fig. 5C, a hard mask layer 550 is conformally formed over the patterned passivation layer 514, the patterned hard mask 510, the patterned buffer layer 512, the channel portion 540, and the semiconductor substrate 500. A hard mask 550 is formed on the sidewalls of the channel 540 to protect the sidewalls of the channel 540 from being etched by the subsequent second etching operation 522 (see fig. 5D). The structural details and fabrication of hard mask layer 550 are similar to those of hard mask layer 450 of FIG. 4C and therefore will not be repeated here.

As shown in fig. 5D, a second etching operation 522 is performed on the hard mask layer 550 and the bottom of the first trenches 530 to remove a portion of the hard mask layer 550 and a portion of the semiconductor substrate 500, thereby deepening the first trenches 530 into a plurality of second trenches 532, respectively. In the second etching operation 522, the hard mask layer 550 is etched over the top surface of the semiconductor substrate 500 before etching the semiconductor substrate 500. This second etch operation 522 may be performed in a manner similar to that described in the second etch operation 422 of fig. 4D and will not be repeated here.

In some embodiments, as shown in fig. 5E, the remaining portions of the hard mask 550 are removed to expose the channel portions 540 and the sidewalls of the patterned hard mask 510 and the patterned buffer layer 512 corresponding to each channel portion 540. The remaining portions of the hard mask 550 may be removed using, for example, a dry etch or a wet etch.

As shown in fig. 5F, shallow trench isolation 560 is formed in second trench 532. The fabrication of the shallow trench isolation structure 560 may be performed similarly to the process described in fig. 4F-4H, and is not repeated here.

After the formation of the shallow trench isolation 560, various operations are performed to form a semiconductor device. In some embodiments, these operations include forming a dummy gate stack over the channel portion 540, forming a lightly doped drain region, forming gate spacers beside the dummy gate stack, forming source and drain structures adjacent to the gate spacers, forming a contact etch stop layer, and forming an inter-layer dielectric layer.

After the formation of the interlayer dielectric layer, the dummy gate stack is removed. Referring to fig. 5G, a channel nanowire release (release) operation is performed to release the nanowire. In some embodiments, the semiconductor device is configured to be an n-type device (e.g., having an n-type channel), the first film 504a (including silicon germanium (SiGe)) in the channel portion 540 is removed _x) Germanium, or the like) so that each second film 504b (including silicon or the like) is released to form a nanowire. In some embodiments, the semiconductor device is configured to be a p-type device (e.g., having a p-type channel), the second film 504b (including silicon or the like) in the channel portion 540 is removed, and thus each first film 504a (including silicon germanium (SiGe) is formed _x) Germanium, or the like) is released to form the nanowire. In some exemplary embodiments, the first thin film 504a or the second thin film 504b is removed using a dry etching technique or a wet etching technique.

As shown in fig. 5H, a plurality of gate dielectric layers 570 are formed to wrap the second films 504b, respectively. In some embodiments, forming the gate dielectric layer 570 includes thermal oxidation, chemical vapor deposition, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, the like, or combinations thereof. In some illustrative embodiments, the gate dielectric layer 570 may comprise a high-k dielectric material. For example, the gate dielectric layer 570 may comprise hafnium dioxide, zirconium dioxide, titanium dioxide, the like, or combinations thereof.

With continued reference to fig. 5H, a gate structure 580 is formed to wrap around the gate dielectric 570, substantially completing the semiconductor device 590. The details of the structure and fabrication of gate structure 580 are similar to those of gate structure 480 of fig. 4I and are not repeated here.

Fig. 6A-6G are schematic cross-sectional views illustrating intermediate stages in a method of fabricating a semiconductor device according to some embodiments of the present disclosure. As shown in fig. 6A, a semiconductor substrate 600 is provided. In some embodiments, the semiconductor substrate 600 includes a first region 602 and a second region 604. First, theThe first region 602 may be adjacent to the second region 604 or may be separated from the second region 604 by a distance. In some exemplary embodiments, the first portion 602a of the semiconductor substrate 600 in the first region 602 is a single layer structure. The semiconductor substrate 600 may comprise a single crystal semiconductor material or a compound semiconductor material. For example, the semiconductor substrate 600 may comprise silicon, germanium, tin-silicon-germanium, group III-V compounds, silicon-germanium (Si) _xGe _1-xIn which 1 is>x>0) Or the like.

In some embodiments, the second portion 604a of the semiconductor substrate 600 in the second region 604 is etched, and the epitaxially grown epitaxial structure 604b is over the etched second portion 604a of the semiconductor substrate 600. The epitaxial structure 604b and the semiconductor substrate 600 comprise different materials. For example, the semiconductor substrate 600 may comprise silicon, and the epitaxial structure 604b may comprise silicon germanium (SiGe) _x) Or germanium. In some embodiments, a patterned buffer layer 612, a patterned hard mask 610, and a patterned protection layer 614 are formed over the first portion 602a and the epitaxial structure 604b of the semiconductor substrate 600. The fabrication of the patterned buffer layer 612, the patterned hard mask 610, and the patterned protection layer 614 is similar to the fabrication of the patterned buffer layer 412, the patterned hard mask 410, and the patterned protection layer 414 of fig. 4A, and thus is not repeated here.

As shown in fig. 6B, a first etch operation 620 is performed on the semiconductor substrate 600 and the epitaxial structure 604B. A first etch operation 620 is performed to remove the first portion 602a of the semiconductor substrate 600 and a portion of the epitaxial structure 604b to form a plurality of first trenches 630 to define a plurality of channel portions 640 and 650. This first etch operation 620 may be performed in a manner similar to that described in the first etch operation 420 of fig. 4B and will not be repeated here.

As shown in fig. 6C, a hard mask layer 660 is conformally formed over the patterned protection layer 614, the patterned hard mask 610, the patterned buffer layer 612, the channel portions 640 and 650, and the semiconductor substrate 600. In some embodiments, a hard mask layer 660 is formed on the sidewalls of the channel portions 640 and 650 to protect the sidewalls of the channel portions 640 and 650 from being etched by the subsequent second etching operation 622 (see fig. 6D). The structural details and fabrication of hard mask layer 660 are similar to those of hard mask layer 450 of FIG. 4C and therefore will not be repeated here.

As shown in fig. 6D, a second etching operation 622 is performed on the hard mask layer 660 and the bottom of the first trenches 630 to remove a portion of the hard mask layer 660 and a portion of the semiconductor substrate 600, thereby deepening the first trenches 630 into a plurality of second trenches 632, respectively. This second etch operation 622 may be performed in a manner similar to that described in the second etch operation 422 of fig. 4D and will not be repeated here.

In some embodiments, as shown in fig. 6E, the remaining portions of the hard mask 660 are removed to expose the channel portions 640 and 650, and the sidewalls of the patterned hard mask 610 and the patterned buffer layer 612 corresponding to each channel portion 640 and 650. The remaining portions of hard mask 660 may be removed, for example, by dry etching or wet etching.

As shown in fig. 6F, shallow trench isolation structures 670 are formed in the second trenches 632. The fabrication of the shallow trench isolation 670 may be performed similarly to the process described in FIGS. 4F-4H, and is not repeated here.

After the shallow trench isolation 670 is formed, various operations are performed to form a semiconductor device. In some embodiments, these operations include forming a dummy gate stack over channel portions 640 and 650, forming lightly doped drain regions, forming gate spacers beside the dummy gate stack, forming source and drain structures adjacent to the gate spacers, forming a contact etch stop layer, and forming an inter-layer dielectric layer.

After the formation of the interlayer dielectric layer, the dummy gate stack is removed. As shown in fig. 6G, a gate dielectric layer 680 is formed over the sidewalls and upper surface of the channel portions 640 and 650. The structural details and fabrication of the gate dielectric layer 680 are similar to those of the gate dielectric layer 470 of fig. 4I and therefore will not be repeated here.

A first gate structure 684 and a second gate structure 686 are formed over the channel portion 650 and the channel portion 640, respectively. The first gate structure 684 and the second gate structure 686 may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, other suitable processes, or combinations thereof. Each of the first and second gate structures 684, 686 may include a work function metal layer and an additional conductive layer, such as aluminum, tungsten, other suitable materials, or combinations thereof. The workfunction metal layer of an n-channel mosfet may comprise tantalum, titanium aluminum nitride, other suitable materials, or combinations thereof. The workfunction metal layer of the p-channel mosfet may comprise titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. In some embodiments, the first gate structure 684 includes a p-type work function metal layer and the second gate structure 686 includes an n-type work function metal layer. That is, the first gate structure 684 is configured to fabricate a p-channel mosfet, and the second gate structure 686 is configured to fabricate an n-channel mosfet. During fabrication of the first and second gate structures 684, 686, N/P patterning may be performed to separate one type of element from another, and vice versa. Then, a chemical mechanical polishing process may be performed to planarize the semiconductor device 690.

Fig. 7 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. The method begins at operation 700, where a semiconductor substrate is provided. The method continues with operation 710 in which a patterned hard mask is formed over the semiconductor substrate. The method continues with operation 720 in which a first etching operation is performed on the semiconductor substrate to form a plurality of first trenches in the semiconductor substrate to define a plurality of channel portions. Subsequently, operation 730 is performed. A hard mask layer is conformally formed over the channel portion. The method continues with operation 740, where a second etching operation is performed to form a plurality of bases. The method continues with operation 750 where shallow trench isolation structures are formed around the base. The method continues with operation 760 in which a gate dielectric layer is formed over the channel portion. Subsequently, operation 770 is performed. Forming a gate structure over the gate dielectric layer.

Fig. 8 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. The method begins at operation 800, where a semiconductor substrate is provided. The method continues with operation 810 in which a plurality of first and second films are sequentially stacked alternately above the semiconductor substrate. The method continues with operation 820 in which a patterned hard mask is formed over an uppermost one of the first and second films. The method continues with operation 830 where a first etching operation is performed on the first film, the second film, and the semiconductor substrate to form a plurality of first trenches to define a plurality of channel portions. Subsequently, operation 840 is performed. A hard mask layer is conformally formed over the channel portion. The method continues with operation 850, which performs a second etching operation to form a plurality of bases. The method continues with operation 860 where shallow trench isolation structures are formed around the base. The method continues with operation 870, which performs a channel nanowire release operation to release the nanowires. The method continues with operation 880 where a gate dielectric layer is formed to encapsulate the nanowires, respectively. Subsequently, operation 890 is performed. Forming a gate structure over the gate dielectric layer.

Fig. 9 is a flow chart illustrating a method of fabricating a semiconductor device according to some embodiments of the present disclosure. The method begins at operation 900, which provides a semiconductor substrate comprising a first region and a second region. The method continues with operation 910 in which a patterned hard mask is formed over the first region and the second region of the semiconductor substrate. The method continues with operation 920 in which a first etching operation is performed on the first and second regions of the semiconductor substrate to form a plurality of first trenches defining a plurality of channel portions. Subsequently, operation 930 is performed. A hard mask layer is conformally formed over the channel portion. The method continues with operation 940 where a second etching operation is performed to form a plurality of bases. The method continues with operation 950 in which shallow trench isolation structures are formed around the base. The method continues with operation 960 in which a gate dielectric layer is formed over the channel portion. Subsequently, operation 970 is performed. And forming a gate structure above the gate dielectric layer, wherein the gate structure is respectively located above the first region and the second region of the semiconductor substrate.

The hard mask layer protects the sidewalls of the channel portions from etching during the second etching operation, so that the profile of each channel portion remains intact, thereby forming each channel portion with a substantially flat profile. In addition, the speed of the second etching operation can be improved without worrying about damaging the side wall of the channel part, so that the operation time of the second etching operation can be shortened.

According to one embodiment, the present disclosure provides a method. In the method, a semiconductor substrate is etched to form a trench, whereby the trench defines a channel portion. Depositing a hard mask layer on the sidewall of the channel portion. The semiconductor substrate is anisotropically etched to deepen the trench, whereby the deepen trench further defines a base portion below the channel portion and the hard mask layer. The hard mask layer is removed from the sidewall of the channel portion. The deepened trenches are filled with an isolation material. The isolation material is recessed to form an isolation structure, wherein the channel portion protrudes from the isolation structure.

According to some embodiments, depositing the hard mask layer is performed, whereby the hard mask layer is deposited over the bottom of the trench.

According to some embodiments, the method further comprises etching the hard mask layer over the bottom of the trench prior to anisotropically etching the semiconductor substrate.

According to some embodiments, the semiconductor substrate is anisotropically etched, whereby the upper surface of the base portion contacts the bottom surface of the hard mask layer.

According to some embodiments, the method further comprises depositing a hard mask over the semiconductor substrate and etching the hard mask to form a patterned hard mask over the semiconductor substrate. Wherein, a hard mask layer is deposited, thereby the hard mask layer is deposited on the patterned hard mask.

According to some embodiments, depositing the hard mask layer is performed, whereby the thickness of the hard mask layer ranges from about 0.1nm to about 10 nm.

According to another embodiment, the present disclosure discloses a method. In the method, a first film is epitaxially grown over a semiconductor substrate and a second film is epitaxially grown over the first film. The first film and the second film are etched to form a channel portion, wherein the channel portion has the etched first film and the etched second film. Depositing a hard mask layer on the sidewall of the channel portion. The semiconductor substrate is anisotropically etched to form a base portion under the channel portion and the hard mask layer. The hard mask layer is removed from the sidewall of the channel portion. An isolation structure is formed around the base. The etched first thin film is removed from the channel portion.

According to some embodiments, the semiconductor substrate is anisotropically etched, whereby the upper surface of the base portion contacts the bottom surface of the hard mask layer.

According to some embodiments, the difference between the width of the base portion and the width of the channel portion ranges from about 0.2nm to about 20 nm.

According to some embodiments, the method further comprises depositing a hard mask over the second thin film, and etching the hard mask to form a patterned hard mask over the second thin film. Wherein, a hard mask layer is deposited, thereby the hard mask layer is deposited on the patterned hard mask.

According to some embodiments, depositing the hard mask layer is performed, whereby the hard mask layer is deposited over the upper surface of the semiconductor substrate.

According to some embodiments, the method further comprises etching the hard mask layer over the top surface of the semiconductor substrate prior to anisotropically etching the semiconductor substrate.

According to yet another embodiment, the present disclosure provides an element. The device comprises a semiconductor substrate, an isolation structure, a gate dielectric layer, and a gate structure. The semiconductor substrate has a convex structure, wherein the convex structure has a base portion and a channel portion located above the base portion, the width of the base portion is greater than the width of the channel portion, and the difference between the width of the base portion and the width of the channel portion ranges from about 0.2nm to about 20 nm. The isolation structure surrounds the base of the convex structure, wherein the channel of the convex structure protrudes above the upper surface of the isolation structure. The gate dielectric layer is located above the channel portion of the convex structure. The gate structure is located above the gate dielectric layer.

According to some embodiments, the convex structure has a stepped sidewall.

According to some embodiments, the channel portion and the base portion of the convex structure comprise different materials.

According to some embodiments, the channel portion of the convex structure is spaced apart from the base portion of the convex structure.

According to some embodiments, the gate dielectric layer encapsulates the channel portion of the convex structure.

According to some embodiments, a portion of the gate structure is between the channel portion and the base portion.

According to some embodiments, the gate dielectric layer is in contact with an upper surface of the base.

According to some embodiments, the channel portion and the base portion of the convex structure are made of the same material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.