阅读说明：本技术 鳍状场效晶体管装置 (Fin-shaped field effect transistor device ) 是由 黄如立 江欣哲 潘育麒 杨峻铭 梁春升 庄英良 叶明熙 于 2019-05-07 设计创作，主要内容包括：本发明实施例说明鳍状场效晶体管装置的结构与形成方法。鳍状场效晶体管装置包括：基板；鳍状物,位于基板上；以及栅极结构,位于鳍状物上。栅极结构包括功函数金属层,位于栅极结构的内侧侧壁上。功函数金属层的最顶侧表面低于栅极结构的上表面。栅极结构亦包括充填栅极金属层,位于功函数金属层的最顶侧表面上。充填栅极金属层的上表面与栅极结构的上表面实质上共平面。栅极结构亦包括自组装单层,位于充填栅极金属层与功函数金属层之间。(Embodiments of the present invention illustrate structures and methods of forming finfet devices. The fin field effect transistor device includes: a substrate; a fin on the substrate; and a gate structure on the fin. The gate structure includes a work function metal layer on an inside sidewall of the gate structure. The topmost surface of the work function metal layer is lower than the upper surface of the gate structure. The gate structure also includes a filled gate metal layer on a topmost surface of the work function metal layer. The upper surface of the gate-filled metal layer is substantially coplanar with the upper surface of the gate structure. The gate structure also includes a self-assembled monolayer between the filled gate metal layer and the work function metal layer.)

1. A finfet device, comprising:

a substrate;

a fin on the substrate;

a gate structure on the fin, the gate structure comprising:

a work function metal layer on the inner sidewall of the gate structure, and the topmost surface of the work function metal layer is lower than the upper surface of the gate structure;

a gate-filled metal layer on a topmost surface of the work function metal layer, an upper surface of the gate-filled metal layer being substantially coplanar with an upper surface of the gate structure; and

a self-assembled monolayer between the filled gate metal layer and the work function metal layer.

Technical Field

Embodiments of the present invention relate to semiconductor structures, and more particularly, to structures and methods for improving gate resistance.

Background

Cmos fets are key components in the semiconductor industry and play a significant role in a variety of electronic devices. In semiconductor processing, metals and high-k dielectric materials are used in place of polysilicon and silicon oxide to form gate structures in transistors that meet performance requirements (e.g., carrier mobility and device speed) as transistor dimensions shrink. To form the metal gate, the dummy gate may be formed first and then removed to form a space (e.g., a trench or a reserved space) for the metal gate. Then, a dielectric material with a high dielectric constant and a metal are deposited in the trench to fill the trench and form a metal gate.

Disclosure of Invention

An embodiment of the present invention provides a finfet device, including: a substrate; a fin on the substrate; and a gate structure on the fin. The grid structure comprises a work function metal layer which is positioned on the inner side wall of the grid structure, and the topmost surface of the work function metal layer is lower than the upper surface of the grid structure; a gate-filled metal layer on a topmost surface of the work function metal layer, an upper surface of the gate-filled metal layer being substantially coplanar with an upper surface of the gate structure; and a self-assembled monolayer between the gate-filled metal layer and the work function metal layer.

An embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a grid structure with a work function metal layer; removing the top of the work function metal layer; forming a self-assembled monolayer on a topmost surface of the work function metal layer exposed by removing a top of the work function metal layer; and depositing a fill gate metal layer into the removed top portion of the work function metal layer with the self-assembled monolayer between the fill gate metal layer and the work function metal layer.

An embodiment of the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a grid structure; selectively removing the top of the gate structure; forming an adhesive layer on the upper surface of the gate structure exposed by removing the top of the gate structure; and selectively depositing a conductive layer on the adhesive layer on the removed top of the gate structure, wherein the adhesive layer adheres the upper surface of the gate structure exposed by the removed top of the gate structure and the conductive layer.

Drawings

FIG. 1A is a diagram of a MOSFET device in some embodiments.

Fig. 1B is a top view of the nmos device of fig. 1A, in some embodiments.

Fig. 2 is a cross-sectional view of a gate in some embodiments.

Fig. 3A-3C, 4A-4C, and 5A-5C are cross-sectional views of gates in some embodiments.

Figure 6 is a drawing of a fabrication process for forming a gate metal in an etched-back gate in some embodiments.

Description of reference numerals:

h1, h2, h3 vertical depth

H _FFin height

H _GHeight of grid

Lg gate length

L _SLength of

W fin width

100 semiconductor structure

102 substrate

104 fin

106 isolation structure

108 grid structure

108 ', 108' -1, 108 '-2, 108' -3 intermediate gate structure

110 _DDrain region

110 _SSource region

111 spacer layer

112 channel region

113 lightly doped drain region

114. 128 upper surface

115. 115 ', 115' high dielectric constant dielectric layer

116. 116 ', 116' cap layer

117 sacrificial gate structure

117' gate forming trench

117A, 117B1, 117B2, 117C1, 117C2 etch back trenches

118. 118 ', 118' barrier metal layer

119. 119 ', 119' work function metal layer

120. 120 ', 120' self-assembled monolayers

121. 121' filled gate metal layer

125 gate dielectric layer

128 dotted line

131 cross section

150 region of transistor

200. 300, 400, 500 structure

600 method

601. 602, 603, 604

Detailed Description

The different embodiments or examples provided below may implement different configurations of the present disclosure. The particular components and arrangements are provided to simplify the present disclosure and not to limit the same.

Also, spatially relative terms such as "below," "lower," "underside," "above," "upper" and the like may be used for ease of description to describe one element's relative relationship to another element in the figures. Spatially relative terms may be extended to elements used in other orientations than the orientation illustrated. The elements may also be rotated 90 or other angles, and thus directional terms are used only to describe directions in the drawings.

An example of the field effect transistor described herein is a metal oxide semiconductor field effect transistor. For example, a mosfet may be (i) a planar structure built in or on a planar surface of a substrate, such as a semiconductor wafer, or (ii) a vertical structure.

The term "fin field effect transistor" refers to a field effect transistor formed on a fin that is oriented vertically with respect to a planar surface of a wafer.

"source/drain" refers to the source/drain junctions that form the two ends of a field effect transistor.

The term "perpendicular" as used herein refers to being approximately perpendicular to the substrate surface.

The term "epitaxial layer" refers to a layer or structure of single crystal material. Likewise, the term "epitaxial growth" refers to a layer or structure of single crystal material. The epitaxially grown material may be doped or undoped.

The term "approximate" as used herein refers to a desired objective, characteristic value or parameter for a component or process step, which has been set at the design stage of a product, along with upper and lower limits for the desired value. The range of values typically comes from slight variations or tolerances in the process (tolerances).

One of the problems in forming metal gates of small gate length is how to deposit a sufficient amount of metal into the gate formation trenches. For example, a metal gate with a gate length of 7nm has a higher gate resistance than a metal gate with a gate length of 20nm because the amount of metal deposited in the metal gate with a length of 7nm is less. Similarly, the gate resistance of the 7nm metal gate and the 20nm metal gate is higher than that of the 240nm metal gate.

To reduce the gate resistance, a dry etch back and a wet etch back may be used to remove portions of the workfunction metal in the metal gate and fill in more metal in the metal gate. However, the etch-back process has a low etch selectivity, which may result in metal loss in the etched metal gate. For example, in addition to the workfunction metal, it is also possible to etch back the gate metal (e.g., tungsten) and the barrier layer (e.g., titanium nitride), resulting in a recess depth in the etched back profile. The above steps also reduce the gate height. In addition, the by-products formed during these etch-back processes may be difficult to remove. These etchback methods do not provide the desired etch selectivity between the workfunction metal and the gate metal. For example, the gate metal may be etched back using a wet etch process. As semiconductor devices continue to shrink, it becomes increasingly difficult to fabricate metal gates with the desired low gate resistance.

Embodiments of the present invention illustrate a selective etch back to remove a portion of the workfunction metal surrounding the metal in the metal gate. A relatively low or lower resistance conductive material is then filled into the space formed by the removal of the workfunction metal to increase the metal volume in the metal gate. The selective etch-back process may form one or more self-assembled monolayers on the etched portions. The self-assembled monolayer may improve adhesion between the etched portion and the newly deposited fill gate metal. A selective deposition process may be employed to deposit a newly deposited filler gate metal (e.g., a conductive material) that may include a desired and/or different dopant concentration and/or species to further improve (e.g., reduce) gate resistance. The selective etch back and selective deposition do not require additional masks or additional fabrication processes. Thus, the gate height is substantially unaffected (e.g., reduced), and more metal may be deposited into the metal gate. By using the method disclosed by the embodiment of the invention, the metal grid can have more metal than the metal grid manufactured at the beginning, the resistance of the grid can be reduced, and the electrical property of the semiconductor device can be improved. In addition, the newly deposited filler gate metal may adhere to the etched portions of the metal gate that have no voids or have few voids formed therein. The gate metal formed may be more uniform, thus reducing gate resistance. The method and structure of the embodiments of the invention can improve the device performance.

Fig. 1A, fig. 1B, fig. 2, fig. 3A to fig. 3C, fig. 4A to fig. 4C, and fig. 5A to fig. 5C are metal gates in various semiconductor devices fabricated by a gate resistance improvement method according to an embodiment of the present invention. The fabrication process can form a metal gate with an increased amount of gate metal, which can have a lower gate resistance than other gate metal structures. The additional gate metal according to embodiments disclosed herein may be bonded to the portion of the contact fill gate metal that has no voids or has a small amount of voids therein. The term "fill gate metal" refers to a conductive material subsequently deposited into the removed portion of the workfunction metal layer and may serve as the gate metal for the metal gate structure. Embodiments of the present invention may be used to form metal gates of various metals, such as tungsten, copper, aluminum, any other suitable metal, or combinations thereof. Metal gates may be formed in a variety of semiconductor devices and structures. For example, embodiments of the present invention may be used to form metal gates in planar devices and finfet transistors. The fabrication processes provided herein are merely exemplary, and other processes performed by embodiments of the present invention are not illustrated in subsequent figures.

Figure 1A is an isometric view of a semiconductor structure 100 in accordance with some embodiments of the invention. The semiconductor structure 100 includes a finfet. The semiconductor structure 100 includes a substrate 102, a plurality of fins 104, a plurality of isolation structures 106, and a gate structure 108 on sidewalls and a top surface of each fin 104. Fin 104 and isolation structure 106 have upper surfaces 114 and 128, respectively. The gate structure 108 includes a gate dielectric layer 125 and a sacrificial gate structure 117. In some embodiments, one or more additional layers or structures may be included in the gate structure 108. Fig. 1A is an isometric view of the structure after patterning the gate dielectric layer and the gate layer to form a gate structure 108. Fig. 1A shows only a single gate structure 108. An integrated circuit may include a plurality of gate structures.

Each fin 104 shown in figure 1A includes a pair of source/drain terminals. For simplicity of illustration, a first one of the pair of source/drain terminals is referred to as a source region 110 _SAnd the second of the pair of source/drain terminals is referred to as the drain region 110 _DWherein source/drain ends are formed in fin 104, on fin 104, and/or around fin 104. Channel region 112 of fin 104 is located under gate structure 108. The gate structure 108 hasGate length Lg and gate width (2H) _F+ W) as shown in fig. 1A. In some embodiments, the fin width W is between about 6nm to about 12 nm. In some embodiments, the fin width W is between about 4nm to about 6 nm. In some embodiments, the gate structure 108 has a gate height H from the upper surface 114 of the fin to the upper surface of the gate structure 108 _GBetween about 50nm to about 80 nm. In some embodiments, fin 104 has a fin height H from upper surface 128 of the isolation structure to upper surface 114 of the fin _FBetween about 25nm to about 35 nm.

The substrate 102 may be a silicon substrate. In other embodiments, the substrate 102 may comprise other semiconductor elements such as germanium, semiconductor compounds (including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), semiconductor alloys (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide), or combinations thereof. In some embodiments, the substrate 102 is a semiconductor on insulator. In some embodiments, the substrate 102 may be an epitaxial material.

The isolation structure 106 comprises a dielectric material, which may be composed of silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorine-doped silicate glass, a low-k dielectric material, and/or other suitable insulating materials. The isolation structure 106 may be a shallow trench isolation structure. In some embodiments, the isolation structure 106 is a shallow trench isolation structure and is formed by etching a trench in the substrate 102. Then, the trench is filled with an insulating material, followed by chemical mechanical polishing planarization and etch back. Other fabrication techniques may also be used to form isolation structures 106 and/or fins 104. The isolation structure 106 may comprise a multi-layer structure, such as having one or more liner layers.

Fin 104 is an active region in which one or more transistors are located. Fin 104 may comprise silicon or another semiconductor element such as germanium, a semiconductor compound comprising silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, a semiconductor alloy comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide phosphide, or combinations thereof. The fins 104 may be formed by any suitable process, including photolithography and etching processes. The photolithography process may include forming a photoresist layer on a substrate (e.g., a silicon layer), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a mask unit including the photoresist. A masking unit may then be used to protect regions of the substrate and leave the raised fins during the etching process that forms the recesses into the isolation structures 106. The recess etching process may employ reactive ion etching and/or other suitable processes. Various other methods may be employed to form fins 104 on substrate 102. In some embodiments, fins 104 may include epitaxial material.

The gate structure 108 shown in fig. 1A may be a sacrificial gate structure in a replacement gate process, which may be replaced with a metal gate structure. Prior to the replacement process, the sacrificial gate structure 117 may comprise a sacrificial material such as polysilicon. The replacement process may remove the sacrificial material and fill the trenches, spaces, and/or openings formed by the removal of the sacrificial material with a conductive material (e.g., a metal) to form the metal gate structure. The spacer layer 111 may remain in the displacement process and maintain the space for depositing the conductive material. A conductive material may then be deposited into the space maintained by the spacer layer 111 to form a metal gate structure. The method of forming the metal gate structure will be described in detail below.

Semiconductor structure 100 includes fin 104 and gate structure 108. The semiconductor structure 100 may include various structures, such as lightly doped drain regions and doped source/drain structures, of transistors employing the semiconductor structure 100 formed by additional processes. A lightly doped drain region may be formed in fin 104 by doping, and the term "lightly doped drain region" refers to a lightly doped region between a channel region and at least one source/drain region of a transistor. The doping process may be performed by ion implantation. Embodiments of the present invention are not limited to the doping process used to implant ions into lightly doped drain regions.

Figure 1B is a top view of a transistor region 150 having one of the fins 104 of figure 1A along a surface height of an upper surface 128 of an isolation structure 106. Transistor region150 include a source region 110 _SAnd the drain region 110 _D. Transistor region 150 also includes channel region 112, which is part of fin 104, and gate structure 108 surrounds fin 104 on three sides, as shown in figure 1A. The channel region 112 under the gate structure 108 has a width (fin width W). The length of the channel region 112 may be slightly different from the gate length Lg, depending on the conditions of the fabrication process and the device design. For simplicity of illustration, the length of the channel region 112 is denoted as the gate length Lg. The transistor region 150 also includes a gate dielectric layer 125 and a sacrificial gate structure 117. Fig. 1B also shows a spacer layer 111 formed on the gate structure 108. Lightly doped drain regions 113 are formed in the top surface and sidewalls of fins 104. The lightly doped drain region 113 shown in FIG. 1B has a width (fin width W) and a length L _S. The boundaries of the lightly doped drain region 113 may be aligned or misaligned with the spacer layer 111 (along the surface height shown in fig. 1B). Fig. 1B also shows another gate structure 108 in dashed lines. Other gate structures 108 are described above, which are parallel and similar to the gate structures 108 described above and are not shown in FIG. 1A.

Fig. 1B shows the spacer layer 111 surrounding the sacrificial gate structure 117 of the gate structure 108. The method of forming the spacer layer 111 may be any suitable method. For example, a compliant spacer layer is first deposited on the substrate, including on the gate structure 108. An etch-back process may then be employed to remove portions of the compliant spacer layer, exposing portions of the source/drain regions for ion implantation. Portions of the compliant spacer layer on the gate structure 108 are then removed. The remaining compliant spacer layer forms a spacer layer 111 that is at least on the sidewalls of the dummy gate structure 117. The spacer layer 111 may comprise a dielectric material such as silicon oxide, silicon oxynitride, silicon carbonitride, silicon nitride, any other suitable material, or a combination of any of the above. In some embodiments, the deposition process is a plasma enhanced chemical vapor deposition process, although other possible deposition processes may be used. In some embodiments, the spacer layer 111 has a thickness between about 2nm to about 14 nm. The thickness of the spacer layer 111 may provide a distance offset from the lightly doped drain region and prevent dopants from being implanted into the channel region 112.

Lightly doped drain regions 113 are then formed in fin 104 between adjacent spacer layers 111 using any suitable process. For example, an ion implantation process may be employed to form lightly doped drain region 113, which may employ any suitable dopant species. Although lightly doped drain region 113 is shown adjacent to the top surface of fin 104, lightly doped drain region 113 may be adjacent to both the top surface and the sidewalls of fin 104. The lightly doped drain implant may be performed vertically or obliquely toward the sidewalls of the fin. Lightly doped drain region 113 may extend to a depth below the surface of fin 104 depending on the implantation process. For example, lightly doped drain region 113 may extend to a depth below the upper surface of fin 104. In other embodiments, lightly doped drain region 113 may extend from a sidewall surface of fin 104 to an interior of fin 104. The substrate 102 may have p-type and n-type devices. Additional processes, such as lithographic patterning processes, may be employed to protect the p-type device region from the dopant ions used in the n-type device region. After implanting the dopant ions, a thermal anneal may be performed to drive in and activate the dopants. The thermal anneal may be a rapid thermal process anneal, a spike anneal, a microsecond anneal, a laser anneal, any other suitable annealing process, or any combination of the above. Spike annealing is operated at a spike annealing temperature for a period of time (in seconds). The microsecond anneal is operated at the peak anneal temperature for a period of time (in microseconds). The laser anneal is operated at the peak anneal temperature for a period of time (in nanoseconds to microseconds).

Furthermore, any suitable process may be employed to form the source region 110 _SA/drain region 110 _DLightly doped drain regions 113 in fins 104 between adjacent spacer layers 111. For example, the source region 110 may be formed by ion implantation using any suitable dopant species _SA/drain region 110 _D. In another example, a portion of the lightly doped drain region 113 between adjacent spacer layers 111 is removed and an epitaxial process is performed to grow suitable source/drain material between adjacent spacer layers 111. The source region 110 may be formed by in-situ doping with any suitable dopant _SA/drain region 110 _DWith any suitable doping level.The source region 110 may be formed according to various applications and/or embodiments _SA/drain region 110 _DThe depth from the upper surface 114 may be greater than or less than the depth of the lightly doped drain region 113. Source region 110 _SA/drain region 110 _DMay be less than, equal to, or greater than the lateral width of the lightly doped drain region 113, depending on the application.

Fig. 2-5C are various cross-sectional views of various stages in the fabrication of a finfet in accordance with various embodiments of the present invention. The method provided by the embodiment of the invention can be part of the gate replacement process or after the gate replacement process. In the embodiment of the present invention, the metal gate structure formed by the method disclosed in the embodiment of the present invention may be referred to as the middle gate structure 108'. The gate structure 108 shown in fig. 1A and 1B may also be referred to as a sacrificial gate structure, and the sacrificial gate structure 117 shown in fig. 1A and 1B may also be referred to as a gate structure. The intermediate gate structure 108' may be formed in accordance with the gate structure 108.

Fig. 2-5C illustrate an exemplary fabrication process for forming the metal gate structure. In some embodiments, the substrate 102 comprises silicon. In embodiments of the present invention, structures of different sizes (e.g., intermediate gate structures 108' of different gate lengths) are configured in the same figure for illustrative purposes. The dimensions of these structures in the drawings are not intended to represent the actual dimensions of the structures. For illustrative purposes, the structures shown in fig. 2-5C are cross-sectional views of a semiconductor structure, taken along section line 131 of fig. 1A or along a similar direction. The semiconductor structures may be formed in the same or different integrated circuits. The semiconductor structures may be formed via the same or different fabrication processes.

Figure 2 is a drawing of a structure 200 including an exemplary intermediate gate structure 108' along the cross-sectional line 131 shown in figure 1A in some embodiments. An intermediate gate structure 108 'may be formed from the gate structure 108, including a gate formation trench 117' surrounded by the spacer layer 111. The gate length (Lg) of the subsequently formed metal gate structure is defined as the lateral length of the metal gate subsequently formed between the source and drain regions, as shown in fig. 2. After removing the sacrificial gate structure 117, an intermediate gate structure 108' may be formed from the gate structure 108. After removing the sacrificial gate structure 117, a gate forming trench 117' may be formed. The method of removing the sacrificial gate structure 117 may include removing sacrificial gate material (e.g., polysilicon) from the gate structure 108 to form a gate forming trench 117'. Spacer layer 111 may remain on fin 104 and may serve to preserve space required for deposition of other layers in intermediate gate structure 108' and to protect subsequently formed metal gate structures. Intermediate gate structure 108' may be used to represent a partially formed gate structure having any suitable gate length Lg.

The method of removing the sacrificial gate structure 117 may include any suitable process. For example, a patterning process (e.g., a photolithography process) and a subsequent etching process (e.g., a wet or dry etching process) may be used to remove the sacrificial material surrounded by the spacer layer 111. During the patterning and etching processes, one or more hard masks may be formed on the gate structure 108 to expose the sacrificial material and protect the spacer layer 111. The etching process may be a selective etch or a controlled time etch, so that the sacrificial material may be completely removed. In some embodiments, the selective etch does not require an additional etch mask, e.g., the selective etch may be directed toward the semiconductor structure 100. Details of the removal process and associated masks are not described in detail herein. The channel region 112 may be formed under the gate structure 108 before forming the gate structure 108 or after removing the sacrificial gate structure 117. Dashed line 128 refers to the height of the upper surface of isolation structure 106. The gate dielectric layer 125 may be formed as part of the gate structure 108, or the gate dielectric layer 125 may be formed after the gate formation trench 117' is formed. Any suitable process may be employed to form gate dielectric layer 125. For example, the gate dielectric layer may comprise silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, any other suitable material, or a combination of any of the above. In another example, the gate dielectric layer 125 may also comprise hafnium oxide, zirconium oxide, lanthanum oxide, and/or other suitable high-k dielectric materials, and the deposition method may be plasma-enhanced chemical vapor deposition, physical vapor deposition, and/or atomic layer deposition. The gate dielectric layer may reduce the gap between the substrate material in fin 104 and the subsequently formed high-k dielectric layerAnd the reliability of the semiconductor structure 100 is maintained to preserve carrier mobility in the channel region 112. In some embodiments, after forming the gate forming trench 117', the gate dielectric layer 125 is formed by plasma enhanced chemical vapor deposition. In some embodiments, gate dielectric layer 125 comprises silicon oxide having a thickness of between about

To In the meantime.

Fig. 3A-3C are structures 300 in some embodiments that include exemplary intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 of different gate lengths. Fig. 3A to 3C each follow the sectional line 131 shown in fig. 1A. The intermediate gate structures 108' shown in fig. 3A-3C may each be formed from the gate structure 108 shown in fig. 2. For purposes of illustrating the method and structure of embodiments of the present invention, the gate lengths of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 are different from each other. In some embodiments, the gate length Lg of the intermediate gate structure 108 ' -1 < the gate length Lg of the intermediate gate structure 108 ' -2 < the gate length Lg of the intermediate gate structure 108 ' -3. For example, the gate length Lg of the intermediate gate structure 108 ' -1 can be 7nm, the gate length Lg of the intermediate gate structure 108 ' -2 can be 20nm, and the gate length Lg of the intermediate gate structure 108 ' -3 can be 240 nm.

In some embodiments, the intermediate gate structures 108 '-1, 108' -2, and 108 '-3 of fig. 3A-3C may each be formed from intermediate gate structures (e.g., the intermediate gate structure 108' of fig. 2) having similar structures (e.g., different dimensions and/or different gate lengths). A plurality of layers may be sequentially deposited into the gate formation trench 117 ' to form the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 of fig. 3A-3C from the intermediate gate structure 108 ' of fig. 2. The subsequently formed metal gate structure may include a barrier layer, a gate dielectric layer, a work function layer, a metal layer, and/or other suitable materials filled in the gate formation trench. In other embodiments, the metal gate structure may further include a cap layer, an etch stop layer, and/or other suitable materials. The spacer layer 111 may comprise a dielectric material such as silicon nitride, silicon oxycarbonitride, silicon carbonitride, other suitable insulating materials, or any combination thereof. For illustrative purposes, the gate dielectric layer 125 in the various figures of the embodiments of the present invention refers to the gate dielectric layer at the bottom of the metal gate structure. However, the gate dielectric layer 125 may comprise the same or different materials in different structures.

A high-k dielectric layer may be formed on the sidewalls of the spacer layer 111 and the gate dielectric layer 125 in the gate formation trench 117'. The high-k dielectric layer may be formed to block between the channel region 112 and a subsequently formed metal gate, thereby preventing leakage current in the channel region 112 and reducing power consumption of the semiconductor structure 100. In some embodiments, the high-k dielectric layer may comprise hafnium oxide, zirconium oxide, lanthanum oxide, other suitable materials, or a combination of any of the foregoing. The high-k dielectric layer may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, other suitable deposition methods, or any combination thereof. In some embodiments, the high-k dielectric layer has a thickness of between about 5nm and about 15 nm. In the present embodiment, the dielectric layers 115, 115 ', and 115 ″ having high dielectric constants are respectively disposed in the intermediate gate structures 108' -1, 108 '-2, and 108' -3.

A capping layer may be formed on the high-k dielectric layer in the gate-forming trench 117'. In one example, the capping layer may comprise a high dielectric constant barrier material, such as titanium nitride and/or TSN. In another example, the capping layer can protect the high-k dielectric layer from a subsequently formed barrier metal layer and reduce interface traps between the gate dielectric layer 125 and the substrate 102. The capping layer may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, metal organic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. The cap layer may have a thickness of between about 1nm and about 3 nm. In some embodiments, the cap layer is about 1.5 nm. In the present embodiment, the intermediate gate structures 108 '-1, 108' -2, and 108 '-3 have capping layers 116, 116', and 116 ", respectively.

A barrier metal layer may be further formed on the cap layer in the gate forming trench 117'. The barrier layer may comprise a metal and/or compound such as tantalum nitride and/or niobium nitride. The barrier metal layer can improve the adhesion between the cap layer and the subsequently formed work function metal layer. The barrier metal layer may also prevent carrier and/or ion diffusion between the cap layer and the work function metal layer. The barrier metal layer may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, metal organic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. The thickness of the barrier metal layer may be between about 1nm and about 3 nm. In some embodiments, the thickness of the barrier metal layer is about 1.5 nm. In the embodiment of the present invention, the intermediate gate structures 108 '-1, 108' -2, and 108 '-3 have barrier metal layers 118, 118', and 118 ", respectively.

A workfunction metal layer may also be formed on the barrier gold layer in the gate formation trench 117'. Exemplary p-type work function metals that may be included in the metal gate structure include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, tungsten nitride, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, other suitable p-type work function materials, or combinations thereof. Exemplary n-type workfunction metals that may be included in the metal gate structure include titanium, silver, tantalum aluminum carbide, titanium aluminum nitride, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable n-type workfunction materials, or combinations thereof. The work function is related to the material composition of the work function layer, and thus the material of the first work function layer may be selected to adjust its work function to achieve a desired threshold voltage for the devices to be formed in the respective regions. In some embodiments, the work function metal layer may comprise a work function metal such as titanium nitride, titanium aluminum carbide, other suitable work function metals, or any combination thereof. The work function metal layer may change the threshold voltage of the intermediate gate structure 108' to a desired value. The work function metal layer may be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma enhanced chemical vapor deposition, organometallic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. In some embodiments, the work function metal layer has a thickness between about 1nm and about 3 nm. In an embodiment of the present invention, the intermediate gate structures 108 '-1, 108' -2, and 108 '-3 have work function metal layers 119, 119', and 119 ", respectively.

A fill gate metal (e.g., a gate metal layer) may be further formed on the workfunction metal layer in the gate formation trench 117'. The gate-filling metal layer may fill the remaining space in the gate-forming trench 117'. The filler gate metal layer may comprise a suitable conductive material such as copper, aluminum, and/or tungsten. In some embodiments, the filled gate metal layer comprises tungsten. The gate metal layer may be formed by chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, metal organic chemical vapor deposition, sputtering, other suitable deposition methods, or any combination thereof. In some embodiments, the thickness of the gate metal layer is between about 1nm and 3 nm. In the present embodiment, the intermediate gate structures 108 ' -2 and 108 ' -3 have gate-filled metal layers 121 and 121 ', respectively. In some embodiments, the intermediate gate structure 108' -1 has little or no gate metal, as shown in fig. 3A. Reasons for the lack of gate metal in the intermediate gate structure 108' -1 may include the small gate length and the lack of space for depositing the gate metal after forming the workfunction metal layer 119. As shown in fig. 3A, the work function metal layer 119 may fill the remaining space in the gate formation trench 117' after deposition of the barrier metal layer 118. Furthermore, since the gate length of the intermediate gate structure 108 '-2 is less than the gate length of the intermediate gate structure 108' -3, the gate metal deposited in the intermediate gate structure 108 '-2 is less than the gate metal deposited in the intermediate gate structure 108' -3.

In some embodiments, a planarization process such as chemical mechanical polishing may be used after the formation of the above-mentioned layers to remove the excess thickness of the layers on the spacer layer 111. The upper surface of the gate forming trench 117' may be planarized. In this way, the top surfaces of the spacer layer 111, the high-k dielectric layer, the capping layer, the barrier metal layer, the work function metal layer, and the gate-filling metal layer may be coplanar with each other. For illustrative purposes, the semiconductor structure formed after the planarization process is referred to as the intermediate gate structure 108'. In various embodiments, other planarization and/or etching processes may be employed to form the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3.

As shown in fig. 3A-3C, the high-k dielectric layers 115, 115 ', and 115 ", the capping layers 116, 116 ', and 116", and the barrier metal layers 118, 118 ', and 118 "each form a U-shaped structure (e.g., a view along the cross-section line 131 or x-y plane) in the gate formation trench 117 ' of each of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3. Due to the gate length differences, the work function metal layers 119 'and 119 "in the intermediate gate structures 108' -2 and 108 '-3 each form a U-shaped structure in the respective gate forming trench 117', while the work function metal layer 119 in the intermediate gate structure 108 '-1 may form a vertical stripe structure (along the y-axis) in the gate forming trench 117'. In summary, for the intermediate gate structure 108 '-1, the topmost surface of the work function metal layer 119 may be substantially coplanar with the upper surface of the intermediate gate structure 108' -1. For intermediate gate structures 108 ' -2 and 108 ' -3, the topmost surfaces of work function metal layers 119 ' and 119 ", respectively, may be substantially coplanar with the upper surface of the intermediate gate structures.

As shown in fig. 3A-3C, the gate-filling metal layer 121 is deposited in an intermediate gate structure having a smaller gate length (e.g., the intermediate gate structure 108 '-2) than in an intermediate gate structure having a larger gate length (e.g., the intermediate gate structure 108' -3). In particular, for some intermediate gate structures having a small gate length (e.g., intermediate gate structure 108 '-1), no gate metal may be deposited in the gate formation trench 117'. As such, it becomes increasingly difficult to deposit sufficient gate metal into the metal gate structure as technology nodes evolve. The gate resistance of a metal gate structure may increase as the amount of gate metal decreases. The gate resistance may increase from the middle gate structure 108 '-1 toward the middle gate structure 108' -3. Fig. 4A to 5C are diagrams illustrating an embodiment of a method for improving gate resistance of different intermediate gate structures.

Fig. 4A-4C illustrate structures 400 in some embodiments, including exemplary intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 of different gate lengths. Fig. 4A to 4C are taken along the sectional line 131 shown in fig. 1A. In some embodiments, the top of the workfunction metal layer in each intermediate gate structure 108 ' -1, 108 ' -2, and 108 ' -3 is etched back to a desired depth to form an etch-back trench from its exposed topmost surface of the workfunction metal layer. As shown in fig. 4A to 4C, in the intermediate gate structure 108' -1, an etch-back trench 117A is formed in the work function metal layer 119 and has a vertical depth (or recess depth) h 1. In the intermediate gate structure 108 '-2, etch-back trenches 117B1 and 117B2 are formed in the workfunction metal layer 119' and each have a vertical depth h2 (along the y-axis). In the intermediate gate structure 108' -3, etch-back trenches 117C1 and 117C2 are formed in the workfunction metal layer 119 ″ and each have a vertical depth h 3. In some embodiments, the vertical depth of the etch-back trench in each workfunction metal layer may vary from about 40nm to about 50nm, and the vertical depths h1, h2, and h3 may be the same or different. For illustrative purposes, it is assumed that the etch-back trenches in the same gate formation trench have substantially the same depth (e.g., vertical depths h1, h2, and h 3). In some embodiments, the vertical depths h1, h2, and h3 are less than the vertical length of the respective workfunction metal layers, and may be about 40 nm.

In some embodiments, the top of the workfunction metal layer in the intermediate gate structure 108' is removed and an etch back trench is formed. The above steps may expose the inner surface of the etched portion. For example, for the etch back trench 117A of the intermediate gate structure 108' -1, the topmost surface of the etched work function metal layer 119 and the sidewall surface of the barrier metal layer 118 may be exposed. For etch-back trenches 117B1 and 117B2 of intermediate gate structure 108 ' -2, the topmost surface of etched work function metal layer 119 ' may be exposed, filling a portion of the sidewall surface of gate metal layer 121, and a portion of the sidewall surface of barrier metal layer 118 '. For etch-back trenches 117C1 and 117C2 of intermediate gate structures 108 '-3, the topmost surface of etched work function metal layer 119 "may be exposed, filling a portion of the sidewall surface of gate metal layer 121', and a portion of the sidewall surface of barrier metal layer 118". The exposed surface may be contacted by a subsequently deposited fill gate metal (e.g., a gate metal deposited by a subsequent process to fill the etch-back trench).

In some embodiments, the etch-back process may be performed using a suitable etch process. In some embodiments, a wet etch is performed to selectively etch the top of the respective workfunction metal layer. In some embodiments, an etchant (e.g., an etching solution) may selectively etch the workfunction metal layer on other layers and/or materials in the gate formation trench 117'. For example, the etch selectivity (e.g., the ratio of etch rates) of the etchant on the gate metal may be at least about 2, and/or the etch selectivity on the high-k dielectric material may be at least about 2. In some embodiments, the etch selectivity over the gate metal is at least about 3. The etch selectivity over other layers and/or materials may be as high as desired so that the selective etch may remove the top of the workfunction metal layer while the other layers in the gate formation trench 117' may remain substantially the same in thickness, height, and/or shape.

The etchant may be dispensed on a wafer or semiconductor structure 100 that is to be processed under appropriate conditions. The etchant may comprise phosphoric acid, which may be mixed with other etchants and/or additives. In some embodiments, the etchant comprises a mixture of hydrogen peroxide, phosphoric acid, and hot deionized water. In some embodiments, the fill gate metal layer comprises tungsten and the work function metal layer comprises titanium nitride, and the ratio of phosphoric acid: hydrogen peroxide: the weight ratio of the hot deionized water is about 10:1:1.5, and the etch selectivity is about 5 (e.g., the etch rate of the work function metal layer is about five times the etch rate of the fill gate metal layer). In some embodiments, the weight ratio of hydrogen peroxide, phosphoric acid, and hot deionized water may be varied to adjust etch selectivity and/or etch rate on the same or different materials. For example, when the fill gate metal layer and/or the workfunction metal layer comprise other materials, the phosphoric acid: hydrogen peroxide: weight ratio of hot deionized water. In some embodiments, other acidic media or solutions may be mixed into the mixture to achieve different etch selectivity, etch rate, and/or pH control. For example, hydrogen chloride may be added to the mixture to adjust the pH of the etchant. The etching conditions and/or parameters, such as the etching time and the etchant temperature, can be controlled to obtain the desired vertical depth of the etched back trench. For example, if a vertical depth of about 40nm is to be obtained with an etch selectivity of about 5, the etch time of the semiconductor structure 100 may be about 360 seconds, and the etch temperature may be between room temperature and about 80 ℃. In some embodiments, increasing the etchant temperature may increase the etch rate and thus decrease the etch time.

In some embodiments, the semiconductor structure 100 or wafer may be rinsed with a wet solution after the etching process. In some embodiments, the rinse solution is a mixture of pure deionized water, carbon dioxide-containing deionized water, dilute ammonium hydroxide, any other suitable rinse solution, or any combination of the above. The rinsed semiconductor structure 100 or wafer may be dried using any suitable method. In some embodiments, the drying process comprises nitrogen spin drying and/or isopropanol drying. The drying temperature of the drying process may be between room temperature and about 100 ℃.

The etchant may be used to form a self-assembled monolayer when reacting with the work function metal layer and/or other layers of the intermediate gate structure 108', such as the fill gate metal layer and/or the barrier metal layer. In some embodiments, the etchant facilitates the formation of a self-assembled monolayer when reacting with the fill gate metal, the work function metal layer, and the barrier metal layer, and the self-assembled monolayer after the etching process may cover the exposed surfaces of these layers. As shown in fig. 4A-4C, the self-assembled monolayers 120, 120', and 120 "are formed after selective etching. After the selective etching, the self-assembled monolayer may cover the exposed topside surface of the work function metal layer, fill the exposed upper and sidewall surfaces of the gate metal layer, and the exposed topside surface of the barrier metal layer. For example, for the intermediate gate structure 108' -1, the self-assembled monolayer may cover the exposed topmost surface of the etched work function metal layer 119 and the exposed top and sidewall surfaces of the barrier metal layer 118. For intermediate gate structure 108 ' -2, the self-assembled monolayer may cover the exposed topmost surface of etched work function metal layer 119 ', fill the exposed top and sidewall surfaces of gate metal layer 121, and the exposed top and sidewall surfaces of barrier metal layer 118 '. For intermediate gate structure 108 '-3, the self-assembled monolayer may cover the exposed topmost surface of etched work function metal layer 119 ", fill the exposed top and sidewall surfaces of gate metal layer 121', and the exposed top and sidewall surfaces of barrier metal layer 118". The self-assembled monolayer may serve as an adhesion layer, which may then adhere and/or conform to the gate-filled metal in the etched-back trenches (e.g., etched-back trenches 117A, 117B1, 117B2, 117C1, and 117C2), and improve the contact and/or adhesion between the gate-filled metal and the material in the etched-back trenches.

Specifically, the self-assembled monolayer may be formed between the phosphate and the material of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 (e.g., the work function metal layer, the material filling the gate metal layer, and/or the barrier metal layer). For example, the phosphate may form a self-assembled monolayer with the metal oxide in these layers. In some embodiments, the metal layer comprises tungsten, the work function metal layer comprises titanium nitride, and the barrier metal layer comprises tantalum nitride. The phosphate may then react with the titanium oxide in the work function metal layer to form a self-assembled monolayer of titanium phosphate on the exposed surface of the work function metal layer, with the tantalum oxide in the barrier metal layer to form a self-assembled monolayer of tantalum phosphate on the exposed surface of the barrier metal layer, and with the tungsten oxide in the gate-filled metal layer to form a self-assembled monolayer of tungsten phosphate on the exposed surface of the gate-filled metal layer. In the present embodiments, the term "self-assembled monolayer of phosphate of a metal" is merely for convenience of description to distinguish between different chemical compounds, and does not denote the chemical composition or formula of the compound.

The self-assembled monolayer may cover the material that reacts with the phosphate. In some embodiments, the etchant composition may be selected to match the material being etched and/or the material being exposed, so that the self-assembled monolayer may completely cover the inner surface of the etched-back trench. The self-assembled monolayer may improve adhesion between subsequently deposited gate-filled metal and the etched-back trench, so that the gate-filled metal may fill the etched-back trench with little or no voids. In summary, the amount of gate metal in the subsequently formed metal gate structure may be increased, and the gate resistance may be reduced. In some embodiments, a self-assembled monolayer is formed on the work function metal layer to improve adhesion between the fill gate metal and the work function metal layer. In some embodiments, the self-assembled monolayer is formed on the gate metal filling layer to improve adhesion between the gate metal and the metal filling layer, so that no voids are formed between the gate metal and the metal filling layer. In some embodiments, the resistance of the self-assembled monolayer is sufficiently low or negligible so that the presence of the self-assembled monolayer has little or no effect on the conductivity of the filled gate metal layer and the filled gate metal. In various embodiments, other suitable materials may be used to form the work function metal layer, the fill gate metal layer, and/or the metal barrier layer. The etchant composition may be varied to ensure that a self-assembled monolayer (having an adhesion function to bond the fill gate metal to the work function metal layer) is formed at least on the work function metal layer. The particular choice of etchant composition may not be limiting to the embodiments of the invention.

In some embodiments, the workfunction metal layer may be etched back by other methods. For example, a planarization process may be used to expose and etch the topmost surface of the work function metal layer in the intermediate gate structure 108' and a mask may be used to cover the topmost surface of the other layers. As noted above, the top of the workfunction metal layer may be removed by a suitable etch, such as a time controlled wet and/or dry etch process. The mask may be removed after the etch back. An adhesion layer (e.g., a liner layer or a self-assembled monolayer) may optionally be formed on the inner surfaces of the etched-back trenches 117A, 117B1, 117B2, 117C1, and 117C2 by any suitable method. For example, the adhesion layer may be formed in the etch-back trench by rinsing the etch-back trench with a suitable acidic solution, such as a sulfuric acid-based solution. The adhesive layer may be in any suitable form, such as a monolayer or film. The resistance of the adhesion layer is sufficiently low so that the presence of the adhesion layer only slightly or does not affect the conductivity of the gate-filled metal layer and the gate-filled metal.

Fig. 5A-5C illustrate structures 500 in some embodiments including exemplary intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 of different gate lengths. Fig. 5A to 5C are taken along the sectional line 131 shown in fig. 1A. As shown in fig. 5A-5C, a filled gate metal (in the figures having the same pattern as the filled gate metal layer) may be deposited into the etched-back trench to contact the filled gate metal layer. The self-assembled monolayer formed in each of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 may improve adhesion and/or cohesion between the filled gate metal and the filled gate metal layer, between the filled gate metal and the work function metal layer, and/or between the filled gate metal and the barrier metal layer. In some embodiments, the doping level of the gate-fill metal is higher than the doping level of the gate-fill metal layer. In some embodiments, the filled gate metal is formed by a suitable deposition process, such as chemical vapor deposition, atomic layer deposition, or the like, and is in-situ doped, thereby forming a desired doping level and dopant species in the filled gate metal to further reduce the resistance of the subsequently formed metal gate structure.

In some embodiments, the fill gate metal is deposited via a selective deposition process and is in-situ doped during the selective deposition. In some embodiments, the gate-filled metal layer comprises tungsten and the gate-filled metal comprises tungsten. A selective deposition method for forming tungsten may include atomic layer deposition. In some embodiments, an atomic layer deposition process may be performed using precursor gases of tungsten pentachloride gas and hydrogen gas. Solid tungsten may be selectively formed in the etch-back trench. In some embodiments, the flow rate of tungsten pentachloride is between about 50sccm to about 100sccm and the flow rate of hydrogen is between about 1000sccm to about 2000 sccm. Tungsten pentachloride may be carried by argon to pump into a reaction chamber at a temperature between about 450 ℃ and 550 ℃ to a chamber pressure of about 40 Torr. Hydrogen gas may be pumped into the reaction chamber to a pressure of about 60 Torr. As described above, tungsten may be deposited to fill the etch-back trench. In some embodiments, a selective deposition process is used to form tungsten without an additional mask to ensure that tungsten is formed in the etch-back trench. In some embodiments, after forming the tungsten, a chemical mechanical polish may be performed to planarize the upper surface of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3.

In some embodiments, other deposition methods (e.g., selective or non-selective) may be used to fill the filled gate metal into the etched-back trench. If a non-selective deposition method is used, an etch back process may be performed to remove excess gate metal outside the etch back trench. For example, a patterning process may be performed to expose and remove excess gate metal outside the etched-back trench. A chemical mechanical polishing process may then be performed to planarize the upper surface of the intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3.

In some embodiments, a filler gate metal having a different gate metal (e.g., a different native gate metal material than the filler gate metal layer) may also be deposited. The filled gate metal may have a relatively low resistance or lower resistance than the filled gate metal layer. In some embodiments, the self-assembled monolayer covering the etch-back trench may improve adhesion between the filled gate metal (such as comprising a metal and/or conductive material different from the original gate metal material filled with the gate metal layer) and the work-function metal layer.

In some embodiments, appropriate dopants may be formed into the filled gate metal to further reduce gate resistance. For example, boron may be doped into the fill gate metal to increase the doping level and thus reduce the gate resistance. Boron may be deposited on the filled gate metal (which may comprise the same or different material than the original gate metal material of the filled gate metal layer). In some embodiments, the self-assembled monolayer covers the etch-back trench, improving adhesion between the doped filled gate metal and at least the workfunction metal layer. In some embodiments, the self-assembled monolayer adheres the doped filled gate metal to the filled gate metal layer with little or no voids therein.

After depositing the gate metal into the etch-back trenches 117A, 117B1, 117B2, 117C1, and 117C2, a metal gate structure may be formed. The intermediate gate structures 108 ' -1, 108 ' -2, and 108 ' -3 shown in fig. 5A-5C may be cross-sectional views of metal gate structures having a filled gate metal. The metal gate structure with the filled gate metal may have more gate metal and lower gate resistance than the metal gate structure without the filled gate metal (e.g., the middle gate structures 108 ' -1, 108 ' -2, and 108 ' -3 shown in fig. 3A-3C).

In some embodiments, after forming the metal gate structures, the metal gate structures may be separated, and/or segmented along the x-axis or direction in which the metal gate structures extend to form short channel metal gate structures. For example, a metal gate structure may be located on a fin 104. In some embodiments, the channel length after separation and/or cutting is about 10 nm. Insulating material (e.g., silicon nitride and/or silicon oxide) may optionally be deposited over the separate metal gate structures to electrically isolate the metal gate structures from each other. In some embodiments, chemical mechanical polishing is performed to planarize the upper surface of the insulating material. In some embodiments, the foregoing process is referred to as a "last cut protocol".

In the embodiment of the invention, the method for replacing part of the work function metal layer with the conductive material can reduce the gate resistance of the metal gate structure. In some embodiments, other portions and/or layers of the metal gate structure may also be replaced with a conductive material (e.g., a conductive material having a desired resistance and/or doping level) to further reduce the gate resistance. For example, the top of the barrier metal layer and the top of the workfunction metal layer may be removed (or selectively removed) together to further increase the amount of gate metal in the metal gate structure. One or more etch back processes may be performed. In summary, the etchant used to remove these portions can be adjusted to form a self-assembled monolayer on the etched surface and improve adhesion between other layers exposed on the etched surface and the subsequently deposited conductive material. In addition, a suitable conductive material may be formed (or selectively formed) in the etch-back trench to fill the metal gate structure. Specific methods and structures may be had by reference to the embodiments of the invention and are not described in detail herein.

Compared with other schemes, the metal gate structure formed by the method and the structure disclosed by the embodiment of the invention has lower gate resistance. A selective etch may be performed to remove the top of the workfunction metal layer and form a self-assembled monolayer on the inside surface of the etched portion to improve adhesion between the subsequently deposited filler gate metal and the workfunction metal layer. A selective deposition may be performed to fill the etched portions with a fill gate metal. The filled gate metal has a relatively low or low gate resistance compared to the original gate metal material. For metal gate structures with little or no gate metal layer on the work function metal layer prior to the gate metal filling process, the gate metal may be deposited into the gate metal structure after the filling process and the gate resistance may be reduced. For metal gate structures that have sufficient gate metal in the gate metal layer filled prior to the gate metal filling process, more gate metal (or conductive material having a relatively low or lower resistance) may be included in the metal gate structure to further reduce the gate resistance. In some embodiments, the selective etching and selective deposition do not require an additional mask for the process, and thus no additional fabrication processes are required in forming the semiconductor structure 100. In some embodiments, the selective etch has little or no effect on gate dimensions (e.g., gate height). In some embodiments, the gate height of the metal gate structure is reduced by up to about 10% after a fabrication process, such as an etch-back process.

Fig. 6 is a flow diagram of an exemplary method 600 of forming a metal gate structure with a filled gate metal. Other fabrication processes may be performed between the various steps of the method 600, but the related description is omitted herein for the sake of brevity. The fabrication process shown in fig. 6 may also be performed in a different order. Any variation of the described fabrication steps is within the scope of embodiments of the present invention. For ease of explanation, the term "first metal gate structure" refers to the metal gate structure prior to performing the disclosed method, and "second metal gate structure" refers to the metal gate structure formed using the disclosed method.

In step 601, a substrate is provided. The substrate may include a first metal gate structure having a work function metal layer. The first metal gate structure may be formed from a gate replacement process and may also include other layers surrounding the work function metal layer, such as a high-k dielectric layer, a capping layer, a barrier layer, or the like. In some embodiments, the first metal gate structure has a small gate length and may include little or no gate metal on the work function metal layer. In some embodiments, the first metal gate structure has insufficient gate metal on the work function metal layer. The substrate may comprise any suitable semiconductor material. The work function metal layer may comprise a suitable material having a desired work function, such as titanium nitride. The gate metal may comprise a suitable conductive material, such as tungsten. Details of the first metal gate structure may be provided in fig. 3A-3C and related description.

In step 602, a selective etch is used to remove the top of the workfunction metal layer. An etchant having a desired etch selectivity may be dispensed onto the wafer and/or substrate to perform the selective etching. In some embodiments, the etchant has a desired higher etch selectivity for the work function metal layer of the first metal gate structure and other materials (e.g., gate metal). In some embodiments, the time of the selective etch may be controlled to remove a desired amount (e.g., depth) of the top of the workfunction metal layer. After the etching process, an etch-back trench may be formed in the work function metal layer, and a topmost surface of the work function metal layer may be exposed. In some embodiments, the gate fill metal layer comprises tungsten and the work function metal layer comprises titanium nitride, and the mixture used for the selective etch comprises phosphoric acid, hydrogen peroxide, and hot deionized water. In some embodiments, the etchant has five times higher selectivity to titanium nitride than to tungsten. In some embodiments, the exposed inner surface of the etch-back trench also comprises other layers surrounding the workfunction metal layer, such as a filled gate metal layer and/or a barrier metal layer. The etchant reacts with the material exposed in the etched back trench and forms a self-assembled monolayer on the exposed surface of the etched back trench. The self-assembled monolayer may improve adhesion between the exposed inner surface of the etched-back trench and a subsequently deposited filler gate metal. In some embodiments, the self-assembled monolayer improves adhesion between a subsequently formed filled gate metal and a work function metal layer and reduces and/or eliminates voids between the filled gate metal and the filled gate metal layer. The composition details of the etchant and the self-assembled monolayer are as described above in conjunction with fig. 4A-4C.

In step 603, a conductive material is deposited into the etch-back trench in the workfunction metal layer to form a second metal gate structure. The conductive material may be referred to as a filled gate metal. A selective deposition process may be employed to deposit a suitable conductive material, which may be the same or different from the layer of filled gate metal. In-situ doping may be employed to increase the doping level of the conductive material, and thus the gate resistance of the second metal gate structure may be further reduced. In some embodiments, atomic layer deposition is performed to selectively deposit a conductive material into the etch-back trench. In some embodiments, the gate-fill metal layer of the first metal gate structure comprises tungsten, the gate-fill metal comprises tungsten, and boron is doped into the gate-fill metal via in-situ doping. Meanwhile, the self-assembled monolayer on the inner side surface of the etched groove can improve the adhesion between the gate-filled metal and the work function metal layer and also improve the adhesion between the gate-filled metal and the gate-filled metal layer. In some embodiments, an atomic layer deposition process may be performed using precursor gases of tungsten pentachloride gas and hydrogen gas. Solid tungsten may be selectively formed in the etch-back trench. In some embodiments, the flow rate of tungsten pentachloride is between about 50 standard cubic centimeters per minute (sccm) to about 100sccm, and the hydrogen flow rate may be between about 1000sccm to about 2000 sccm. Tungsten pentachloride may be supported by argon to pump into a reaction chamber at a temperature between about 450 c to about 550 c, such that the chamber pressure may be about 40 Torr. Hydrogen gas may be pumped into the reaction chamber such that the chamber pressure may be about 60 Torr. Optionally, a chemical mechanical polish is performed to planarize the top surface of the second metal gate structure. The gate metal fill is described in detail above with reference to fig. 5A-5C.

The method 600 may optionally further comprise step 604. In step 604, the second metal gate structure may be cut and/or separated along the direction of fin 104 to form a short channel structure. An insulating material, such as silicon nitride, may be used to fill the spaces between adjacent short channel structures, insulating the short channel structures from each other. In some embodiments, chemical mechanical polishing is performed to planarize the short channel structure.

Embodiments of the present invention illustrate a selective etch-back process for a method of removing a work function metal surrounding a gate metal in a metal gate. A relatively low resistance or less resistive conductive material is then filled into the space created by the removal of the workfunction metal to increase the gate metal volume in the metal gate. A selective etch-back process forms a self-assembled monolayer over the etched portions. The self-assembled monolayer may improve adhesion between the etched portion and the newly deposited filled gate metal. The newly deposited fill gate metal (e.g., conductive material) may be deposited by selective deposition and may include desired and/or different dopant concentrations and/or species to further improve (e.g., reduce) gate resistance. The selective etch back and selective deposition do not require additional masks or additional fabrication processes. Thus, the gate height is not substantially affected (e.g., reduced) and more gate metal may be deposited into the metal gate. By adopting the method disclosed by the embodiment of the invention, the grid metal amount of the metal grid can be higher than that of the metal grid manufactured at the beginning, the grid resistance can be reduced, and the electrical property of the semiconductor device can be improved. In addition, the newly deposited filled gate metal may adhere to the etched portions of the metal gate with little (or no) voids formed therein. The gate metal formed may be more uniform. The gate resistance can be further reduced. Thus, the method and structure disclosed in the embodiments of the present invention can improve device performance.

In some embodiments, a finfet device, comprising: a substrate; a fin on the substrate; and a gate structure on the fin. The grid structure comprises a work function metal layer which is positioned on the inner side wall of the grid structure, and the topmost surface of the work function metal layer is lower than the upper surface of the grid structure; a gate-filled metal layer on a topmost surface of the work function metal layer, an upper surface of the gate-filled metal layer being substantially coplanar with an upper surface of the gate structure; and a self-assembled monolayer between the gate-filled metal layer and the work function metal layer.

In some embodiments, the self-assembled monolayer includes an adhesion layer between the work function metal layer and the filled gate metal layer.

In some embodiments, the finfet device further comprises an additional gate-filled metal layer surrounding the work function metal layer, and an upper surface of the additional gate-filled metal layer is substantially coplanar with an upper surface of the gate structure, wherein the self-assembled monolayer is between the additional gate-filled metal layer and the gate-filled metal layer.

In some embodiments, the self-assembled monolayer comprises: a first portion formed of a phosphate and a work function metal layer located between the work function metal layer and the filled gate metal layer; and a second portion formed by the phosphate and the other gate-filled metal layer, between the gate-filled metal layer and the other gate-filled metal layer.

In some embodiments, the finfet device further comprises a barrier metal layer surrounding the work-function metal layer, wherein a top surface of the barrier metal layer is substantially coplanar with a top surface of the gate structure, wherein the self-assembled monolayer further comprises a third portion formed by a phosphate and the barrier metal layer, the third portion being located between the barrier metal layer and the gate-filled metal layer.

In some embodiments, the filled gate metal layer and the other filled gate metal layer each comprise a common conductive material.

In some embodiments, the gate-filled metal layers have a first doping level, the other gate-filled metal layers have a second doping level, and the first doping level is higher than the second doping level.

In some embodiments, the work function metal layer comprises titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; the barrier metal layer comprises tantalum nitride or niobium nitride; each of the filled gate metal layer and the other filled gate metal layers comprises one or more of tungsten and aluminum; and the fill gate metal layer comprises boron.

In some embodiments, a first portion of the self-assembled monolayer comprises titanium oxide and phosphate, a second portion of the self-assembled monolayer comprises tungsten oxide and phosphate, and a third portion of the self-assembled monolayer comprises tantalum oxide and phosphate.

In some embodiments, a method of forming a semiconductor device includes: providing a substrate, wherein the substrate comprises a grid structure with a work function metal layer; removing the top of the work function metal layer; forming a self-assembled monolayer on a topmost surface of the work function metal layer exposed by removing a top of the work function metal layer; and depositing a fill gate metal layer into the removed top portion of the work function metal layer with the self-assembled monolayer between the fill gate metal layer and the work function metal layer.

In some embodiments, the step of removing the top portion of the work-function metal layer comprises performing a selective etch-back that etches the work-function metal layer at a higher rate than other materials of the substrate.

In some embodiments, the work function metal layer comprises titanium nitride, titanium aluminum nitride, or titanium aluminum carbide; and the step of performing the selective etch back includes using a mixture of hydrogen peroxide, phosphoric acid, and hot deionized water to remove the top of the work function metal layer at room temperature to 80 ℃.

In some embodiments, the step of selectively etching back further comprises forming a self-assembled monolayer on the work-function metal layer, and wherein the self-assembled monolayer comprises a portion formed by the mixture and the work-function metal layer.

In some embodiments, the step of depositing a gate fill metal layer into the top portion of the removed work function metal layer comprises selectively depositing a gate metal into the top portion of the removed work function metal layer, and the self-assembled monolayer is an adhesion layer between the gate fill metal layer and the work function metal layer.

In some embodiments, the substrate further comprises an additional filled gate metal layer surrounded by the work function metal layer, wherein the selectively etching back further comprises forming another portion of the self-assembled monolayer on the additional filled gate metal layer, the other portion of the self-assembled monolayer being formed from the mixture with the additional filled gate metal layer, and the additional filled gate metal layer being bonded to the filled gate metal layer via the other portion of the self-assembled monolayer.

In some embodiments, the step of depositing the gate-fill metal layer includes performing atomic layer deposition and in-situ doping processes, and wherein the gate-fill metal layer and the other gate-fill metal layer include a common conductive material.

In some embodiments, the common conductive material comprises tungsten; and the doping level of the gate-filled metal layer is higher than the doping levels of the other gate-filled metal layers, and the gate-filled metal layer comprises boron.

In some embodiments, a method of forming a semiconductor device includes: providing a substrate, wherein the substrate comprises a grid structure; selectively removing the top of the gate structure; forming an adhesive layer on the upper surface of the gate structure exposed by removing the top of the gate structure; and selectively depositing a conductive layer on the adhesive layer on the removed top of the gate structure, wherein the adhesive layer adheres the upper surface of the gate structure exposed by the removed top of the gate structure and the conductive layer.

In some embodiments, the doping level of the conductive layer is higher than the doping level of the top of the removed gate structure.

In some embodiments, the step of selectively removing the top portion of the gate structure comprises a selective etching process, and the step of depositing the conductive layer comprises a selective deposition process and an in-situ doping process.

It is to be understood that paragraphs (not abstract) of the embodiments may be used to interpret the claims. The abstract may describe one or more but not all exemplary embodiments, and thus the appended claims are not to be limited.

Features of the above-described embodiments or examples may be helpful to one skilled in the art in understanding embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that such equivalent substitutions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.