Semiconductor structure and semiconductor manufacturing method
阅读说明:本技术 半导体结构及半导体制造方法 (Semiconductor structure and semiconductor manufacturing method ) 是由 郑新立 张聿骐 于 2019-07-26 设计创作,主要内容包括:本发明实施例是有关半导体结构及半导体制造方法。所述半导体结构包含:衬底;有源区域,其包含夹置于两个源极/漏极区之间的沟道区;绝缘区,其从俯视图围绕所述有源区域;及电介质层,其放置在所述绝缘区与所述源极/漏极区之间的界面上方且与所述界面接触。本发明实施例还公开一种制造半导体结构的方法。(Embodiments of the present invention relate to semiconductor structures and semiconductor fabrication methods. The semiconductor structure includes: a substrate; an active region comprising a channel region sandwiched between two source/drain regions; an insulating region surrounding the active region from a top view; and a dielectric layer placed over and in contact with an interface between the insulating region and the source/drain region. The embodiment of the invention also discloses a method for manufacturing the semiconductor structure.)
1. A semiconductor structure, comprising:
a substrate;
an active region comprising a channel region and two source/drain regions, the channel region being sandwiched between the two source/drain regions;
an insulating region surrounding the active region from a top view; and
a dielectric layer placed over and covering an interface between the insulating region and the source/drain region.
2. The semiconductor structure of claim 1, further comprising at least one metal silicide member over and in contact with the active region, wherein the metal silicide member does not extend to the interface between the insulating region and the source/drain regions, wherein the metal silicide member laterally abuts the dielectric layer.
3. The semiconductor structure of claim 1, wherein the dielectric layer comprises silicon oxide, silicon nitride, or silicon oxynitride.
4. The semiconductor structure of claim 2, further comprising a contact etch stop layer over the dielectric layer and the metal silicide member, and further comprising a contact through the contact etch stop layer and in contact with the metal silicide member.
5. The semiconductor structure of claim 1, wherein the dielectric layer overlaps the source/drain regions with an overlap width substantially greater than about 0.2 μ ι η.
6. The semiconductor structure of claim 1, wherein a thickness of the dielectric layer is in a range from about 200 to 600 angstroms.
7. A semiconductor structure, comprising:
a semiconductor substrate;
a gate structure over the semiconductor substrate, the gate structure extending in a first direction;
an active area pattern in the semiconductor substrate, the active area pattern extending in a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction;
an insulating region surrounding the active region pattern;
a first dielectric strip over the semiconductor substrate, wherein the first dielectric strip directly covers at least an interface between the first edge of the active area pattern and the insulating region; and
a second dielectric strip over the semiconductor substrate, the second dielectric strip spaced apart from the first dielectric strip, wherein the second dielectric strip directly covers at least an interface between the second edge of the active area pattern and a second insulating region.
8. The semiconductor structure of claim 7, further comprising one silicide layer over and in contact with the active area pattern, wherein the silicide layer is between the first dielectric strip and the second dielectric strip, and further comprising a contact etch stop layer over the first dielectric strip, the second dielectric strip, and the silicide layer, and further comprising a contact through the contact etch stop layer and in contact with the silicide layer.
9. A method of fabricating a semiconductor structure, comprising:
receiving a semiconductor substrate;
forming an insulating region in the semiconductor substrate to define an active region in the semiconductor substrate;
forming a gate structure across the active region defined in the semiconductor substrate;
forming a source or drain region in the active region, wherein the source or drain region abuts the insulating region; and
forming a photoresist protective dielectric film over the source or drain region, the insulating region, and the gate structure, wherein the photoresist protective dielectric film overlaps an interface between the source or drain region and the insulating region and exposes a portion of the source or drain region and a portion of the gate structure.
10. The method of claim 9, further comprising:
forming a metal layer over the exposed portion of the source or drain region and the exposed portion of the gate structure; and
annealing the semiconductor substrate.
Technical Field
Embodiments of the present invention relate to semiconductor structures and semiconductor fabrication methods.
Background
Shallow Trench Isolation (STI) is widely used in semiconductor manufacturing to provide isolation of active areas on a substrate. However, STI is susceptible to noise and leakage problems. Therefore, there is a need to alleviate the above problems.
Disclosure of Invention
An embodiment of the present invention relates to a semiconductor structure, which includes: a substrate; an active region comprising a channel region and two source/drain regions, the channel region being sandwiched between the two source/drain regions; an insulating region surrounding the active region from a top view; and a dielectric layer placed over and covering an interface between the insulating region and the source/drain region.
An embodiment of the present invention relates to a semiconductor structure, which includes: a semiconductor substrate; a gate structure over the semiconductor substrate, the gate structure extending in a first direction; an active area pattern in the semiconductor substrate, the active area pattern extending in a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction; an insulating region surrounding the active region pattern; a first dielectric strip over the semiconductor substrate, wherein the first dielectric strip directly covers at least an interface between the first edge of the active area pattern and the insulating region; and a second dielectric strip over the semiconductor substrate, the second dielectric strip being spaced apart from the first dielectric strip, wherein the second dielectric strip at least directly covers an interface between the second edge of the active area pattern and a second insulating region.
One embodiment of the present invention relates to a method of fabricating a semiconductor structure, comprising: receiving a semiconductor substrate; forming an insulating region in the semiconductor substrate to define an active region in the semiconductor substrate; forming a gate structure across the active region defined in the semiconductor substrate; forming a source or drain region in the active region, wherein the source or drain region abuts the insulating region; and forming a photoresist protective dielectric film over the source or drain region, the insulating region, and the gate structure, wherein the photoresist protective dielectric film overlaps an interface between the source or drain region and the insulating region and exposes a portion of the source or drain region and a portion of the gate structure.
Drawings
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various components are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1-2 illustrate cross-sectional views of a semiconductor device in process;
3A, 4A, 5A, 6A and 7A are diagrams illustrating fragment layout views of a semiconductor device at various stages of fabrication, according to some embodiments of the present disclosure; and
fig. 3B, 4B, 5B, 6B, and 7B are diagrams illustrating fragmentary cross-sectional views of a semiconductor device at various stages of fabrication, according to some embodiments of the present disclosure.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different components of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, such are merely examples and are not intended to be limiting. For example, a first means formed over or on a second means in the following description may include embodiments in which the first means and the second means are formed in direct contact, and may also include embodiments in which additional means may be formed between the first means and the second means, such that the first means and the second means may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Moreover, for ease of description, spatially relative terms such as "below …," "below …," "below," "above …," "on," and the like may be used herein to describe one element or component's relationship to another element(s) or component, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Also, as used herein, the term "about" generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" means within an acceptable standard error of the mean, as considered by the ordinary artisan. Except in the operating/working examples, or where otherwise expressly specified, all numerical ranges, amounts, values and percentages (e.g., for amounts of materials, durations, temperatures, operating conditions, ratios of amounts, and the like disclosed herein) are to be understood as modified in all instances by the term "about". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that may vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to the other end point or between the two end points. All ranges disclosed herein are inclusive of the endpoints unless otherwise specified.
In the integrated circuit industry today, hundreds of thousands of semiconductor devices are built on a single chip. Each device on the chip must be electrically isolated to ensure that it operates independently without disturbing the other device. The technology of isolating semiconductor devices has become an important aspect of modern Metal Oxide Semiconductor (MOS), particularly MOS employed by fully customized integrated circuit designs and bipolar integrated circuit technology for separating different devices or different functional regions. With the high integration of semiconductor devices, improper electrical isolation in the device will result in current leakage, and current leakage can consume large amounts of power as well as compromise functionality. Some examples of reduced functionality include latch-up, noise margin degradation, voltage offset, and cross-talk, which can temporarily or permanently damage the circuit.
Shallow Trench Isolation (STI) for semiconductor chip with high integrationElectrical isolation of the sheet. STI structures may be fabricated using a variety of methods including, for example, Buried Oxide (BOX) isolation methods for shallow trenches. The BOX method involves oxidizing Silicon (SiO) by Chemical Vapor Deposition (CVD) 2) Filling the trench followed by planarization of Chemical Vapor Deposition (CVD) silicon oxide (SiO) by a plasma etch-back process and/or a Chemical Mechanical Polishing (CMP) process 2) To produce a flat surface. Shallow trenches etched for the BOX process are anisotropically plasma etched into the substrate (e.g., silicon), and typically between about 0.3 microns and about 1.0 micron deep.
A silicide layer is typically formed on top of silicon structures in a semiconductor device, such as polysilicon gates, source/drain regions, and local interconnects, in order to reduce contact resistance when forming gate or source/drain contacts. In the process of forming the silicide layer, a dielectric layer may be used to cover portions of the silicon structure and expose predetermined areas. A metal layer is blanket deposited over the dielectric layer and the exposed areas. A thermal treatment is then performed to promote a chemical reaction in which the metal layer contacts the silicon structure to form a silicide layer. Since the dielectric layer shields a portion of the semiconductor device from the metal layer, a silicide layer will not be formed on the portion covered by the dielectric layer during the heat treatment. The unreacted portions of the metal layer are then stripped, leaving the silicide layer on the desired areas.
Fig. 1-2 illustrate cross-sectional views of a
In the
The process of etching the
Fig. 3A, 4A, 5A, 6A, and 7A are diagrams illustrating fragment layout views of a
Referring to fig. 3A, the
An exemplary material for the
With respect to
In some embodiments, the
The
The gate spacers 43 may be formed by depositing a dielectric layer(s) and then patterning the dielectric layer to remove horizontal portions deposited on the
With respect to
Referring to fig. 4A, a
Referring to fig. 5A, a portion of the
In some embodiments, the remaining dielectric layer 306_1 overlaps a portion of the
In some embodiments, the left and right ends of each of the remaining dielectric layers 306_1 and 306_2 may be aligned with the leftmost edge 302_3 and the rightmost edge 302_4 of the
Referring to fig. 5B, a portion of the
Fig. 7A and 7B illustrate the formation of an insulating dielectric layer 310, such as a Contact Etch Stop Layer (CESL), and contact plugs 314. An insulating dielectric layer 310 covers and contacts the
After forming insulating dielectric layer 310, ILD layer 312 is formed. ILD layer 312 may be formed by a suitable technique, such as Chemical Vapor Deposition (CVD). For example, high density plasma CVD may be performed to form ILD layer 312. The ILD layer 312 may be formed on the
Contact openings are then formed in ILD 312 and insulating dielectric layer 310 by a photolithography process and an etching process comprising one or more etching steps such that
Next, contact plugs 314 are formed in the contact openings to contact the
In many embodiments, an interconnect structure may be further formed on ILD layer 312. The interconnect structure may include vertical interconnects (e.g., conventional vias or contacts) and horizontal interconnects (e.g., metal lines). Interconnect structures may implement a variety of conductive materials including copper, tungsten, and silicide. In one example, a copper related interconnect structure is formed using a damascene process. Although the
Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a substrate; an active region comprising a channel region sandwiched between two source/drain regions; an insulating region surrounding the active region from a top view; and a dielectric layer placed over and in contact with an interface between the insulating region and the source/drain region.
Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate, the gate structure extending in a first direction; an active area pattern in the semiconductor substrate, the active area pattern extending in a second direction perpendicular to the first direction, wherein the active area pattern includes a first edge and a second edge along the second direction; an insulating region surrounding the active region pattern; a first dielectric strip over the semiconductor substrate, wherein the first dielectric strip directly covers at least an interface between the first edge of the active area pattern and the insulating region; and a second dielectric strip over the semiconductor substrate, the second dielectric strip being spaced apart from the first dielectric strip, wherein the second dielectric strip at least directly covers an interface between the second edge of the active area pattern and a second insulating region.
Some embodiments of the present disclosure provide a method of fabricating a semiconductor structure. The method comprises the following steps: receiving a semiconductor substrate; forming an insulating region in the semiconductor substrate to define an active region in the semiconductor substrate; forming a gate structure across the active region defined in the semiconductor substrate; forming a source or drain region in the active region, wherein the source or drain region abuts the insulating region; and forming a photoresist protective dielectric film over the source or drain region, the insulating region, and the gate structure, wherein the photoresist protective dielectric film overlaps an interface between the source or drain region and the insulating region and exposes a portion of the source or drain region and a portion of the gate structure.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Description of the symbols
10 semiconductor device
32 gate dielectric
34 gate electrode
43 Gate spacer
101 Shallow Trench Isolation (STI)
102 first region
103 second region
104 semiconductor substrate
105 gate oxide layer
106 gate electrode
107 spacer liner
108 spacer
109 source/drain regions
110 resistor
111 insulator layer
112 dielectric layer
113 photoresist mask
115 pit
300 semiconductor device
300A cross-sectional view
300B cross-sectional view
301 semiconductor substrate
302 active area pattern
302_1 topmost edge
302_2 bottommost edge
302_3 leftmost edge
302_4 rightmost edge
303 insulating region
304 gate structure
305 opening
306 dielectric layer
306_1 residual dielectric layer
306_2 residual dielectric layer
307 top surface
308 silicide region
310 insulating dielectric layer
312 interlayer dielectric (ILD) layer
314 contact plug
d1 overlap width
d2 overlap width
d3 width
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