阅读说明：本技术 基于沟槽栅垂直浅超结的氮化镓基mosfet器件及制作方法 (Gallium nitride based MOSFET device based on trench gate vertical shallow super junction and manufacturing method ) 是由 刘爽 赵胜雷 张进成 刘志宏 宋秀峰 郝跃 于 2019-11-01 设计创作，主要内容包括：本发明公开了一种基于沟槽栅垂直浅超结的氮化镓基MOSFET器件,主要解决现有技术击穿电压较低,漂移区电场集中的问题。包括衬底、漂移层、P-柱层、P+层、n+层、栅介质层、源极、漏极、栅极和钝化层。其中,漂移层位于衬底的上部,P-柱层位于漂移层中,P-柱层两侧的上方依次为P+层和n+层,栅介质层位于n+层上部,源极位于栅介质层两侧,漏极位于衬底下部；栅极位于栅介质层上部,且采用凹槽结构,该凹槽位于漂移层、P+层和n+层的中间,钝化层位于栅极和源极之间。本发明通过在漂移层中淀积的P-柱层,拓展了PN结耗尽区,减少了工艺复杂性和泄漏电流,提高了器件的击穿电压和可靠性,可作为高功率系统及电力电子开关。(The invention discloses a gallium nitride-based MOSFET (metal oxide semiconductor field effect transistor) device based on a vertical shallow super junction of a trench gate, which mainly solves the problems of low breakdown voltage and concentrated electric field of a drift region in the prior art. The device comprises a substrate, a drift layer, a P-column layer, a P + layer, an n + layer, a gate dielectric layer, a source electrode, a drain electrode, a grid electrode and a passivation layer. The drift layer is positioned at the upper part of the substrate, the P-column layer is positioned in the drift layer, the P + layer and the n + layer are sequentially arranged above two sides of the P-column layer, the gate dielectric layer is positioned at the upper part of the n + layer, the source electrode is positioned at two sides of the gate dielectric layer, and the drain electrode is positioned at the lower part of the substrate; the grid electrode is positioned on the upper part of the grid dielectric layer and adopts a groove structure, the groove is positioned among the drift layer, the P + layer and the n + layer, and the passivation layer is positioned between the grid electrode and the source electrode. The invention expands PN junction depletion region, reduces process complexity and leakage current, improves breakdown voltage and reliability of the device, and can be used as high power system and power electronic switch.)

1. A gallium nitride-based MOSFET device based on a vertical shallow super junction of a trench gate comprises a substrate (1), a drift layer (2), a P-column layer (3), a P + layer (4), an n + layer (5), a gate dielectric layer (6), a source electrode (7), a drain electrode (8), a grid electrode (9) and a passivation layer (10). The drift layer (2) is positioned at the upper part of the substrate (1), the P-column layer (3) is positioned in the drift layer (2), the P + layer (4) and the n + layer (5) are sequentially arranged above two sides of the P-column layer (3), the gate dielectric layer (6) is positioned at the upper part of the n + layer (5), the source electrode (7) is positioned at two sides of the gate dielectric layer (6), and the drain electrode (8) is positioned at the lower part of the substrate (1); the grid electrode (9) is positioned on the upper portion of the grid dielectric layer (6), a groove structure is adopted, the groove is positioned among the drift layer (2), the P + layer (4) and the n + layer (5), the passivation layer (10) is positioned between the grid electrode (9) and the source electrode (7), and the grid electrode structure is characterized in that the P-column layer (3) is arranged in the drift layer (2) and used for expanding a PN junction depletion region and improving the breakdown voltage of a device.

2. The device is characterized in that a P-column layer (3) is arranged in the drift layer (2) and used for expanding a PN junction depletion region and improving the breakdown voltage of the device.

3. The device of claim 1, wherein the gate electrode has a recessed structure.

4. Device according to claim 1, characterized in that the P-pillar layer (3) has a doping concentration of 10 ¹⁶cm ^-3～10 ¹⁸cm ^-3And a thickness not exceeding 1/2 the thickness of the drift region (2).

5. The device according to claim 1, characterized in that the gate dielectric layer (6) and the passivation layer (10) are made of SiN or SiO ₂Or Al ₂O ₃Or HfO ₂A medium.

6. A method for manufacturing a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction is characterized by comprising the following steps:

1) cleaning and pretreating the surface of the substrate to eliminate surface dangling bonds, and removing the dangling bonds at H ₂Removing surface pollutants by heat treatment in an atmosphere reaction chamber at the temperature of 900-1200 ℃;

2) depositing GaN with the thickness of 5-20 mu m on the substrate after the heat treatment by adopting an MOCVD (metal organic chemical vapor deposition) process to be used as a drift layer of the device;

3) selectively etching the drift region, selecting a region to be etched and etching a window exposing the P-column layer, wherein the thickness of the etched window is not more than 1/2 of the thickness of the drift region;

4) epitaxial doping concentration at exposed window is 10 ¹⁶cm ^-3～10 ¹⁸cm ^-3A P-column layer of (a);

5) depositing a P + layer with the thickness of 100 nm-1000 nm on the drift region and the P-column layer by adopting an MOCVD (metal organic chemical vapor deposition) process, wherein the doping concentration of the P + layer is 10 ¹⁸cm ^-3～10 ¹⁹cm ^-3；

6) Depositing an n + layer with the thickness of 100 nm-1000 nm on the P + layer by adopting an MOCVD process, wherein the doping concentration of the n + layer is 10 ¹⁸cm ^-3～10 ¹⁹cm ^-3；

7) Manufacturing a mask, exposing a source electrode window by adopting an etching process, wherein the thickness of the source electrode window extends into 10-50 nm of the P + layer, depositing source electrode metal on the window to be deposited by adopting a magnetron sputtering process, and depositing drain electrode metal which is the same as that of the source electrode on the back side of the device;

8) manufacturing a mask, exposing a grid window by adopting an etching process, wherein the thickness of the grid window extends into 10-50 nm of a drift layer, depositing a grid dielectric layer on a grid window to be deposited, and then depositing grid metal on the grid dielectric layer;

9) placing the epitaxial wafer subjected to the steps into a PECVD reaction chamber, and carrying out passivation layer deposition;

10) and photoetching and etching the passivation layer of the gate electrode and the passivation layer of the source electrode to form a gate contact hole and a source contact hole, thereby finishing the manufacture of the device.

7. The method of claim 6, wherein: the MOCVD process parameters of the step 2), the step 4), the step 5) and the step 6) are as follows:

the pressure in the reaction chamber was: the temperature of the molten metal is 10 to 100Torr,

the Ga source flow is: 10-100 mu mol/min of the mixture,

the flow of ammonia gas is as follows: 800-6000sccm,

the hydrogen flow rate was: 1000-.

8. The method as claimed in claim 6, wherein the magnetron sputtering process in step 7) is performed under the condition that aluminum, titanium, nickel, permalloy, tungsten, lead and gold with a purity of 99.999% are used as the target material, and the pressure in the reaction chamber is kept within a range of 8.6 to 9.4 x 10 ^{- 2}Pa. And the source electrode metal deposited on the window to be deposited and the drain electrode metal on the back side adopt metal combination of Ti/Al or Ti/Al/Ni/Au or Ti/Al/Mo/Au.

9. The method of claim 7, wherein the gate metal deposited on the gate dielectric layer in step 8) is a combination of metals of Ni/Au/Ni or Ti/Au or Ti/Pt/Au, wherein the thickness of the first layer of metal Ni or Ti is 20to 80nm, the thickness of the second layer of metal Au or Pt is 50 to 300nm, and the thickness of the third layer of metal Ni or Au is 20to 300 nm.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride-based MOSFET device which can be used for electric energy conversion of power electronic equipment and circuit control under high-voltage and high-current density.

Background

The high-power semiconductor device is applied to electric energy conversion of power electronic equipment and circuit control under high voltage and high current density, and with the increasingly reduced available environmental resources of human beings, the development of a novel power device with excellent performance and high conversion efficiency is one of effective schemes for effectively solving energy and environmental conflicts. For a high-power semiconductor device, the power quality factor of the high-power semiconductor device mainly depends on the breakdown voltage and the specific on-resistance of the device, but both of the devices often need to be optimized and designed comprehensively to effectively improve the performance of the power device. With the continuous development of the field of semiconductor power devices, the performance of the power devices is fundamentally changed from the first generation of Si materials to the second generation of GaAs materials. However, so far, the performance of semiconductor power devices made of traditional two-generation materials has approached the theoretical limit determined by the material properties. The third generation semiconductor broadband materials represented by GaN have the characteristics of high frequency, high power, radiation resistance, high saturated electron mobility and the like, and have excellent potential in the aspect of power electronics. Compared with the traditional transverse device, the vertical power device of the trench gate vertical MOSFETs device can improve the breakdown characteristic of the device only by increasing the thickness of the drift region of the device without sacrificing the transverse size of a chip, so that the vertical power device has high power density and is suitable for power electronic switching devices. The vertical devices with mature technical development at present mainly comprise a CAVET device and a trench gate MOSFET device, and the trench gate MOSFET device is developed more rapidly along with the improvement of a P-type GaN doping technology. Compared with a CAVET device, the trench gate MOSFET device is easier to realize an enhancement device, a current blocking layer in the CAVET device is not needed, an electric field is mainly concentrated in a body and is not easily influenced by an interface state, and the width of a current channel can reach a micron level. However, the activation rate of the P-type GaN hole of the trench gate MOSFET device is still low at present, so that a depletion region between a P + layer and a drift layer is limited by doping, the breakdown voltage of the device is low, the power quality factor of the device is influenced, and the high power performance of the trench gate MOSFET device is reduced.

Disclosure of Invention

The invention aims to provide a gallium nitride based MOSFET device based on a vertical shallow super junction of a trench gate and a manufacturing method thereof aiming at the defects of the prior device technology, so as to improve the breakdown characteristic of the device and improve the high output power performance of the device.

In order to achieve the purpose, the technical scheme of the invention is as follows:

1. a gallium nitride-based MOSFET device based on a vertical shallow super junction of a trench gate comprises a substrate, a drift layer, a P-column layer, a P + layer, an n + layer, a gate dielectric layer, a source electrode, a drain electrode, a grid electrode and a passivation layer. The drift layer is positioned at the upper part of the substrate, the P-column layer is positioned in the drift layer, the P + layer and the n + layer are sequentially arranged above two sides of the P-column layer, the gate dielectric layer is positioned at the upper part of the n + layer, the source electrode is positioned at two sides of the gate dielectric layer, and the drain electrode is positioned at the lower part of the substrate; the grid is positioned on the upper part of the grid dielectric layer, a groove structure is adopted, the groove is positioned among the drift layer, the P + layer and the n + layer, and the passivation layer is positioned between the grid and the source. The drift layer is provided with a P-column layer for expanding a PN junction depletion region and improving the breakdown voltage of the device.

Further, the gate electrode is characterized by adopting a groove structure.

Further, the substrate is made of a GaN bulk material.

Further characterized in that the P-pillar layer has a doping concentration of 10 ¹⁶cm ^-3～10 ¹⁸cm ^-3And a thickness not exceeding 1/2 a of the thickness of the drift region.

Further, it is characterized in that: the gate dielectric layer adopts SiN or SiO ₂Or Al ₂O ₃Or HfO ₂A medium.

Further, the passivation layer is made of SiN or SiO ₂Or Al ₂O ₃Or HfO ₂A medium.

2. A method for manufacturing a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction is characterized by comprising the following steps:

1) cleaning and pretreating the surface of the substrate to eliminate surface dangling bonds, and removing the dangling bonds at H ₂Removing surface pollutants by heat treatment in an atmosphere reaction chamber at the temperature of 900-1200 ℃;

2) depositing GaN with the thickness of 5-20 mu m on the substrate after the heat treatment by adopting an MOCVD (metal organic chemical vapor deposition) process to be used as a drift layer of the device;

3) selectively etching the drift region, selecting a region to be etched and etching a window exposing the P-column layer, wherein the thickness of the etched window is not more than 1/2 of the thickness of the drift region;

4) epitaxial doping concentration at exposed window is 10 ¹⁶cm ^-3～10 ¹⁸cm ^-3A P-column layer of (a);

5) depositing a P + layer with the thickness of 100 nm-1000 nm on the drift region and the P-column layer by adopting an MOCVD (metal organic chemical vapor deposition) process, wherein the doping concentration of the P + layer is 10 ¹⁸cm ^-3～10 ¹⁹cm ^-3；

6) Depositing an n + layer with the thickness of 100 nm-1000 nm on the P + layer by adopting an MOCVD process, wherein the doping concentration of the n + layer is 10 ¹⁸cm ^-3～10 ¹⁹cm ^-3；

7) Manufacturing a mask, exposing a source electrode window by adopting an etching process, wherein the thickness of the source electrode window extends into 10-50 nm of the P + layer, depositing source electrode metal on the window to be deposited by adopting a magnetron sputtering process, and depositing drain electrode metal which is the same as that of the source electrode on the back side of the device;

8) manufacturing a mask, exposing a grid window by adopting an etching process, wherein the thickness of the grid window extends into 10-50 nm of a drift layer, depositing a grid dielectric layer on a grid window to be deposited, and then depositing grid metal on the grid dielectric layer;

9) placing the epitaxial wafer subjected to the steps into a PECVD reaction chamber, and carrying out passivation layer deposition;

10) and photoetching and etching the passivation layer of the gate electrode and the passivation layer of the source electrode to form a gate contact hole and a source contact hole, thereby finishing the manufacture of the device.

Compared with the prior art, the invention has the following advantages:

firstly, the P-column layer is deposited in the drift layer, so that the P-column layer and the drift layer have interaction, and PN junction depletion regions can be increased in the length direction and the width direction of the P-column layer, so that the phenomenon of electric field peak concentration in the drift layer is weakened, the breakdown voltage of the device is improved, and high output power is realized;

secondly, the thickness of the P-column layer deposited in the drift layer is not more than half of the thickness of the drift layer, so that the drift layers on two sides do not need to be completely etched, and the process cost is optimized and reduced;

thirdly, because the newly deposited P-column layer replaces the original part of the drift layer, the leakage current between the grid and the drain is reduced when the device is conducted, and the static power consumption of the vertical power device is further reduced.

Drawings

Fig. 1 is a structural diagram of a gallium nitride-based MOSFET device based on a trench-gate vertical shallow super junction according to the present invention.

Fig. 2 is a flow chart illustrating the fabrication of the device of fig. 1 according to the present invention.

Detailed Description

The invention is described in further detail below with reference to the figures and examples.

Referring to fig. 1, the gallium nitride-based MOSFET device with a trench gate vertical shallow super junction of the present invention includes a substrate 1, a drift layer 2, a P-column layer 3, a P + layer 4, an n + layer 5, a gate dielectric layer 6, a source 7, a drain 8, a gate 9, and a passivation layer 10. The drift layer 2 is positioned at the upper part of the substrate 1, the P-column layer 3 is positioned in the drift layer 2, a P + layer 4 and an n + layer 5 are sequentially arranged above two sides of the P-column layer 3, the gate dielectric layer 6 is positioned at the upper part of the n + layer, the source electrode 7 is positioned at two sides of the gate dielectric layer 6, and the drain electrode 8 is positioned at the lower part of the substrate 1; the grid electrode 9 is positioned on the upper part of the grid dielectric layer 6 and adopts a groove structure, the groove is positioned among the drift layer 2, the P + layer 4 and the n + layer 5, and the passivation layer 10 is positioned between the grid electrode 9 and the source electrode 7.

The substrate 1 is made of a GaN bulk material;

the drift layer 2 is made of GaN, and the thickness of the drift layer is 5-20 microns;

the P-column layer 3 is made of GaN, and the thickness of the P-column layer is 0.1-10 mu m;

the P + layer 4 is made of GaN, and the thickness of the GaN is 50-1000 nm;

the n + layer 5 is made of GaN, and the thickness of the n + layer is 50-500 nm;

the passivation layer 6 adopts SiN or SiO ₂Or Al ₂O ₃Or HfO ₂And the like;

the source electrode metal and the drain electrode metal are combined by adopting metal layers of Ti/Al or Ti/Al/Ni/Au or Ti/Al/Mo/Au, and the grid electrode metal is combined by adopting metal layers of Ni/Au/Ni or Ni/Au or W/Au or Mo/Au.

Referring to fig. 2, the invention manufactures a gallium nitride-based MOSFET device based on a trench gate vertical shallow super junction, and three embodiments are given as follows: