阅读说明：本技术 一种智能毛刺设计电路 (Intelligent burr design circuit ) 是由 徐九八 苏军恒 吴国良 赵永锁 杜磊 李海滨 于 2019-11-26 设计创作，主要内容包括：本发明提供一种智能毛刺设计电路。所述智能毛刺设计电路包括FPGR核心板,所述FPGR核心板连接有第一DA转换模块、第二DA转换模块、DA模块、快速开关和USB转串口模块,所述USB转串口模块连接有PC,所述第一DA转换模块连接有运算放大器和ARM处理器,所述运算放大器连接有第二加法器,所述第二加法器连接有第一加法器、电流放大器和可调稳压LDO,所述第一加法器和所述DA模块均与所述快速开关,所述第一加法器连接有测试设备,所述测试设备与所述电流放大器相连接。本发明提供的智能毛刺设计电路具有可以产生任意毛刺信号,幅度可调,时间可控,精度高,信号稳定,无失真,可调节毛刺频率和相位的优点。(The invention provides an intelligent burr design circuit. Intelligence burr design circuit includes FPGR core plate, FPGR core plate is connected with first DA conversion module, second DA conversion module, DA module, fast switch and USB and changes serial port module, USB changes serial port module and is connected with PC, first DA conversion module is connected with operational amplifier and ARM treater, operational amplifier is connected with the second adder, the second adder is connected with first adder, current amplifier and adjustable steady voltage LDO, first adder with the DA module all with fast switch, first adder is connected with test equipment, test equipment with current amplifier is connected. The intelligent burr design circuit provided by the invention has the advantages of capability of generating any burr signal, adjustable amplitude, controllable time, high precision, stable signal, no distortion and adjustable burr frequency and phase.)

1. An intelligent glitch design circuit, comprising: core plate of FPGR, core plate of FPGR is connected with first DA conversion module, second DA conversion module, DA module, fast switch and USB and changes serial module, USB changes serial module and is connected with PC, first DA conversion module is connected with operational amplifier and ARM treater, operational amplifier is connected with the second adder, the second adder is connected with first adder, current amplifier and adjustable steady voltage LDO, first adder with the DA module all with fast switch, first adder is connected with test equipment, test equipment with current amplifier is connected, adjustable steady voltage LDO with second DA conversion module is connected, adjustable steady voltage LDO is connected with switching power supply, switching power supply is connected with DC/DC module.

2. The intelligent glitch design circuit of claim 1 in which the output voltage of the switching power supply is 12V.

3. The intelligent glitch design circuit of claim 1 in which the output voltage of the DC/DC module is +5V and-5V.

4. The intelligent glitch design circuit of claim 1, wherein the output level of the adjustable regulated LDO is 0-5V.

Technical Field

The invention relates to the technical field of irrigation, in particular to an intelligent burr design circuit.

Background

The glitch attack technique is an attack of invading (hack) a smart card by applying an abnormal signal to a power signal or an externally provided signal, so that the smart card operates unpredictably. For example, a glitch is applied to an operating voltage used to drive a chip in a smart card to steal data from an electrically erasable programmable read-only memory (EEPROM). Thus, the smart card may include a glitch detector that detects a sudden increase or decrease in voltage.

Voltage glitch attacks are made by rapidly changing the voltage input to the chip, causing some transistors in the chip to be affected, causing one or more flip-flops to enter an error state, thereby causing the processor to skip or implement an erroneous operation, causing information hidden in the chip to leak out along with the resulting error. A glitch attack is one of the injection defect attacks and its principle is to affect its normal operation by rapidly changing the signal input to the microcontroller. The voltage is applied to the gate by the gate, but the gate may be applied with a short electric field or electromagnetic pulse. Each transistor and the lines connected to it form an RC circuit with a time delay characteristic, the maximum available clock frequency of the processor being dependent on the maximum delay of the circuit. Likewise, each flip-flop has a characteristic time window between receiving the input voltage and the resulting output voltage. Each window is determined by a given voltage and temperature. If clock glitches or power supply glitches would affect some transistors in the chip, causing one or more flip-flops to go into an erroneous state, the processor may skip or implement the erroneous operation.

Disclosure of Invention

The invention solves the technical problem of providing an intelligent burr design circuit which can generate any burr signal, has adjustable amplitude, controllable time, high precision, stable signal and no distortion, and can adjust the frequency and the phase of the burr.

In order to solve the above technical problem, the intelligent glitch design circuit provided by the present invention comprises: core plate of FPGR, core plate of FPGR is connected with first DA conversion module, second DA conversion module, DA module, fast switch and USB and changes serial module, USB changes serial module and is connected with PC, first DA conversion module is connected with operational amplifier and ARM treater, operational amplifier is connected with the second adder, the second adder is connected with first adder, current amplifier and adjustable steady voltage LDO, first adder with the DA module all with fast switch, first adder is connected with test equipment, test equipment with current amplifier is connected, adjustable steady voltage LDO with second DA conversion module is connected, adjustable steady voltage LDO is connected with switching power supply, switching power supply is connected with DC/DC module.

Preferably, the output voltage of the switching power supply is 12V.

Preferably, the output voltage of the DC/DC module is +5V and-5V.

Preferably, the output level of the adjustable voltage regulation LDO is 0-5V.

Compared with the related art, the intelligent burr design circuit provided by the invention has the following beneficial effects:

the invention provides an intelligent burr design circuit, which generates high and low level signals through an FPGA, controls an enabling end of a fast switch, controls a voltage output signal of a DA converter, inputs the signal to an adder, superposes direct current voltage, thereby generating voltage burrs with the direct current voltage, can attack various high-speed chips, is suitable for various fields, has wide application range and high reliability, and has the advantages of stable working point, strong anti-interference capability, convenient and fast detection, high detection operation efficiency, high gain, low distortion, controllable time, high precision, controllable amplitude adjustment and wide application prospect compared with the prior art.

Drawings

FIG. 1 is a combinational logic circuit of a first prior art of an intelligent glitch design circuit provided by the present invention;

FIG. 2 is a combinational logic circuit of a second prior art of the intelligent glitch design circuit provided by the present invention;

FIG. 3 is a combinational logic circuit of an intelligent glitch design circuit according to a preferred embodiment of the present invention.

Detailed Description

The invention is further described with reference to the following figures and embodiments.

FIG. 1 is a combinational logic circuit of a first prior art of an intelligent glitch design circuit provided by the present invention; FIG. 2 is a combinational logic circuit of a second prior art of the intelligent glitch design circuit provided by the present invention; FIG. 3 is a combinational logic circuit of an intelligent glitch design circuit according to a preferred embodiment of the present invention. Intelligence burr design circuit includes: core plate of FPGR, core plate of FPGR is connected with first DA conversion module, second DA conversion module, DA module, fast switch and USB and changes serial module, USB changes serial module and is connected with PC, first DA conversion module is connected with operational amplifier and ARM treater, operational amplifier is connected with the second adder, the second adder is connected with first adder, current amplifier and adjustable steady voltage LDO, first adder with the DA module all with fast switch, first adder is connected with test equipment, test equipment with current amplifier is connected, adjustable steady voltage LDO with second DA conversion module is connected, adjustable steady voltage LDO is connected with switching power supply, switching power supply is connected with DC/DC module.

The output voltage of the switching power supply is 12V.

The output voltage of the DC/DC module is +5V and-5V.

The output level of the adjustable voltage-stabilizing LDO is 0-5V.

The working principle of the intelligent burr design circuit provided by the invention is as follows:

when a CPU is in normal operation, if the voltage of a chip is changed from VCC to 0 and maintained for a few nanoseconds, a processor skips the execution of some instructions and recovers the normal execution within a few milliseconds after a Glitch attack, and an attacker generates a voltage pulse during the reading and writing of an EEPROM so that a read key is a fixed value 00. in order to attack and obtain a key with n bytes, the attacker can generate n-1 voltage pulses during the operation of the chip so that the key read from the EEPROM is 0000 … xx 0000.. 00, encrypt a known plaintext by using the wrong key to obtain a result C, because an unknown part in the whole key has xx with one byte, the value of xx can be obtained by 256 times of brute force cracking, and the attacker can safely obtain the key with the whole n bytes by generating the Glitch at different positions.

The FPGA pulse generator and DA signal conversion is adopted, voltage burrs are generated through the pulse generator, output is achieved through DA conversion, the voltage burrs are input to the adder, and direct-current voltage is superposed, so that the voltage burrs with the direct-current voltage are generated.

The power burr attack platform adopts an ARM processor as a main control chip, and the FPGA is a narrow pulse generation unit, so that a stable burr signal can be generated on a power pin, and the requirement of a contact type intelligent card on power burr test is met.

The clock glitch attack is that when a CPU runs normally, a pulse generator of an FPGA generates a plurality of nanosecond glitches with any amplitude which are superposed to a certain period or a plurality of periods of an input clock, so that the CPU is subjected to wrong operation.

At a specific moment, a plurality of burrs are added on a normal clock signal, so that the clock frequency of the chip is higher than the highest running frequency of the chip and exceeds the processing capacity of the chip, and an unstable state occurs due to the over-frequency running of the chip, so that the chip makes mistakes.

At a specific moment, a negative burr is added on a normal reset pin to reset a partial module of the chip or initialize the internal state to cause the operation of the chip to be wrong.

At a specific moment, negative burrs are added on a normal input/output pin (high-point average) to interfere a chip input/output module, and when the chip input/output module is not well isolated from an internal logic area, a storage area and a bus, unexpected errors occur in the chip.

The method is used for injecting voltage pulses with specific width into a power supply pin at specific time in the process of executing encryption and decryption operation by a chip, so that errors occur in the encryption and decryption operation, the error ciphertext is monitored through upper computer software, an error operation result is obtained, and the correct secret key is obtained from the error ciphertext through some specific algorithms by utilizing the obtained errors.

In addition, the method is widely applied to burr attack tests in the fields of smart card chips, POS machine chips and the like.

Compared with the related art, the intelligent burr design circuit provided by the invention has the following beneficial effects:

the invention provides an intelligent burr design circuit, which generates high and low level signals through an FPGA, controls an enabling end of a fast switch, controls a voltage output signal of a DA converter, inputs the signal to an adder, superposes direct current voltage, thereby generating voltage burrs with the direct current voltage, can attack various high-speed chips, is suitable for various fields, has wide application range and high reliability, and has the advantages of stable working point, strong anti-interference capability, convenient and fast detection, high detection operation efficiency, high gain, low distortion, controllable time, high precision, controllable amplitude adjustment and wide application prospect compared with the prior art.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.