阅读说明：本技术 三维存储器结构及其制备方法 (Three-dimensional memory structure and preparation method thereof ) 是由 左明光 张坤 熊少游 周烽 宋锐 曾海 詹侃 于 2019-10-12 设计创作，主要内容包括：本发明提供一种三维存储器结构及其制备方法,制备方法包括如下步骤：提供半导体衬底,形成叠层结构,并于叠层结构中形成沟道孔,形成功能侧壁层,形成沟道层,形成栅极间隙,去除所述牺牲层形成牺牲间隙；于牺牲间隙内形成栅极层；以及于形成有栅极层的叠层结构上制备绝缘盖层,且绝缘盖层与栅极间隙形成间隙腔。通过上述方案,本发明在栅极间隙中制备间隙腔,进一步在间隙腔内壁制备包覆栅极层的漏电材料抑制层,从而可以有利于栅极漏电流的减小,并减小材料制备所带来的应力,进而减小整个器件结构的应力,采用背面刻蚀等工艺制备背面连接引出区,从背面连线实现与正面连线响应的功能。(The invention provides a three-dimensional memory structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor substrate, forming a laminated structure, forming a channel hole in the laminated structure, forming a functional side wall layer, forming a channel layer, forming a grid gap, and removing the sacrificial layer to form a sacrificial gap; forming a gate layer in the sacrificial gap; and preparing an insulating cover layer on the laminated structure with the grid layer, wherein a gap cavity is formed between the insulating cover layer and the grid gap. Through the scheme, the gap cavity is prepared in the grid gap, the leakage material inhibiting layer coating the grid layer is further prepared on the inner wall of the gap cavity, so that the reduction of grid leakage current can be facilitated, the stress caused by material preparation is reduced, the stress of the whole device structure is further reduced, the back connection leading-out region is prepared by adopting the back etching and other processes, and the function of responding to the front connection line is realized from the back connection line.)

1. A preparation method of a three-dimensional memory structure is characterized by comprising the following steps:

providing a semiconductor substrate;

forming a laminated structure on the semiconductor substrate, and forming a channel hole in the laminated structure, wherein the laminated structure comprises sacrificial layers and insulating medium layers which are alternately laminated, and the channel hole penetrates through the laminated structure;

forming a functional side wall layer on the inner wall of the channel hole, and forming a channel layer on the surface of the functional side wall layer;

forming a gate gap in the laminated structure, wherein a space is reserved between the gate gap and the channel hole;

removing the sacrificial layer based on the gate gap to form a sacrificial gap;

forming a gate layer in the sacrificial gap; and

and preparing an insulating cover layer on the laminated structure with the grid layer, wherein a clearance cavity is formed between the insulating cover layer and the grid gap.

2. The method of claim 1, further comprising the step of, after forming the gate layer in the sacrificial gap: and etching back the gate layer around the gate gap based on the gate gap to form a plurality of groove regions communicated with the gate gap at the periphery of the gate gap.

3. The method of fabricating a three-dimensional memory structure according to claim 2, further comprising, before fabricating the insulating cap layer, the steps of: and forming a leakage current inhibiting layer on the inner wall of the grid gap, wherein the leakage current inhibiting layer is also formed on the inner wall of the groove region at the same time.

4. The method of claim 3, wherein the leakage current suppression layer comprises a high-k dielectric layer.

5. The method of claim 1, wherein the insulating cap layer is prepared by a physical vapor deposition process; the material of the insulating cover layer comprises at least one of silicon oxide and silicon nitride.

6. The method of claim 1, further comprising the step of, after forming the channel hole: and forming a high-dielectric-constant dielectric layer on the inner wall of the channel hole, wherein the functional side wall layer is formed on the surface of the high-dielectric-constant dielectric layer, and the channel layer is formed on the surface of the functional side wall layer.

7. The method of fabricating a three-dimensional memory structure according to claim 6, further comprising, after forming the channel layer, the steps of: and forming a filling insulating layer in the channel hole, preparing a connecting block on the filling insulating layer, wherein the side edge of the connecting block is in contact with the channel layer, and the insulating cover layer is in contact with the upper surface of the connecting block, the upper surface of the channel layer, the upper surface of the functional side wall layer and the upper surface of the high-dielectric-constant medium layer.

8. The method of claim 1, further comprising a step of forming a bottom stack structure on the semiconductor substrate and a bottom epitaxial layer in the semiconductor substrate corresponding to the channel hole, wherein the stack structure is formed on the bottom stack structure, and the bottom epitaxial layer extends into the bottom stack structure, wherein the method further comprises a step of forming a sidewall protection layer on an outer wall of the bottom epitaxial layer based on the bottom stack structure.

9. The method of claim 1, wherein the channel hole includes N sub-channel holes that are connected to each other, the stack structure includes N sub-stack structures that are sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate, each sub-stack structure corresponds to each sub-channel hole, where N is an integer greater than or equal to 2, and the method of forming the channel hole and the stack structure includes:

forming a first sub-stack structure on the semiconductor substrate;

forming a first sub-channel hole penetrating through the first sub-stack structure in the first sub-stack structure;

filling a first hole filling sacrificial layer in the first sub-gate gap;

continuing to form a subsequent sub-laminated structure, a sub-channel hole and a hole filling sacrificial layer on the semiconductor substrate until an Nth sub-laminated structure, an Nth sub-channel hole and an N-1 th hole filling sacrificial layer are formed, so that the sub-channel hole at the top part exposes the hole filling sacrificial layer in the sub-gate gap at the lower layer; and

and removing each hole filling sacrificial layer based on the Nth sub-channel hole to obtain the channel hole and the laminated structure.

10. The method for fabricating a three-dimensional memory structure according to any one of claims 1 to 9, further comprising, after forming the insulating cap layer, the steps of: and inverting the structure with the insulating cover layer to form a connection lead-out region in the semiconductor substrate corresponding to the bottom of the gate gap.

11. The method of claim 10, wherein the step of forming the connection lead-out region comprises: forming a lead-out groove body in the semiconductor substrate corresponding to the bottom of the grid gap, preparing a contact layer on the inner wall of the lead-out groove body, and forming a conductive layer on the surface of the contact layer, wherein the conductive layer fills the lead-out groove body.

12. A three-dimensional memory structure, the three-dimensional memory structure comprising:

a semiconductor substrate; and

the stacked structure comprises gate layers and insulating medium layers which are alternately stacked, the channel holes and the gate gaps penetrate through the stacked structure, and a space is reserved between the channel holes and the gate gaps;

the functional side wall layer is formed on the inner wall of the channel hole, and the channel layer is formed on the surface of the functional side wall layer; and

and the insulating cover layer is formed on the stacked structure, and the insulating cover layer and the gate gap form a clearance cavity.

13. The three-dimensional memory structure of claim 12, further comprising a plurality of recessed regions at least between adjacent ones of the insulating dielectric layers, the recessed regions contacting the gate layer and communicating with the gate gap.

14. The three-dimensional memory structure of claim 13, further comprising a leakage current suppression layer formed on the inner wall of the gate gap and also formed on the inner wall of the recess region.

15. The three-dimensional memory structure of claim 14, wherein the leakage current suppression layer comprises a high dielectric constant dielectric layer.

16. The three-dimensional memory structure of claim 12, further comprising a high-k dielectric layer, wherein the high-k dielectric layer is formed on an inner wall of the channel hole, the functional sidewall layer is formed on a surface of the high-k dielectric layer, and the channel layer is formed on a surface of the functional sidewall layer.

17. The three-dimensional memory structure of claim 16, further comprising a filling insulating layer formed on the channel layer surface and filled in the channel hole, and a connection block on the filling insulating layer, wherein a side edge of the connection block is in contact with the channel layer, and the insulating cap layer is in contact with the connection block upper surface, the channel layer upper surface, and the functional sidewall layer upper surface.

18. The three-dimensional memory structure according to claim 12, wherein the channel hole comprises N sub-channel holes which are arranged in a vertical direction, the stacked structure comprises N sub-stacked structures which are sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate, each sub-stacked structure corresponds to each sub-channel hole one to one, and N is an integer greater than or equal to 2.

19. The three-dimensional memory structure according to any one of claims 12-18, wherein the three-dimensional memory structure comprises a connection lead-out region formed in the semiconductor substrate corresponding to the bottom of the gate gap.

20. The three-dimensional memory structure of claim 19, wherein the connection lead-out region comprises a contact layer and a conductive layer, wherein the contact layer is located on an inner wall of a lead-out groove formed in the semiconductor substrate, the conductive layer is located on the surface of the contact layer and fills the lead-out groove, and the bottom of the lead-out groove is opposite to the bottom of the gate gap.

Technical Field

The invention belongs to the field of semiconductor design and manufacture, and particularly relates to a three-dimensional memory structure and a preparation method thereof.

Background

With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to address the difficulties encountered with flat flash memories and to pursue lower production costs per unit cell, three-dimensional memory structures have arisen that can enable each memory die in a memory device to have a greater number of memory cells.

In a non-volatile memory, such as a NAND memory, one way to increase the memory density is by using a vertical memory array, i.e. a 3D NAND memory, and the existing 3D NAND flash memory is mainly prepared by the following processes: firstly, a laminated structure formed by alternately overlapping sacrificial layers and inter-gate dielectric layers is formed, then the sacrificial layers are removed and filled to form a gate layer so as to obtain the 3D NAND flash memory, and with the development of the process, in order to achieve higher storage density, the number of layers stacked in the 3D NAND flash memory also increases significantly, such as from 32 layers to 64 layers, to 96 layers or even 128 layers, etc., however, as the number of layers stacked in a 3D NAND flash memory increases, the process difficulty is increased along with the increase of the process difficulty, the depth-to-width ratio (AR) of the hole is increased, the etching difficulty is increased, the process technology difficulty of the traditional injection deposition of materials in the hole is increased, the Characteristic Dimension (CD) of a grid gap is larger, the distance between the center of a channel hole and the grid gap is reduced, and the leakage current between a Grid Layer (GL) and a source line structure (ACS, ARRAY COMMON SOURCELINE) is increased, namely the leakage current between the grid layer and a grid gap filling structure is increased.

Therefore, it is necessary to provide a three-dimensional memory structure and a method for fabricating the same to solve the above-mentioned problems in the prior art.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-dimensional memory structure and a method for fabricating the same, which are used to solve the problem of increased leakage current between the gate and the source line caused by the increased number of process layers in the prior art.

To achieve the above and other related objects, the present invention provides a method for fabricating a three-dimensional memory structure, the method comprising the steps of:

providing a semiconductor substrate;

forming a laminated structure on the semiconductor substrate, and forming a channel hole in the laminated structure, wherein the laminated structure comprises sacrificial layers and insulating medium layers which are alternately laminated, and the channel hole penetrates through the laminated structure;

forming a functional side wall layer on the inner wall of the channel hole, and forming a channel layer on the surface of the functional side wall layer;

forming a gate gap in the stacked structure, the gate gap having a distance from the channel hole,

removing the sacrificial layer based on the gate gap to form a sacrificial gap;

forming a gate layer in the sacrificial gap; and

and preparing an insulating cover layer on the laminated structure with the grid layer, wherein a clearance cavity is formed between the insulating cover layer and the grid gap.

Optionally, the forming of the gate layer in the sacrificial gap includes: and etching back the gate layer around the gate gap based on the gate gap to form a plurality of groove regions communicated with the gate gap at the periphery of the gate gap.

Optionally, before preparing the insulating cap layer, the method further comprises the steps of: and forming a leakage current inhibiting layer on the inner wall of the grid gap, wherein the leakage current inhibiting layer is also formed on the inner wall of the groove region at the same time.

Optionally, the leakage current suppression layer comprises a high dielectric constant dielectric layer.

Optionally, preparing the insulating cover layer by using a physical vapor deposition process; the material of the insulating cover layer comprises at least one of silicon oxide and silicon nitride.

Optionally, the method further includes, after forming the channel hole, the steps of: and forming a high-dielectric-constant dielectric layer on the inner wall of the channel hole, wherein the functional side wall layer is formed on the surface of the high-dielectric-constant dielectric layer, and the channel layer is formed on the surface of the functional side wall layer.

Optionally, the method further includes, after forming the channel layer: the method also comprises the following steps after the channel layer is formed: and forming a filling insulating layer in the channel hole, preparing a connecting block on the filling insulating layer, wherein the side edge of the connecting block is in contact with the channel layer, and the insulating cover layer is in contact with the upper surface of the connecting block, the upper surface of the channel layer, the upper surface of the functional side wall layer and the upper surface of the high-dielectric-constant medium layer.

Optionally, the method for manufacturing a three-dimensional memory structure further includes a step of manufacturing a bottom stacked structure on the semiconductor substrate and a step of manufacturing a bottom epitaxial layer in the semiconductor substrate corresponding to the channel hole, where the stacked structure is formed on the bottom stacked structure, and the bottom epitaxial layer extends into the bottom stacked structure, and the method for manufacturing a three-dimensional memory structure further includes a step of forming a sidewall protection layer on an outer wall of the bottom epitaxial layer based on the bottom stacked structure.

Optionally, the channel hole includes N sub-channel holes that are arranged in a vertically-communicated manner, the stacked structure includes N sub-stacked structures that are sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate, each sub-stacked structure corresponds to each sub-channel hole one to one, where N is an integer greater than or equal to 2, and the method for forming the channel hole and the stacked structure includes:

forming a first sub-stack structure on the semiconductor substrate;

forming a first sub-channel hole penetrating through the first sub-stack structure in the first sub-stack structure;

filling a first hole filling sacrificial layer in the first sub-gate gap;

forming a second sub-stack structure on the first sub-stack structure on which the first hole-filling sacrificial layer is formed, and forming a second sub-channel hole penetrating through the second sub-stack structure in the second sub-stack structure;

forming a second hole-filling sacrificial layer in the second sub-gate gap;

continuing to form a subsequent sub-stack structure, a sub-channel hole and a hole filling sacrificial layer on the semiconductor substrate until an Nth sub-stack structure, an Nth sub-channel hole and an N-1 th hole filling sacrificial layer are formed, so that the sub-channel hole at the top part exposes the hole filling sacrificial layer in the sub-gate gap at the lower layer, wherein when the gate gap comprises two sub-channel holes, the second gate gap is not filled; and

and removing each hole filling sacrificial layer based on the sub-channel hole at the top to obtain the channel hole and the laminated structure.

Optionally, the method further includes, after forming the insulating cap layer: and inverting the structure with the insulating cover layer to form a connection lead-out region in the semiconductor substrate corresponding to the bottom of the gate gap.

Optionally, the step of forming the connection lead-out region includes: and forming a lead-out groove body in the semiconductor substrate corresponding to the bottom of the grid gap, preparing a contact layer on the inner wall of the lead-out groove body, and forming a conductive layer on the surface of the contact layer, wherein the conductive layer fills the lead-out groove body.

The invention also provides a three-dimensional memory structure, which is preferably prepared by the preparation method of the three-dimensional memory structure provided by the invention, and the three-dimensional memory structure comprises the following components:

a semiconductor substrate; and

the stacked structure comprises gate layers and insulating medium layers which are alternately stacked, the channel holes and the gate gaps penetrate through the stacked structure, and a space is reserved between the channel holes and the gate gaps;

the functional side wall layer is formed on the inner wall of the channel hole, and the channel layer is formed on the surface of the functional side wall layer; and

and the insulating cover layer is formed on the stacked structure, and the insulating cover layer and the gate gap form a clearance cavity.

Optionally, the three-dimensional memory structure further includes a plurality of groove regions, the groove regions are at least located between adjacent insulating dielectric layers, and the groove regions are in contact with the gate layer and are communicated with the gate gaps.

Optionally, the three-dimensional memory structure further includes a leakage current suppression layer, the leakage current suppression layer is formed on an inner wall of the gate gap, and the leakage current suppression layer is also formed on an inner wall of the groove region.

Optionally, the leakage current suppression layer comprises a high dielectric constant dielectric layer.

Optionally, the three-dimensional memory structure further includes a high-dielectric-constant dielectric layer, wherein the high-dielectric-constant dielectric layer is formed on an inner wall of the channel hole, the functional side wall layer is formed on a surface of the high-dielectric-constant dielectric layer, and the channel layer is formed on a surface of the functional side wall layer.

Optionally, the three-dimensional memory structure further includes a filling insulating layer and a connection block, the filling insulating layer is formed on the surface of the channel layer and filled in the channel hole, the connection block is located on the filling insulating layer, a side edge of the connection block contacts with the channel layer, and the insulating cover layer contacts with the upper surface of the connection block, the upper surface of the channel layer, and the upper surface of the functional side wall layer.

Optionally, the channel hole includes N sub-channel holes that are arranged in a vertically-communicated manner, the stacked structure includes N sub-stacked structures that are sequentially stacked in a direction perpendicular to the surface of the semiconductor substrate, each sub-stacked structure corresponds to each sub-channel hole one to one, and N is an integer greater than or equal to 2.

Optionally, the three-dimensional memory structure includes a connection lead-out region formed in the semiconductor substrate corresponding to the bottom of the gate gap.

Optionally, the connection lead-out region includes a contact layer and a conductive layer, wherein the contact layer is located on an inner wall of a lead-out groove formed in the semiconductor substrate, the conductive layer is located on a surface of the contact layer and fills the lead-out groove, and a bottom of the lead-out groove is opposite to a bottom of the gate gap.

As described above, according to the three-dimensional memory structure and the manufacturing method of the three-dimensional memory structure, the gap cavity is manufactured in the gate gap, and the leakage material inhibiting layer covering the gate layer is further manufactured on the inner wall of the gap cavity, so that the reduction of gate leakage current can be facilitated, the stress caused by material manufacturing can be reduced, the stress of the whole device structure can be further reduced, the back connection lead-out region is manufactured by adopting the processes of back etching and the like, and the function corresponding to the front connection line is realized by the back connection line.

Drawings

FIG. 1 is a flow chart of a process for fabricating a three-dimensional memory structure according to the present invention.

Figure 2 shows a schematic representation of the provision of a semiconductor substrate in the fabrication of a three-dimensional memory structure of the present invention.

Fig. 3 is a schematic diagram illustrating the formation of a stacked structure in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 4 is a diagram illustrating the formation of gate gaps and channel holes in the fabrication of a three-dimensional memory structure according to the present invention.

FIG. 5 is a schematic top view of a gate gap and a channel hole formed in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 6 is a diagram illustrating the formation of a first sub-channel hole in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 7 is a schematic diagram illustrating the formation of a first hole-filling sacrificial layer in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 8 is a diagram illustrating the formation of a second sub-stack structure in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 9 is a diagram illustrating the formation of a second sub-channel hole in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 10 shows a schematic representation of the formation of a second hole-filling sacrificial layer in the fabrication of the three-dimensional memory structure of the present invention.

FIG. 11 is a schematic representation of the formation of a high-k dielectric layer, a functional sidewall layer and a channel layer in a channel hole during the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 12 shows a schematic representation of the formation of a sacrificial epitaxial layer in the fabrication of a three-dimensional memory structure of the present invention.

FIG. 13 is a schematic representation of the formation of an insulating spacer layer in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 14 shows a schematic representation of the removal of the sacrificial epitaxial layer in the fabrication of the three-dimensional memory structure of the present invention.

FIG. 15 is a schematic representation of the formation of a sidewall protection layer in the fabrication of a three-dimensional memory structure according to the present invention.

Figure 16 is a diagram illustrating the formation of a sacrificial gap in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 17 is a diagram illustrating the formation of a gate layer in the fabrication of a three-dimensional memory structure according to the present invention.

FIG. 18 is a diagram illustrating the formation of recessed regions in the fabrication of a three-dimensional memory structure according to the present invention.

FIG. 19 is a schematic representation of the formation of an insulating cap layer in the fabrication of a three-dimensional memory structure according to the present invention.

Fig. 20 is a schematic diagram illustrating the formation of a leakage current suppressing layer in the fabrication of a three-dimensional memory structure according to the present invention.

FIG. 21 is a schematic representation of the formation of connection lead-out regions in the fabrication of a three-dimensional memory structure according to the present invention. .

Description of the element reference numerals

101 semiconductor substrate

102 laminated structure

102a sub-stack structure

103 insulating dielectric layer

104 sacrificial layer

105 bottom laminate structure

105a bottom dielectric layer

105b bottom sacrificial layer

106 channel hole

106a sub-channel hole

107 gate gap

107a sub-gate gap

108 filling hole sacrificial layer

109 high dielectric constant dielectric layer

110 functional sidewall layer

111 channel layer

112 filling the insulating layer

113 insulation gap

114 sacrificial epitaxial layer

115 insulating spacer layer

116 side wall protection layer

117 bottom sacrificial gap

118 grid layer

119 stacking structure

119a sub-stacking structure

120 groove region

121 connecting block

122 insulating cover

123 clearance cavity

124 leakage current suppressing layer

125 headspace

126 connect lead-out areas

127 conductive layer

128 contact layer

129 bottom epitaxial layer

S1-S7

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.