SGT MOSFET structure and process manufacturing method thereof
阅读说明：本技术 Sgt mosfet结构及其工艺制造方法 (SGT MOSFET structure and process manufacturing method thereof ) 是由 陈桥梁 刘挺 王新 楼颖颖 杨乐 于 2019-10-22 设计创作，主要内容包括：本发明涉及一种SGT MOSFET结构及其工艺制造方法。本发明SGT MOSFET通过在栅极沟槽下方植入P柱构成,通过在Si衬底片表面生长N型外延层,然后刻蚀深沟槽,接着在深沟槽内填充BSG材料并回刻,再通过各向同性腐蚀形成栅极沟槽,接着栅极沟槽内回填HDP并回刻,最后高温退火回流使BSG材料中Boron扩散至深沟槽外围的Si材料中形成P柱。采用本发明所述方法制作的SGT MOSFET,可以在实现较小的器件尺寸的同时,灵活调节P柱的宽度和浓度,有利于实现电荷平衡,优化器件参数和性能,工艺可控性强。(The invention relates to an SGT MOSFET structure and a process manufacturing method thereof. The SGT MOSFET is formed by implanting a P column below a grid groove, an N-type epitaxial layer grows on the surface of a Si substrate, then a deep groove is etched, a BSG material is filled in the deep groove and etched back, the grid groove is formed through isotropic corrosion, HDP is filled in the grid groove and etched back, and finally high-temperature annealing and refluxing are carried out to enable Boron in the BSG material to diffuse into Si material on the periphery of the deep groove to form the P column. The SGT MOSFET manufactured by the method can flexibly adjust the width and the concentration of the P column while realizing smaller device size, is favorable for realizing charge balance, optimizes device parameters and performance, and has strong process controllability.)
An SGT MOSFET structure, characterized by:
the MOSFET structure is located on an epitaxial substrate, and a region is arranged below a gate groove of the MOSFET structure and filled with a material which is in an inverse shape with the epitaxy to realize charge balance.
2. The SGT MOSFET structure of claim 1, wherein:
the area under the gate trench of the MOSFET is a deep trench.
3. The SGT MOSFET structure of claim 2, wherein:
the deep groove below the MOSFET grid groove is filled with a doped oxide which is in an inverse type with the epitaxy.
4. The SGT MOSFET structure of claim 3, wherein:
the epitaxial material of the MOSFET is N-type, and the filler in the deep groove below the grid groove is a P-type oxide film: borosilicate glass BSG.
5. The SGT MOSFET structure of claim 4, wherein:
the MOSFET gate trench is self-aligned to the deep trench below it.
6. The SGT MOSFET structure of claim 5, wherein:
the deep trench is less deep than the thickness of the MOSFET.
A process for fabricating an SGT MOSFET structure, comprising:
the method comprises the following steps:
the method comprises the following steps: growing an N-type epitaxial layer on the surface of the Si substrate slice;
step two: carrying out a photoetching process by using a groove photoetching plate, exposing the position of the groove, and etching the exposed position into a deep groove by dry etching;
step three: filling borosilicate glass BSG in the deep trench by using a CVD (chemical vapor deposition) process;
step four: grinding and removing the redundant BSG on the Si surface by a CMP (chemical mechanical polishing) process, and corroding the BSG in the groove to be below the Si surface by wet corrosion;
step five: expanding the width of the groove by utilizing isotropic etching to form a grid groove;
step six: HDP oxide is filled in the grid groove;
step seven: diffusing Boron in the borosilicate glass BSG material into the Si material at the periphery of the deep groove by utilizing high-temperature annealing to form a P column;
step eight: HDP OX back etching in the grid groove;
the subsequent steps are the same as in a conventional MOSFET process.
8. The process manufacturing method of an SGT MOSFET structure according to claim 7, wherein:
in the second step, the depth of the groove formed by dry etching is between 5 microns and 20 microns, and the width of the groove is between 0.2 microns and 2 microns.
9. The process manufacturing method of an SGT MOSFET structure according to claim 8, wherein:
in the fourth step, the BSG is wet etched to a depth of between 1 micron and 1.5 microns below the Si surface.
10. The process manufacturing method of an SGT MOSFET structure according to claim 9, wherein:
in the seventh step, the temperature of BSG high-temperature annealing is between 800 and 1000 ℃, only nitrogen is introduced in the annealing process, or mixed gas of nitrogen and oxygen is introduced in proportion, and the proportion of the introduced nitrogen to the introduced oxygen is 10: 1 to 20: 1.
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to an SGT MOSFET structure and a process manufacturing method thereof.
Background
The SGT (Split-Gate-Trench) structure introduces horizontal depletion on the basis of the vertical depletion (P-Body/N-Epi junction) of the traditional Trench MOSFET due to the charge coupling effect, and changes the electric field of a device from triangular distribution to approximately rectangular distribution. Under the condition of adopting the epitaxial specification with the same doping concentration, the device can obtain higher breakdown voltage, and the structure is widely applied to the field of medium and low voltage power devices.
Fig. 1 shows a conventional SGT (Split-Gate-Trench) structure, in which a Trench is formed by etching, and then a shielding electrode dielectric layer, typically a thick oxide layer, is grown in the Trench to achieve charge balance. The source-drain breakdown voltage of the SGT with the structure is controlled by the thickness of the oxide layer, the higher the breakdown voltage is, the thicker the oxide layer needs to be, and the thickness of the oxide layer reaches about 6000A for a 100V device. Therefore, the trench CD needs to be defined to be relatively wide in device design (the trench CD needs to be 1um or more for a 100V device). However, a mainstream direction of current SGT device design is to obtain a lower Rsp (on-resistance per unit area), and the size of a unit cell needs to be reduced as much as possible, and the traditional SGT structural features obviously hinder its development.
Disclosure of Invention
The invention aims to provide an SGT MOSFET structure and a process manufacturing method thereof, wherein BSG (borosilicate glass) material is filled in a groove through a CVD (chemical vapor deposition) process, and then Boron is automatically diffused into the silicon material on the periphery of the groove through annealing to form a P column, so that the width and the concentration of the P column can be effectively adjusted by changing the concentration of BSG and the annealing temperature, and the charge balance with an N-type epitaxial layer is realized.
The technical scheme adopted by the invention is as follows:
SGT MOSFET structure characterized by:
the MOSFET structure is located on an epitaxial substrate, and a region is arranged below a gate groove of the MOSFET structure and filled with a material which is in an inverse shape with the epitaxy to realize charge balance.
The area under the gate trench of the MOSFET is a deep trench.
The deep groove below the MOSFET grid groove is filled with a doped oxide which is in an inverse type with the epitaxy.
The epitaxial material of the MOSFET is N-type, and the filler in the deep groove below the grid groove is a P-type oxide film: borosilicate glass BSG.
The MOSFET gate trench is self-aligned to the deep trench below it.
The deep trench is less deep than the thickness of the MOSFET.
The technical manufacturing method of the SGT MOSFET structure is characterized by comprising the following steps:
the method comprises the following steps:
the method comprises the following steps: growing an N-type epitaxial layer on the surface of the Si substrate slice;
step two: carrying out a photoetching process by using a groove photoetching plate, exposing the position of the groove, and etching the exposed position into a deep groove by dry etching;
step three: filling borosilicate glass BSG in the deep trench by using a CVD (chemical vapor deposition) process;
step four: grinding and removing the redundant BSG on the Si surface by a CMP (chemical mechanical polishing) process, and corroding the BSG in the groove to be below the Si surface by wet corrosion;
step five: expanding the width of the groove by utilizing isotropic etching to form a grid groove;
step six: HDP oxide is filled in the grid groove;
step seven: diffusing Boron in the borosilicate glass BSG material into the Si material at the periphery of the deep groove by utilizing high-temperature annealing to form a P column;
step eight: HDP OX back etching in the grid groove;
the subsequent steps are the same as in a conventional MOSFET process.
In the second step, the depth of the groove formed by dry etching is between 5 microns and 20 microns, and the width of the groove is between 0.2 microns and 2 microns.
In the fourth step, the BSG is wet etched to a depth of between 1 micron and 1.5 microns below the Si surface.
In the seventh step, the temperature of BSG high-temperature annealing is between 800 and 1000 ℃, only nitrogen is introduced in the annealing process, or mixed gas of nitrogen and oxygen is introduced in proportion, and the proportion of the introduced nitrogen to the introduced oxygen is 10: 1 to 20: 1.
The invention has the following advantages:
by adopting the SGT MOSFET structure and the process manufacturing method, a thick shielding electrode dielectric layer does not need to be grown in the groove, and meanwhile, the BSG has good high-temperature reflux characteristic and good groove filling capacity, and can greatly reduce the CD of the groove, so that the unit cell size can be reduced, the same breakdown voltage can be realized by adopting an epitaxial wafer with higher doping concentration, the Rsp of a device is reduced, and the market competitiveness is enhanced.
Meanwhile, the manufacturing method of the invention considers the characteristic that the BSG is easy to diffuse, the BSG filled at the lower part of the deep groove is completely sealed in the groove by using the thick oxide, and then the high-temperature annealing is carried out, thus completely avoiding the contamination of the channel and the gate oxidation possibly caused by the BSG diffusion and realizing the complete compatibility with the conventional integrated circuit manufacturing process.
Drawings
FIG. 1 is a schematic diagram of a conventional SGT structure;
FIG. 2 is a schematic diagram of a first step of the present invention;
FIG. 3 is a schematic view of step two of the present invention;
FIG. 4 is a schematic view of step three of the present invention;
FIG. 5 is a schematic view of step four of the present invention;
FIG. 6 is a schematic view of step five of the present invention;
FIG. 7 is a schematic representation of step six of the present invention;
FIG. 8 is a schematic view of step seven of the present invention;
FIG. 9 is a schematic view of step eight of the present invention;
FIG. 10 is a diagram illustrating a ninth step of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific embodiments.
The invention relates to an SGT structure MOSFET and a process manufacturing method thereof, wherein the method is realized by the following steps:
the method comprises the following steps: growing an N-type
The source-drain withstand voltage is set to range from 5 microns to 20 microns as shown in fig. 2.
Step two: and taking an ONO (silicon oxide 3-silicon nitride 4-silicon oxide 5) film as a hard mask, carrying out a photoetching process by utilizing a groove photoetching plate, exposing the position needing to be grooved, having no photoresist mask, and masking the rest part by using photoresist. Then, the
Step three: and filling the
Step four: the excess BSG on the Si surface is removed by a CMP process, and the BSG in the trench is etched to 1-1.5 microns below the Si surface by wet etching, as shown in FIG. 5.
Step five: the trench width is expanded by isotropic etching to form the
Step six: the gate trench is backfilled with
Step seven: and (3) utilizing a furnace tube to perform high-temperature annealing reflux so that the Boron in the BSG material is diffused into the Si material at the periphery of the deep groove to form the
Step eight: the HDP oxide in the gate trench is etched back until the distance between the HDP oxide and the top of the BSG is about 2000-5000A, which is used as an isolation layer between the BSG and the gate POLY, as shown in FIG. 9.
Step nine: the final metal level of the gate oxide layer is the same as that of the conventional MOSFET process, and the final device structure is shown in fig. 10 after completion.
The SGT MOSFET structure obtained by the method is located on the epitaxial substrate, an area is arranged below the gate trench, and the area is filled with a material which is inverted to the epitaxial structure to realize charge balance. The area under the gate trench of the MOSFET is a deep trench. The deep groove below the MOSFET grid groove is filled with a doped oxide which is in an inverse type with the epitaxy. The epitaxial material of the MOSFET is N-type, and the filler in the deep groove below the grid groove is a P-type oxide film: borosilicate glass BSG. The MOSFET gate trench is self-aligned to the deep trench below it. The depth of the deep trench is smaller than the thickness of the extension of the MOSFET.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
The SGT MOSFET is characterized in that BSG materials are filled in a groove, and then a furnace tube is used for annealing at high temperature, so that Boron is diffused to the periphery of the groove to form a P column, and charge balance with N-type epitaxy is realized, and a charge coupling effect of a thick oxide layer is not realized. The SGT MOSFET manufactured by the manufacturing method can flexibly adjust the width and the concentration of the P column while realizing smaller device size, is favorable for optimizing device parameters and performance, and has strong process controllability. In addition, the manufacturing method of the invention considers the characteristic that the BSG is easy to diffuse, the BSG filled at the lower part of the deep groove is completely sealed in the groove by the thick oxide, and then high-temperature annealing is carried out, thus completely avoiding the contamination of the channel and gate oxidation possibly caused by the BSG diffusion and realizing the complete compatibility with the conventional integrated circuit manufacturing process.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.
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