阅读说明：本技术 薄膜晶体管、像素驱动电路和显示面板 (Thin film transistor, pixel driving circuit and display panel ) 是由 袁宾 冯兵明 周琦 顾维杰 马应海 于 2019-11-11 设计创作，主要内容包括：本发明公开了一种薄膜晶体管、像素驱动电路和显示面板,薄膜晶体管包括衬底；位于衬底上的栅极层、有源层以及位于栅极层和有源层之间的栅极绝缘层；栅极绝缘层包括高介电膜层,栅极绝缘层还包括位于高介电膜层与栅极层之间的第一钝化层和/或位于高介电膜层与有源层之间的第二钝化层。通过本发明的技术方案,有利于增加薄膜晶体管的面积电容以及载流子迁移率,减小薄膜晶体管的尺寸以及栅极绝缘层的厚度,同时有利于减小薄膜晶体管的漏电流,提高薄膜晶体管的偏压稳定性,降低薄膜晶体管的磁滞效应。(The invention discloses a thin film transistor, a pixel driving circuit and a display panel, wherein the thin film transistor comprises a substrate; a gate electrode layer, an active layer, and a gate insulating layer between the gate electrode layer and the active layer on the substrate; the gate insulating layer comprises a high dielectric film layer, and further comprises a first passivation layer located between the high dielectric film layer and the gate electrode layer and/or a second passivation layer located between the high dielectric film layer and the active layer. The technical scheme of the invention is beneficial to increasing the area capacitance and the carrier mobility of the thin film transistor, reducing the size of the thin film transistor and the thickness of the grid insulating layer, simultaneously being beneficial to reducing the leakage current of the thin film transistor, improving the bias stability of the thin film transistor and reducing the hysteresis effect of the thin film transistor.)

1. A thin film transistor, comprising:

a substrate;

a gate electrode layer, an active layer and a gate insulating layer between the gate electrode layer and the active layer on the substrate;

the gate insulating layer comprises a high dielectric film layer, and further comprises a first passivation layer located between the high dielectric film layer and the gate electrode layer and/or a second passivation layer located between the high dielectric film layer and the active layer.

2. The thin film transistor according to claim 1, wherein the gate layer is located on a side of the substrate away from the active layer or the active layer is located on a side of the gate layer away from the substrate.

3. The thin film transistor of claim 1, wherein the gate insulating layer further comprises a first passivation layer between the high dielectric film layer and the gate layer, the first passivation layer having a thickness of 100 angstroms or more and 150 angstroms or less.

4. The thin film transistor of claim 1, wherein the gate insulating layer further comprises a second passivation layer between the high dielectric film layer and the active layer, the second passivation layer having a thickness of 100 angstroms or more and 150 angstroms or less.

5. The thin film transistor of claim 1, wherein the high dielectric film layer has a thickness of 1000 angstroms or more and 1200 angstroms or less.

6. The thin film transistor of claim 1, wherein the material forming the high dielectric film layer comprises at least one of hafnium oxide, zirconium oxide, tantalum oxide, and aluminum oxide.

7. The thin film transistor of claim 1, wherein the high dielectric film layer is formed using an atomic deposition process.

8. A pixel driving circuit, comprising:

a driving module for supplying a driving current to an organic light emitting element, the organic light emitting element emitting light in response to the driving current;

the data writing module is used for writing a data signal into the control end of the driving module in a data writing stage;

the storage module is used for maintaining the voltage of the control end of the driving module;

the driving module includes the thin film transistor according to any one of claims 1 to 7.

9. The pixel driving circuit according to claim 8, further comprising:

and the setting module is electrically connected with the control end of the driving module and comprises the thin film transistor.

10. A display panel, comprising:

a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction; wherein the first direction intersects the second direction;

a plurality of pixel units each including the pixel driving circuit according to claim 8 or 9 and an organic light emitting element electrically connected to the corresponding pixel driving circuit are formed in a space where the scanning line and the data line intersect.

Technical Field

The embodiment of the invention relates to the technical field of display, in particular to a thin film transistor, a pixel driving circuit and a display panel.

Background

Organic Light Emitting Displays (OLEDs) are receiving much attention due to their advantages of self-emission, fast response, thin and light weight, low power consumption, and flexible display, and the OLED technology is gradually applied to various electronic products, wherein Active Matrix Organic Light Emitting Displays (AMOLEDs) are the main trend of OLED development due to their advantages of high image quality, short response time of moving images, low power consumption, wide viewing angle, ultra-light and ultra-thin profile.

The organic light emitting display is provided with pixel driving circuits corresponding to different pixels, each pixel driving circuit comprises a plurality of thin film transistors, and a gate insulating layer of each thin film transistor has a plurality of defects, so that the leakage current of the gate insulating layer is too large, the off-state current of each thin film transistor is increased, and the display panel has display chromatic aberration to cause abnormal display.

Disclosure of Invention

In view of the above, the present invention provides a thin film transistor, a pixel driving circuit and a display panel, which are beneficial to increasing the area capacitance and the carrier mobility of the thin film transistor, reducing the size of the thin film transistor and the thickness of a gate insulating layer, and simultaneously beneficial to reducing the leakage current of the thin film transistor, improving the bias stability of the thin film transistor, and reducing the hysteresis effect of the thin film transistor.

In a first aspect, an embodiment of the present invention provides a thin film transistor, including: a substrate; a gate electrode layer, an active layer and a gate insulating layer between the gate electrode layer and the active layer on the substrate; the gate insulating layer comprises a high dielectric film layer, and further comprises a first passivation layer located between the high dielectric film layer and the gate electrode layer and/or a second passivation layer located between the high dielectric film layer and the active layer.

Further, the gate layer is located on a side of the substrate away from the active layer or the active layer is located on a side of the gate layer away from the substrate.

Further, the gate insulating layer further comprises a first passivation layer located between the high dielectric film layer and the gate layer, and the thickness of the first passivation layer is greater than or equal to 100 angstroms and less than or equal to 150 angstroms.

Further, the gate insulating layer further comprises a second passivation layer located between the high dielectric film layer and the active layer, and the thickness of the second passivation layer is greater than or equal to 100 angstroms and less than or equal to 150 angstroms.

Furthermore, the thickness of the high dielectric film layer is greater than or equal to 1000 angstroms and less than or equal to 1200 angstroms.

Further, the material of the high dielectric film layer comprises at least one of hafnium oxide, zirconium oxide, tantalum oxide and aluminum oxide.

Further, the high dielectric film layer is formed by adopting an atomic deposition process.

In a second aspect, an embodiment of the present invention further provides a pixel driving circuit, including: a driving module for supplying a driving current to an organic light emitting element, the organic light emitting element emitting light in response to the driving current; the data writing module is used for writing a data signal into the control end of the driving module in a data writing stage; the storage module is used for maintaining the voltage of the control end of the driving module; the driving module comprises a thin film transistor as described in the first aspect.

Further, the pixel driving circuit further includes:

and the setting module is electrically connected with the control end of the driving module and comprises the thin film transistor.

In a third aspect, an embodiment of the present invention further provides a display panel, including: a plurality of scan lines extending in a first direction and a plurality of data lines extending in a second direction; wherein the first direction intersects the second direction; a plurality of pixel units are formed in a space formed by the intersection of the scanning lines and the data lines, and each pixel unit comprises the pixel driving circuit and an organic light-emitting element electrically connected with the corresponding pixel driving circuit.

The embodiment of the invention provides a thin film transistor, a pixel driving circuit and a display panel, wherein the thin film transistor comprises a substrate, a grid layer, an active layer and a grid insulating layer, the grid insulating layer is positioned between the grid layer and the active layer, the grid insulating layer comprises a high dielectric film layer, the grid insulating layer further comprises a first passivation layer positioned between the high dielectric film layer and the grid layer and/or a second passivation layer positioned between the high dielectric film layer and the active layer, the area capacitance and the carrier mobility of the thin film transistor are increased, the size of the thin film transistor and the thickness of the grid insulating layer are reduced, meanwhile, the leakage current of the thin film transistor is reduced, the bias voltage stability of the thin film transistor is improved, and the hysteresis effect of the thin film transistor is reduced.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of another thin film transistor according to an embodiment of the present invention;

fig. 3 is a schematic cross-sectional view of another thin film transistor according to an embodiment of the present invention;

fig. 4 is a schematic cross-sectional structure diagram of another thin film transistor according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the invention;

FIG. 6 is a driving timing diagram of the pixel driving circuit shown in FIG. 5;

fig. 7 is a schematic top view of a display panel according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures. Throughout this specification, the same or similar reference numbers refer to the same or similar structures, elements, or processes. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

As background art, a pixel driving circuit is disposed corresponding to different pixels in an organic light emitting display, the pixel driving circuit includes a plurality of thin film transistors, a gate insulating layer of the thin film transistors has a plurality of defects, a portion of the defects exists in a free charge form, the free charges are redistributed and form a certain current under the action of an external electric field, and the defects also cause a reduction in a barrier between a metal layer and the gate insulating layer, and a carrier can pass through the barrier under the action of heat energy, resulting in an excessive leakage current of the gate insulating layer, which further causes an increase in off-state current of the thin film transistors, and a display panel has a display color difference, which causes abnormal display.

In view of this, the thin film transistor provided in the embodiment of the invention includes a substrate, a gate layer located on the substrate, an active layer, and a gate insulating layer located between the gate layer and the active layer, where the gate insulating layer includes a high dielectric film layer, and the high dielectric film layer is used to improve the dielectric performance of the thin film transistor, and in a case where the thickness of the gate insulating layer is constant, the thin film transistor is beneficial to increasing the area capacitance, reducing the size of the thin film transistor, and improving the carrier mobility of the thin film transistor, and in a case where the area capacitance of the thin film transistor is constant, the thin film transistor is beneficial to reducing the thickness of the gate insulating layer, and. In addition, the grid insulating layer further comprises a first passivation layer located between the high dielectric film layer and the grid layer and/or a second passivation layer located between the high dielectric film layer and the active layer, the surface, facing the grid layer, of the high dielectric film layer can be passivated by the aid of the first passivation layer, potential barriers between the grid insulating layer and the grid layer are increased, accordingly, leakage currents of the thin film transistor are reduced, the surface, facing the active layer, of the high dielectric film layer is passivated by the aid of the second passivation layer, defect states between the interface of the grid insulating layer and the active layer are reduced, bias voltage stability of the thin film transistor is improved, and hysteresis effects of the thin film transistor are reduced.

Fig. 1 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention. As shown in fig. 1, the thin film transistor includes a substrate 1, a gate electrode layer 2 on the substrate 1, an active layer 3, and a gate insulating layer 4 between the gate electrode layer 2 and the active layer 3, wherein the gate insulating layer 4 includes a high dielectric film layer 5, and the gate insulating layer 4 further includes a first passivation layer 6 between the high dielectric film layer 5 and the gate electrode layer 2.

The material constituting the gate insulating layer of the thin film transistor is generally SiO₂，SiO₂The material is generally formed by adopting a Chemical Vapor Deposition (CVD) manufacturing process, but the CVD process is easy to form a non-stoichiometric ratio in the film forming process, so that SiO is caused₂Defects in a gate insulating layer made of the material are increased, a part of the defects exist in the form of free charges, the free charges are redistributed to form a certain current under the action of an external electric field, the contact potential barrier between a metal layer in the thin film transistor and the gate insulating layer is reduced due to the defects, and carriers can pass through the potential barrier under the action of heat energy, so that the thin film transistor has large leakage current.

As shown in fig. 1, the gate insulating layer 4 of the thin film transistor according to the embodiment of the present invention includes the high dielectric film layer 5, for example, the material constituting the high dielectric film layer 5 may include, but is not limited to, at least one of hafnium oxide, zirconium oxide, tantalum oxide, and aluminum oxide, the high dielectric film layer 5 is used to improve the dielectric performance of the thin film transistor, and in the case that the thickness of the gate insulating layer 4 is constant, the area capacitance of the thin film transistor is increased, the carrier mobility of the thin film transistor is increased, the performance of the thin film transistor is optimized, and the increase of the area capacitance of the thin film transistor is beneficial to reducing the size of the thin film transistor, thereby being beneficial to improving the aperture ratio of the. In addition, under the condition that the area capacitance of the thin film transistor is constant, the high dielectric film layer 5 with high dielectric property is beneficial to thinning the thickness of the gate insulating layer 4, and further beneficial to thinning the display panel.

In addition, if only a single high-k film layer 5 is used to form the gate insulating layer 4, the material of the high-k film layer 5 has relatively high defects and is easily crystallized, and the direct contact between the high-k film layer 5 and the gate electrode layer 2 reduces the contact barrier between the gate insulating layer 4 and the gate electrode layer 2, resulting in a large leakage current of the thin film transistor.

As shown in fig. 1, the gate insulating layer 4 according to the embodiment of the present invention includes a first passivation layer 6 between the high dielectric film layer 5 and the gate layer 2, and the material constituting the first passivation layer 6 may include, but is not limited to, SiO, for example₂Therefore, the area capacitance of the thin film transistor is increased by the high dielectric film layer 5, the carrier mobility of the thin film transistor is improved, the size of the thin film transistor is reduced, the thickness of the gate insulating layer 4 is reduced, meanwhile, the surface of the high dielectric film layer 5 facing the gate layer 2 is passivated by the first passivation layer 6, a potential barrier between the gate insulating layer 4 and the gate layer 2 is increased, and then the leakage current of the thin film transistor is reduced.

Fig. 2 is a schematic cross-sectional structure diagram of another thin film transistor according to an embodiment of the present invention, which is different from the thin film transistor with the structure shown in fig. 1 in that the thin film transistor with the structure shown in fig. 2 is exemplarily configured such that the gate insulating layer 4 only includes the second passivation layer 7 located between the high dielectric film layer 5 and the active layer 3.

Similarly, if the gate insulating layer 4 is formed by only a single high dielectric film layer 5, the material of the high dielectric film layer 5 with a high dielectric constant has a relatively high defect ratio and is easy to crystallize, and the direct contact between the high dielectric film layer 5 and the active layer 3 increases the defect state between the interface of the gate insulating layer 4 and the active layer 3, and generates charge traps between the interface of the gate insulating layer 4 and the active layer 3, and when the thin film transistor is in a bias state, the charge traps trap charges, thereby causing the threshold voltage of the thin film transistor to shift, and increasing the hysteresis effect of the thin film transistor.

As shown in fig. 2, the gate insulating layer 4 according to the embodiment of the present invention includes a second passivation layer 7 between the high dielectric film layer 5 and the active layer 3, and the material of the first passivation layer 6 may include, but is not limited to, SiO, for example₂This isIn the same time, the second passivation layer 7 is used for passivating the surface of the high dielectric film layer 5 facing the active layer 3, so that the defect state between the interface of the gate insulating layer 4 and the interface of the active layer 3 is reduced, the bias voltage stability of the thin film transistor is further improved, and the hysteresis effect of the thin film transistor is reduced.

Fig. 3 is a schematic cross-sectional view of another thin film transistor according to an embodiment of the present invention, which is different from the thin film transistor having the structure shown in fig. 1 and 2, in that the gate insulating layer 4 in the thin film transistor having the structure shown in fig. 3 includes both the first passivation layer 6 located between the high dielectric film layer 5 and the gate electrode layer 2 and the second passivation layer 7 located between the high dielectric film layer 5 and the active layer 3, and referring to the above description, in the thin film transistor having the structure shown in fig. 3, while the high dielectric film layer 5 is used to increase the area capacitance of the thin film transistor, improve the carrier mobility of the thin film transistor, reduce the size of the thin film transistor, and reduce the thickness of the gate insulating layer 4, the first passivation layer 6 is used to passivate the surface of the high dielectric film layer 5 facing the gate electrode layer 2, increase the potential barrier between the gate insulating layer 4 and the gate electrode, the surface of the high dielectric film layer 5 facing the active layer 3 is passivated by the second passivation layer 7, so that the defect state between the gate insulating layer 4 and the interface of the active layer 3 is reduced, the bias stability of the thin film transistor is further improved, and the hysteresis effect of the thin film transistor is reduced.

Referring to fig. 1 to 3, a gate layer 2 of the thin film transistor is located on a side of a substrate 1 away from an active layer 3, that is, the thin film transistor is a top-gate thin film transistor, and fig. 4 is a schematic cross-sectional view of another thin film transistor according to an embodiment of the present invention, different from the thin film transistor with the structure shown in fig. 1 to 3, the active layer 3 of the thin film transistor with the structure shown in fig. 4 is located on a side of the gate layer 2 away from the substrate 1, that is, the thin film transistor may also be a bottom-gate thin film transistor.

Similarly, the gate insulating layer 4 in the thin film transistor with the bottom gate structure may include both the first passivation layer 6 between the high dielectric film layer 5 and the gate electrode layer 2 and the second passivation layer 7 between the high dielectric film layer 5 and the active layer 3 as shown in fig. 4, or the gate insulating layer 4 in the thin film transistor with the bottom gate structure may include only the first passivation layer 6 between the high dielectric film layer 5 and the gate electrode layer 2, or the gate insulating layer 4 in the thin film transistor with the bottom gate structure may include only the second passivation layer 7 between the high dielectric film layer 5 and the active layer 3, which also can passivate the surface of the high dielectric film layer 5 facing the gate electrode layer 2 with the first passivation layer 6 while increasing the area capacitance of the thin film transistor with the high dielectric film layer 5, increasing the carrier mobility of the thin film transistor, reducing the size of the thin film transistor, and reducing the thickness of the gate insulating layer 4, and the potential barrier between the gate insulating layer 4 and the gate electrode layer 2 is increased, so that the leakage current of the thin film transistor is reduced, the surface of the high dielectric film layer 5 facing the active layer 3 is passivated by using the second passivation layer 7, the defect state between the interface of the gate insulating layer 4 and the active layer 3 is reduced, the bias voltage stability of the thin film transistor is improved, and the hysteresis effect of the thin film transistor is reduced.

Alternatively, in conjunction with fig. 1, 3, and 4, the thickness of the first passivation layer 6 may be set to 100 angstroms or more and 150 angstroms or less. Specifically, an excessively large thickness of the first passivation layer 6 may cause a decrease in area capacitance of the thin film transistor, and further cause a decrease in mobility of the thin film transistor, and an excessively small thickness of the first passivation layer 6 may cause the first passivation layer 6 not to completely passivate defects in the high dielectric film layer 5 to reduce leakage current of the thin film transistor, and an excessively small thickness of the first passivation layer 6 may also cause an excessively low contact barrier between the first passivation layer 6 and the gate layer 2, and a carrier may easily overcome the barrier to cause leakage current of the thin film transistor. Therefore, the thickness of the first passivation layer 6 is set to be greater than or equal to 100 angstroms and less than or equal to 150 angstroms, which is beneficial to improving the area capacitance of the thin film transistor, further improving the mobility of the thin film transistor, and simultaneously being beneficial to reducing the off-state leakage current of the thin film transistor.

Alternatively, in conjunction with fig. 2, 3, and 4, the thickness of the second passivation layer 7 may be set to 100 angstroms or more and 150 angstroms or less. Specifically, the area capacitance of the thin film transistor is reduced due to the excessively large thickness of the second passivation layer 7, and then the mobility of the thin film transistor is reduced, and a certain number of carriers cannot be induced at the interface between the gate insulating layer 4 and the active layer 3 due to the excessively large thickness of the second passivation layer 7, so that the thin film transistor cannot achieve a turn-on function at all. And too small thickness of the second passivation layer 7 will result in that the second passivation layer 7 cannot completely passivate defects in the high dielectric film layer 5, which is not beneficial to reducing defect states between the gate insulating layer 4 and the active layer 3 interface, and weakening the effect of the second passivation layer 7 in improving the bias stability of the thin film transistor and reducing the hysteresis effect of the thin film transistor. Therefore, the thickness of the second passivation layer 7 is set to be greater than or equal to 100 angstroms and less than or equal to 150 angstroms, which is beneficial to improving the area capacitance of the thin film transistor, thereby improving the mobility of the thin film transistor, ensuring that the thin film transistor can be accurately turned on under the action of the gate voltage, optimizing the bias stability of the thin film transistor and reducing the hysteresis effect of the thin film transistor.

Alternatively, in conjunction with fig. 1 to 4, the thickness of the high dielectric film layer 5 may be set to be greater than or equal to 1000 angstroms and less than or equal to 1200 angstroms. Specifically, the thin film transistor may not be normally turned on due to the excessively large thickness of the high dielectric film layer 5, and the thin film transistor may be broken down due to the excessively small thickness of the high dielectric film layer 5, thereby increasing the leakage current of the thin film transistor. Therefore, the thickness of the high dielectric film layer 5 is set to be greater than or equal to 1000 angstroms and less than or equal to 1200 angstroms, so that the off-state leakage current of the thin film transistor is reduced while the thin film transistor can be accurately started under the action of the gate voltage.

Optionally, the high dielectric film layer 5 may be formed by an atomic deposition process, and the atomic deposition process may precisely control the film formation thickness and the step coverage and selection due to the chemical vapor deposition process, and is a one-layer film formation generation process, and each period has self-restraint, and the high dielectric film layer 5 is formed by the atomic deposition process, which is beneficial to optimizing the film formation process of the high dielectric film layer 5, and further optimizing the performance of the thin film transistor, and the high dielectric film layer 5 including but not limited to at least one of hafnium oxide, zirconium oxide, tantalum oxide, and aluminum oxide may be formed by the atomic deposition process.

The embodiment of the invention also provides a pixel driving circuit, and fig. 5 is a schematic structural diagram of the pixel driving circuit provided by the embodiment of the invention. As shown in fig. 5, the pixel driving circuit 15 includes a driving module 8, a data writing module 9 and a storage module 10, the driving module 8 is configured to provide a driving current to the organic light emitting device 16, the organic light emitting device 16 emits light corresponding to the driving current, the data writing module 9 is configured to write a data signal into a control terminal of the driving module 8 in a data writing phase, the storage module 10 is configured to maintain a voltage of the control terminal of the driving module 8, and the driving module 8 includes the thin film transistor according to the above embodiment, so that the beneficial effects of the above embodiment are achieved, and details thereof are omitted.

Specifically, the data writing module 9 writes the data signal corresponding to the display gray scale into the control terminal of the driving module 8 in the data writing stage, the storage module 10 maintains the voltage at the control terminal of the driving module 8, the driving module 8 provides the driving current to the organic light emitting device 16 in the light emitting stage according to the voltage at the control terminal of the driving module 8, the organic light emitting device 16 emits light in response to the driving current, the driving module 8 is configured to include the thin film transistor according to the above embodiment, the high dielectric film layer 5 in the thin film transistor is beneficial to increasing the area capacitance of the thin film transistor and improving the carrier mobility of the thin film transistor, thereby being beneficial to improving the switching response speed of the driving module 8, and the increase of the area capacitance of the thin film transistor is beneficial to reducing the size of the thin film transistor, further, the area of the pixel driving circuit 15 is reduced, which is beneficial to improving the aperture ratio of the display panel. In addition, the arrangement of the first passivation layer 6 and the second passivation layer 7 reduces leakage current of the thin film transistor, i.e., the driving transistor, which is beneficial to improving the light leakage problem of the organic light emitting element 16 in the non-light emitting stage, and the arrangement of the first passivation layer 6 and the second passivation layer 7 also optimizes bias stability and hysteresis effect of the thin film transistor, i.e., the driving transistor, thereby optimizing the stability of the operation of the pixel driving circuit 15.

Optionally, as shown in fig. 5, the pixel driving circuit 15 further includes a setting module, the setting module is electrically connected to the control terminal of the driving module 8, and the setting module includes the thin film transistor of the above embodiment. Specifically, the setting module may include a threshold compensation module 111, the driving module 8 includes a transistor, the threshold compensation module 111 writes an electrical signal including threshold voltage information of the driving transistor into the control terminal of the driving module 8 in a data writing stage to implement threshold compensation on the driving transistor, and the threshold compensation module 111 includes the thin film transistor according to the above embodiment, so that the potential stability of the control terminal of the driving module 8 can be improved by using a characteristic that a leakage current of the thin film transistor is small, and further, the working stability of the pixel driving circuit 15 is improved. In addition, the setting module may also include the initializing module 112, the initializing module 112 is configured to write the setting potential signal into the control terminal of the driving module 8 in the initialization stage, and the setting initializing module 112 includes the thin film transistor described in the above embodiment, and similarly, the stability of the potential at the control terminal of the driving module 8 can be improved by using the characteristic that the leakage current of the thin film transistor is small, so as to improve the stability of the operation of the pixel driving circuit 15.

Fig. 6 is a driving timing diagram of the pixel driving circuit shown in fig. 5, the structure shown in fig. 5 is a conventional 7T1C pixel driving circuit 15, that is, the pixel driving circuit 15 includes seven thin film transistors and a capacitor, fig. 6 is also a driving timing diagram of a conventional 7T1C pixel driving circuit, a stage T1 is an initialization stage, a stage T2 is a data writing stage, a stage T3 is a light emitting stage, and specific working processes of the 7T1C pixel driving circuit are well known by those skilled in the art and will not be described herein again.

Fig. 7 is a schematic top view structure diagram of the display panel according to the embodiment of the present invention, as shown in fig. 7, the display panel includes a plurality of scan lines 12 extending along a first direction XX 'and a plurality of data lines 13 extending along a second direction YY', and the first direction XX 'intersects the second direction YY'. A plurality of pixel units 14 are formed in a space formed by intersecting the scan lines 12 and the data lines 13, each pixel unit 14 includes a pixel driving circuit 15 and an organic light emitting element 16 electrically connected to the corresponding pixel driving circuit 15 as described in the above embodiment, the pixel circuit 15 can communicate with the data signal line 13 electrically connected to the corresponding pixel circuit under the action of a scan signal input by the scan signal line 12 electrically connected to the pixel circuit 15, and the data signal line 13 transmits a data signal to the corresponding pixel circuit 15, so as to implement a display function. Illustratively, the display panel may include, but is not limited to, an electronic display device such as a mobile phone, a computer, or a television.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.