阅读说明：本技术 控制器及其操作方法 (Controller and operation method thereof ) 是由 朴炳奎 赵荣翼 池承九 于 2019-07-03 设计创作，主要内容包括：控制器及其操作方法。一种控制器可以包括：存储器,其被配置用于存储映射数据和非映射数据；计数器,其被配置用于对存储在所述存储器中的所述非映射数据的数目进行计数；设置器,其被配置用于在所述非映射数据的数目等于或大于预定阈值时对所述非映射数据中的每一个设置偏移值；以及压缩器,其被配置用于基于所述偏移值将所述非映射数据压缩为具有预定压缩长度。(A controller and a method of operating the same. A controller may include: a memory configured to store mapped data and unmapped data; a counter configured to count a number of the unmapped data stored in the memory; a setter configured to set an offset value for each of the non-mapped data when the number of the non-mapped data is equal to or greater than a predetermined threshold; and a compressor configured to compress the unmapped data to have a predetermined compression length based on the offset value.)

1. A controller, the controller comprising:

a memory configured to store mapped data and unmapped data;

a counter configured to count a number of the unmapped data stored in the memory;

a setter configured to set an offset value for each of the non-mapped data when the number of the non-mapped data is equal to or greater than a predetermined threshold; and

a compressor configured to compress the unmapped data to have a predetermined compression length based on the offset value.

2. The controller according to claim 1, wherein the setter sets the offset values to logical addresses respectively corresponding to the unmapped data.

3. The controller of claim 1, wherein the setter sets the offset value to a physical address within a read mapped segment or a write mapped segment.

4. The controller according to claim 1, wherein the setter sets the offset value by performing a modulo operation on a logical address so that the compressed unmapped data has the predetermined compression length.

5. The controller of claim 1, wherein the mapping data and the non-mapping data are recorded in a mapping table.

6. The controller of claim 5, wherein the mapping data and the non-mapping data are recorded in the mapping table in units of mapping segments.

7. The controller according to claim 5, wherein a flag indicating mapping/non-mapping information corresponding to the mapping data and the non-mapping data, respectively, and a relationship between logical addresses and physical addresses corresponding to the mapping data and the non-mapping data are recorded in the mapping table.

8. The controller of claim 1, wherein the memory changes the mapped data to the unmapped data in response to an unmapped command.

9. The controller of claim 8, wherein the memory sets a most significant bit of the unmapped data to have a specific value.

10. The controller of claim 1, wherein the compressor stores the compressed unmapped data in the memory.

11. A method of operation of a controller, the method of operation comprising the steps of:

storing the mapped data and the unmapped data;

counting the number of the unmapped data;

setting an offset value for each of the unmapped data; and

compressing the unmapped data to have a predetermined compression length based on the offset value.

12. The operating method of claim 11, wherein the step of setting the offset value comprises the steps of:

setting the offset values to logical addresses respectively corresponding to the unmapped data.

13. The operating method of claim 11, wherein the step of setting the offset value comprises the steps of:

setting the offset value to a physical address within a read mapped segment or a write mapped segment.

14. The operating method of claim 11, wherein the step of setting the offset value comprises the steps of:

the offset value is set by performing a modulo operation on the logical address such that the compressed unmapped data has a predetermined compression length.

15. The method of operation of claim 11, further comprising the steps of:

recording the mapping data and the non-mapping data in a mapping table.

16. The operating method of claim 15, wherein the mapping data and the non-mapping data are recorded in the mapping table in units of mapping segments.

17. The operating method of claim 15, wherein a flag indicating mapping/non-mapping information corresponding to the mapping data and the non-mapping data, respectively, and a relationship between logical addresses and physical addresses corresponding to the mapping data and the non-mapping data are recorded in the mapping table.

18. The method of operation of claim 11, further comprising the steps of:

receiving a non-mapping command; and

changing the mapping data to the non-mapping data in response to the non-mapping command.

19. The method of operation of claim 18, further comprising the steps of:

setting a most significant bit of the unmapped data to have a specific value.

20. The method of operation of claim 15, further comprising the steps of:

and storing the compressed non-mapping data in the mapping table.

21. A method of operation of a controller, the method of operation comprising the steps of:

detecting non-mapping data in a mapping table;

appending an offset value to each of the unmapped data; and

compressing the unmapped data based on the appended offset value.

Technical Field

Various embodiments of the present invention relate generally to a controller, and more particularly, to a controller capable of efficiently processing data and an operating method thereof.

Background

Computer environment paradigms have turned to pervasive computing, which enables computing systems to be used anytime and anywhere. As a result, the demand for portable electronic devices such as mobile phones, digital cameras, and laptop computers has rapidly increased. These electronic devices typically include memory systems that use memory devices as data storage devices. The data storage device may be used as a primary memory unit or a secondary memory unit of the portable electronic device.

The data storage device using the memory device provides advantages such as excellent stability and durability, high information access speed, and low power consumption because of the absence of a mechanical driving part. In addition, the data storage device may have a higher data access rate and lower power consumption than the hard disk device. Non-limiting examples of data storage devices having these advantages include Universal Serial Bus (USB) memory devices, memory cards for various interfaces, Solid State Drives (SSDs), and the like.

Disclosure of Invention

Various embodiments of the present invention relate to a memory system capable of efficiently using a cache memory by compressing unmapped data.

According to an embodiment of the present invention, a controller may include: a memory configured to store mapped data and unmapped data; a counter configured to count a number of the unmapped data stored in the memory; a setter configured to set an offset value for each of the non-mapped data when the number of the non-mapped data is equal to or greater than a predetermined threshold; and a compressor configured to compress the unmapped data to have a predetermined compression length based on the offset value.

According to an embodiment of the present invention, a method of operating a controller may include the steps of: storing the mapped data and the unmapped data; counting the number of the unmapped data; setting an offset value for each of the unmapped data; and compressing the unmapped data to have a predetermined compression length based on the offset value.

According to an embodiment of the present invention, a method of operating a controller may include the steps of: detecting non-mapping data in a mapping table; appending an offset value to each of the unmapped data; and compressing the unmapped data based on the appended offset value.

Drawings

The description herein makes reference to the accompanying drawings wherein like reference numerals refer to like parts throughout the several views, and wherein:

FIG. 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating a configuration of a memory device of the memory system shown in FIG. 1;

fig. 3 is a circuit diagram illustrating a configuration of a memory cell array of a memory block in the memory device shown in fig. 2;

FIG. 4 is a schematic diagram illustrating a three-dimensional (3D) structure of the memory device shown in FIG. 2;

FIG. 5 is a diagram illustrating a memory system according to an embodiment of the present disclosure;

fig. 6A to 6C are diagrams for describing an operation of setting an offset value corresponding to unmapped data according to an embodiment of the present disclosure;

FIG. 7 is a flow chart for describing the operation of a controller according to an embodiment of the present disclosure;

fig. 8 to 16 are diagrams schematically illustrating application examples of a data processing system according to various embodiments of the present disclosure.

Detailed Description

Various examples of the disclosure are described in more detail below with reference to the accompanying drawings. The present disclosure may be embodied in other different embodiments, forms and variations, and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art to which the invention pertains. Throughout the disclosure, like reference numerals refer to like parts in the various figures and examples of the disclosure. It is noted that references to "an embodiment," "another embodiment," and the like do not necessarily mean only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element described below may also be referred to as a second element or a third element without departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it will be understood that the former may be directly connected or coupled to the latter, or electrically connected or coupled to the latter via intervening elements therebetween.

It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly on, connected or coupled to the other element or one or more intervening elements may be present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms and vice versa, unless the context clearly indicates otherwise. The articles "a" and "an" as used in this application and the appended claims should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form.

It will be further understood that the terms "comprises," "comprising," and their derivatives, when used in this specification, specify the presence of stated elements, and do not preclude the presence or addition of one or more other elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs in view of this disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be practiced without some or all of these specific details. In other instances, well known process structures and/or processes have not been described in detail in order not to unnecessarily obscure the present invention.

It should also be noted that in some cases, features or elements described in connection with one embodiment may be used alone or in combination with other features or elements of another embodiment, unless expressly stated otherwise, as would be apparent to one skilled in the relevant art.

FIG. 1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

Referring to FIG. 1, data processing system 100 may include a host 102 operably coupled to a memory system 110.

The host 102 may include, for example, portable electronic devices such as mobile phones, MP3 players, and laptop computers, or electronic devices such as desktop computers, game consoles, Televisions (TVs), projectors, and the like.

The memory system 110 may operate or perform particular functions or operations in response to requests from the host 102, and in particular, may store data to be accessed by the host 102. The memory system 110 may be used as a primary memory system or a secondary memory system for the host 102. The memory system 110 may be implemented with any of various types of storage devices that may be electrically coupled to the host 102, according to the protocol of the host interface. Non-limiting examples of suitable storage devices include Solid State Drives (SSDs), multimedia cards (MMCs), embedded MMCs (emmcs), reduced size MMCs (RS-MMCs) and micro-MMCs, Secure Digital (SD) cards, mini-SD and micro-SD, Universal Serial Bus (USB) storage devices, Universal Flash Storage (UFS) devices, Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, and the like.

Storage devices for memory system 110 may be implemented with volatile memory devices such as, for example, Dynamic Random Access Memory (DRAM) and static RAM (sram), and/or non-volatile memory devices such as Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), ferroelectric RAM (fram), phase change RAM (pram), magnetoresistive RAM (mram), resistive RAM (RRAM or ReRAM), and flash memory.

Memory system 110 may include a controller 130 and a memory device 150. Memory device 150 may store data to be accessed by host 102, and controller 130 may control the storage of data in memory device 150.

The controller 130 and the memory device 150 may be integrated into a single semiconductor device, which may be included in various types of memory systems as illustrated above.

The memory system 110 may be configured as part of, for example: a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a Portable Multimedia Player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, a digital video player, a storage configuring a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a vehicle-mounted information network, a computer, a, A Radio Frequency Identification (RFID) device or configure one of various components of a computing system.

The memory device 150 may be a non-volatile memory device and may retain data stored therein even when power is not supplied. The memory device 150 may store data provided from the host 102 through a write operation and provide data stored therein to the host 102 through a read operation. Memory device 150 may include a plurality of memory blocks 152 through 156, and each of memory blocks 152 through 156 may include a plurality of pages. Each of the plurality of pages may include a plurality of memory cells electrically coupled with a plurality of Word Lines (WLs).

The controller 130 may control overall operations of the memory device 150 such as a read operation, a write operation, a program operation, and an erase operation. For example, the controller 130 may control the memory device 150 in response to a request from the host 102. Controller 130 may provide data read from memory device 150 to host 102 and/or may store data provided by host 102 into memory device 150.

Controller 130 may include a host interface (I/F)132, a processor 134, an Error Correction Code (ECC) component 138, a Power Management Unit (PMU)140, a memory interface (I/F)142, and a memory 144, all operatively coupled via an internal bus.

The host interface 132 may process commands and data provided from the host 102 and may communicate with the host 102 through at least one of various interface protocols such as: universal Serial Bus (USB), multi-media card (MMC), peripheral component interconnect express (PCI-e or PCIe), Small Computer System Interface (SCSI), serial attached SCSI (sas), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

The ECC component 138 may detect and correct errors in data read from the memory device 150 during a read operation. When the number of erroneous bits is greater than or equal to the threshold number of correctable erroneous bits, the ECC component 138 may not correct the erroneous bits, but may output an error correction failure signal indicating that the correction of the erroneous bits failed.

The ECC component 138 may perform error correction operations based on code modulation such as Low Density Parity Check (LDPC) codes, Bose-Chaudhuri-hocquenghem (bch) codes, turbo codes, Reed-solomon (rs) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), Block Coded Modulation (BCM), and the like. The ECC component 138 may include all or some of the circuitry, modules, systems, or devices used to perform error correction operations based on at least one of the above-described codes.

PMU 140 may provide and manage power for controller 130.

Memory interface 142 may serve as an interface for handling commands and data transferred between controller 130 and memory devices 150 to allow controller 130 to control memory devices 150 in response to requests delivered from host 102. In the case when the memory device 150 is a flash memory (specifically, when the memory device 150 is a NAND flash memory), the memory interface 142 may generate a control signal for the memory device 150 and may process data input into the memory device 150 or output from the memory device 150 under the control of the processor 134.

The memory 144 may serve as a working memory of the memory system 110 and the controller 130, and may store temporary data or transaction data for operating or driving the memory system 110 and the controller 130. The controller 130 may control the memory device 150 in response to a request from the host 102. The controller 130 may deliver data read from the memory device 150 to the host 102, and may store data input through the host 102 within the memory device 150. Memory 144 may be used to store data needed by controller 130 and memory device 150 to perform these operations.

The memory 144 may be implemented using volatile memory. The memory 144 may be implemented using Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). Although fig. 1 illustrates the memory 144 disposed within the controller 130, the present disclosure is not limited thereto. That is, the memory 144 may be internal or external to the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transfers data and/or signals transferred between the memory 144 and the controller 130.

Processor 134 may control the overall operation of memory system 110. Processor 134 may drive or execute firmware to control the overall operation of memory system 110. The firmware may be referred to as a Flash Translation Layer (FTL).

The FTL may perform operations such as interfacing between the host 102 and the memory device 150. The host 102 may send requests for write and read operations to the memory device 150 through the FTL.

The FTL may manage address mapping, garbage collection, wear leveling, etc. In particular, the FTL may store mapping data. Thus, the controller 130 may map logical addresses provided from the host 102 to physical addresses of the memory device 150 by the mapping data. Due to the address mapping operation, memory device 150 may perform operations similar to general purpose devices. In addition, through an address mapping operation based on the mapping data, when the controller 130 updates data of a specific page, the controller 130 may program new data on another empty page and may invalidate old data of the specific page due to characteristics of the flash memory device. In addition, the controller 130 may store the mapping data of the new data in the FTL.

Processor 134 may be implemented with a microprocessor or Central Processing Unit (CPU). The memory system 110 may include one or more processors 134.

A management unit (not shown) may be included in the processor 134. The management unit may perform bad block management of the memory device 150. The management unit may find bad memory blocks included in the memory device 150 and perform bad block management on the bad memory blocks, which are in an unsatisfactory condition for further use. When the memory device 150 is a flash memory (e.g., a NAND flash memory), a program failure may occur during a write operation (e.g., during a program operation) due to the characteristics of the NAND logic function. During bad block management, data of a memory block that failed programming or a bad memory block may be programmed into a new memory block. The bad block seriously deteriorates the utilization efficiency of the memory device 150 having the 3D stacked structure and the reliability of the memory system 110, and thus reliable bad block management is required.

Fig. 2 is a schematic diagram illustrating a memory device 150.

Referring to fig. 2, the memory device 150 may include a plurality of memory BLOCKs BLOCK0 through BLOCK-1, and each of the BLOCKs BLOCK0 through BLOCK-1 may include a plurality of pages, e.g., 2^MA number of pages (which number may vary depending on circuit design). Depending on the number of bits that can be stored or represented in each memory cell, memory device 150 may include multiple memory blocks as Single Level Cell (SLC) memory blocks and multi-level cell (MLC) memory blocks. The SLC memory block may include a plurality of pages implemented with memory cells that are each capable of storing 1 bit of data. An MLC memory block may include multiple pages implemented with memory cells that are each capable of storing multiple bits of data (e.g., two or more bits of data). An MLC memory block including a plurality of pages implemented with memory cells each capable of storing 3-bit data may be defined as a Triple Level Cell (TLC) memory block.

Fig. 3 is a circuit diagram illustrating a memory block 330 in the memory device 150.

Referring to fig. 3, the memory block 330 may correspond to any one of a plurality of memory blocks 152 to 156 included in the memory device 150 of the memory system 110.

Referring to fig. 3, a memory block 330 of the memory device 150 may include a plurality of cell strings 340 electrically coupled to bit lines BL0 through BLm-1, respectively. Each column of the cell strings 340 may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC0 through MCn-1 may be electrically coupled in series between select transistors DST and SST. The respective memory cells MC0 through MCn-1 may be configured by Single Level Cells (SLC) each capable of storing 1-bit information or by multi-level cells (MLC) each capable of storing multiple bits of data information. However, the present invention is not limited to only SLC or MLC. Strings 340 may be electrically coupled to corresponding bit lines BL 0-BLm-1, respectively. For reference, in fig. 3, "DSL" denotes a drain select line, "SSL" denotes a source select line, and "CSL" denotes a common source line.

Although fig. 3 shows, as an example only, that the memory block 330 is composed of NAND flash memory cells, it should be noted that the memory block 330 of the memory device 150 according to the embodiment is not limited to a NAND flash memory. The memory block 330 may be implemented by a NOR flash memory, a hybrid flash memory in which at least two kinds of memory cells are combined, or a NAND flash memory in which a controller is built in a memory chip. The operation characteristics of the semiconductor device can be applied not only to a flash memory device in which a charge storage layer is composed of a conductive floating gate but also to a Charge Trap Flash (CTF) in which a charge storage layer is composed of a dielectric layer.

The power supply circuit 310 of the memory device 150 may provide word line voltages (e.g., a program voltage, a read voltage, and a pass voltage) to be provided to the respective word lines according to an operation mode and a voltage to be provided to a bulk (bulk) (e.g., a well region in which the memory cell is formed). The power supply circuit 310 may perform a voltage generating operation under the control of a control circuit (not shown). The power supply circuit 310 may generate a plurality of variable read voltages for generating a plurality of read data, select one of a sector or a memory block of the memory cell array under the control of the control circuit, select one of word lines of the selected memory block, and supply the word line voltage to the selected word line and the unselected word lines.

The read and write (read/write) circuits 320 of the memory device 150 may be controlled by the control circuit and may function as sense amplifiers or write drivers depending on the mode of operation. During a verify operation or a normal read operation, the read/write circuit 320 may operate as a sense amplifier for reading data from the memory cell array. During a programming operation, the read/write circuit 320 may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit 320 may receive data to be stored into the memory cell array from a buffer (not shown) and drive bit lines according to the received data. The read/write circuit 320 may include a plurality of page buffers 322 to 326 corresponding to columns (or bit lines) or column pairs (or bit line pairs), respectively, and each of the page buffers 322 to 326 may include a plurality of latches (not shown).

Fig. 4 is a schematic diagram illustrating a 3D structure of the memory device 150.

Although fig. 4 illustrates a 3D structure, the memory device 150 may be implemented by a two-dimensional (2D) or three-dimensional (3D) memory device. Specifically, as shown in fig. 4, the memory device 150 may be implemented in a nonvolatile memory device having a 3D stacked structure. When the memory device 150 has a 3D structure, the memory device 150 may include a plurality of memory blocks BLK0 through BLKN-1 each having a 3D structure (or a vertical structure).

As described with reference to fig. 1, the memory 144 may include a mapping cache. The map cache may store map data therein. The mapping data may represent a relationship between a Logical Block Address (LBA) and a Physical Block Address (PBA). The logical block address may be provided with data from the host 102 and may correspond to the data. The physical block address may indicate a storage location of data within the memory device 150. For example, the controller 130 may receive logical block addresses corresponding to write data from the host 102 and may allocate physical block addresses for storing the write data in the memory device 150 through the FTL. The memory 144 may store mapping data representing a relationship between a logical block address and a physical block address corresponding to the write data in a mapping buffer. Memory 144 may also include a mapping table in which the mapping data is an entry. In the mapping table, mapping data may be recorded in units of mapping segments. For example, when the size of a single mapping segment is 1024KB and the size of a single mapping data is 1KB, 1024 mapping data may be recorded in a single mapping table. The memory 144 may store a plurality of mapping tables. However, this is merely an example that will not limit the scope of the present invention. The structure of the mapping table will be described with reference to fig. 6A to 6C.

The controller 130 may read data in response to a read request provided from the host 102 based on the mapping data recorded in the mapping table. Specifically, in response to a read request provided from the host 102, the controller 130 may detect a logical address corresponding to the read request in the mapping table, may detect a physical address indicating a substantial storage location of target data based on mapping data including the detected logical address, and may read the target data stored in the storage location indicated by the detected physical address. The controller 130 may improve the performance of the read operation through the mapping table. However, the mapping cache for storing mapping data constituting the mapping table has a limited capacity, and thus the capacity of the mapping cache needs to be efficiently used.

According to an embodiment of the present disclosure, an operation method of the controller 130 for efficiently using the mapping cache is provided.

Fig. 5 is a diagram illustrating a memory system 110 according to an embodiment of the present invention.

Unlike the memory system 110 shown in fig. 1, fig. 5 illustrates only elements related to embodiments of the present disclosure. Accordingly, the memory system 110 of the present disclosure is not limited to the elements shown in the implementation of FIG. 5. As described with reference to fig. 1-4, memory system 110 may include a controller 130 and a memory device 150. Controller 130 may control memory device 150. Controller 130 may include a processor 134, a memory interface 142, and a memory 144.

Further, the controller 130 may include a counter 510, a setter 530, and a compressor 550.

The memory 144 may store the mapping data in a mapping cache. The memory 144 may store unmapped data, which is a type of mapped data that is unmapped in response to an unmapped command provided from the host 102, into a mapped cache. As described above, the mapping data may represent a relationship between logical addresses and physical addresses. However, unmapped data can no longer represent the relationship between logical and physical addresses. Thus, unmapped data is data that may not be needed on memory 144 and may be deleted at a later time.

The memory 144 may store a mapping table 570 in which mapping data and non-mapping data are recorded. The mapping table 570 may include a flag field and an address field. In the flag field, a flag may be recorded to distinguish mapping data from non-mapping data. In the address field, a logical address and a physical address (e.g., a block number and a page number) may be recorded. The value of the address field may represent a mapping between logical addresses and physical addresses ("L2P"). Both mapping data and non-mapping data may be recorded into the mapping table 570. In the memory 144, mapping/non-mapping bits may be used to distinguish mapping data from non-mapping data. For example, when the map/unmap bit has a value of "0" indicating unmapped data, the value of the Most Significant Bit (MSB) may be set to "0" to indicate unmapped data and may be stored in the memory 144. The unmapped data with a most significant bit having a value of "0" may correspond to a value of "U" in the flag field of the mapping table 570. In contrast, when the map/unmap bit has a "1" value indicating the map data, the value of the most significant bit may be set to "1" to indicate the map data and may be stored into the memory 144. The mapping data having the most significant bit of a value of "1" may correspond to the value of "M" in the flag field of the mapping table 570. However, this is merely an example that will not limit the scope of the present invention.

The processor 134 may control the memory device 150 via the memory interface 142 to store therein mapping data recorded in the mapping table 570 stored in the mapping cache of the memory 144 in response to a refresh (flush) command provided from the host 102.

According to an embodiment of the present invention, the counter 510 may count the number of unmapped data recorded in the entire mapping table 570 stored in the memory 144. According to an embodiment of the present invention, the counter 510 may count the number of unmapped data recorded in the mapping table 570 in units of mapped segments. The counter 510 may compare the counted number of unmapped data to a predetermined threshold. The counter 510 may provide the comparison result to the setter 530.

The setter 530 may set an offset value for each of the unmapped data when the number of unmapped data is equal to or greater than a predetermined threshold.

According to an embodiment of the present invention, the setter 530 may set (or attach) an offset value to a logical address corresponding to the unmapped data. The setter 530 may arrange the non-mapping data based on the mapping table 570 such that an offset value of the non-mapping data increases as the offset value increases (i.e., as the logical address increases).

According to an embodiment of the present invention, the setter 530 may set (or append) the offset value to a physical address within the read mapped segment or the write mapped segment. Assume that when the size of the read map segment is 512KB, the size of the write map segment is 1024KB, and the size of a single map data is 1KB, 1024 map data are included in the write map segment and 512 map data are included in the read map segment. However, this is merely an example that will not limit the scope of the present invention. As described above, the counter 510 may count the number of unmapped data included in each mapped segment. When the number of unmapped data included in a single mapped segment is equal to or greater than a predetermined threshold, the setter 530 may arrange the unmapped data such that the offset value of the unmapped data increases as the physical address increases. For example, when there is first non-mapped data corresponding to the memory block "100" and the page "5" and second non-mapped data corresponding to the memory block "100" and the page "1", the setter 530 may arrange the first non-mapped data and the second non-mapped data in the order of the second non-mapped data and the first non-mapped data. For example, when there is third non-mapped data corresponding to the memory block "50" and the page "5" and fourth non-mapped data corresponding to the memory block "70" and the page "5", the setter 530 may arrange the third non-mapped data and the fourth non-mapped data in the order of the third non-mapped data and the fourth non-mapped data.

According to an embodiment of the present disclosure, the setter 530 may set the offset value by performing a modulo operation on the logical address such that the unmapped data is compressed to have a predetermined compression length. For example, when the compressor 550 compresses the unmapped data to have a compression length of "100", the setter 530 sets the offset value from "1" to "100" as the logical address increases. That is, when there are unmapped data corresponding to the logical addresses LBA1 to LBA100, respectively, the setter 530 may set offset values of "1" to "100" for the unmapped data corresponding to the logical addresses LBA1 to LBA100, respectively. Further, when there are non-mapping data corresponding to logical addresses LBA101 to LBA200, respectively, setter 530 may set offset values of "1" to "100" for the non-mapping data corresponding to logical addresses LBA101 to LBA200, respectively.

The setter 530 may provide the set offset value to the compressor 550.

The compressor 550 may compress the unmapped data to have a predetermined compression length based on the provided offset value. For example, when the predetermined compression length is "50", the compressor 550 may compress the unmapped data corresponding to the offset values of "1" to "50" and the unmapped data corresponding to the offset values of "51" to "100" based on the offset values of "1" to "100" to generate two pieces of compressed unmapped data. The compressed unmapped data may include a starting logical address or starting physical address, a starting offset value corresponding to the starting logical address or starting physical address, and a number of pieces of unmapped data. For example, when "100" pieces of unmapped data having offset values from "5" to "104" are compressed into compressed unmapped data, the compressed unmapped data may include a value of "5" as a starting offset value corresponding to a starting logical address or a starting physical address and a value of "100" as the number of pieces of unmapped data.

The compressor 550 may provide the compressed unmapped data to the memory 144. The memory 144 may store the compressed unmapped data in a map cache.

As described above, according to the embodiment of the present disclosure, the controller 130 may compress the non-mapped data, and thus may efficiently utilize the mapping buffer within the memory 144 having a limited capacity.

Fig. 6A to 6C are diagrams for describing an operation of setting an offset value corresponding to unmapped data according to an embodiment of the present disclosure.

Fig. 6A to 6C illustrate the first and second mapping tables 610 and 650. For clarity of description, the first mapping table 610 and the second mapping table 650 are shown separately, but the first mapping table 610 and the second mapping table 650 are substantially the same mapping table. In the embodiment shown in fig. 6A to 6C, it is assumed that 6 pieces of mapping data are recorded in the first mapping table 610 and 6 pieces of non-mapping data are recorded in the second mapping table 650. It is also assumed that a non-mapping command for all mapping data recorded in the first mapping table 610 is provided, so that all mapping data of the first mapping table 610 becomes non-mapping data and the non-mapping data is recorded into the second mapping table 650.

Each of the first and second mapping tables 610 and 650 may have fields for a Flag ("Flag"), a logical address ("LBA"), a storage Block number ("Block"), and a Page number ("Page") to record mapping data and non-mapping data. As shown in fig. 6A to 6C, all data recorded in the first mapping table 610 is mapping data because all flag fields corresponding to the data are recorded as a value "M". In contrast, all data recorded in the second mapping table 650 is non-mapped data because all flag fields corresponding to the data are recorded as the value "U".

As shown in fig. 6A to 6C, the setter 530 may set an offset value ("offset") corresponding to unmapped data recorded in the second mapping table 650.

Referring to fig. 6A, the setter 530 may set an offset value to a logical address (LBA) corresponding to unmapped data.

For example, the setter 530 may set an offset value "1" for unmapped data corresponding to a logical address (LBA) "1"; the setter 530 may set an offset value of "2" for unmapped data corresponding to the logical address of "2"; and the setter 530 may set an offset value of "3" for the unmapped data corresponding to the logical address of "3". In a similar manner, the setter 530 may set an offset value with respect to the unmapped data such that the offset value of the unmapped data increases as the logical address corresponding to the unmapped data increases.

Referring to fig. 6B, the setter 530 may set the offset value to a physical address within the read map segment or the write map segment. It is assumed that a plurality of pieces of mapping data recorded in the first mapping table 610 configure a single write mapping segment.

For example, as shown in fig. 6B, the setter 530 may set an offset value from the smallest storage block number among the plurality of pieces of unmapped data recorded in the second mapping table 650. For example, the setter 530 may set an offset value of "1" for unmapped data having a minimum storage block number of "10" among the pieces of unmapped data recorded in the second mapping table 650; the setter 530 may set an offset value of "2" for unmapped data of a second minimum storage block number of "20" among the plurality of unmapped data recorded in the second mapping table 650; and the setter 530 may set an offset value of "3" for the unmapped data of the storage block number of "40" (i.e., the third smallest storage block) among the plurality of unmapped data recorded in the second mapping table 650. When there are a plurality of pieces of unmapped data corresponding to the same memory block number among the plurality of pieces of unmapped data recorded in the second mapping table 650, the setter 530 may set an offset value for the plurality of pieces of unmapped data corresponding to the same memory block number based on the page number. For example, the setter 530 may set an offset value "4" for unmapped data having a smallest page number "1" among a plurality of unmapped data corresponding to the same memory block number "100" in the second mapping table 650; the setter 530 may set an offset value "5" for unmapped data having a second minimum page number "2" among a plurality of unmapped data corresponding to the same memory block number "100" in the second mapping table 650; and the setter 530 may set an offset value of "6" for unmapped data of page number "5" among a plurality of unmapped data corresponding to the same memory block number "100" in the second mapping table 650. However, this is merely an example that will not limit the scope of the present invention.

Referring to fig. 6C, the setter 530 may set the offset value by performing a modulo operation on the logical address (LBA) such that the unmapped data is compressed to have a predetermined compression length. Assume that the predetermined compression length is "3". That is, it is assumed that 3 pieces of unmapped data are compressed into compressed unmapped data.

As shown in fig. 6C, the setter 530 may set an offset value of the unmapped data substantially according to a logical address (LBA) corresponding to the unmapped data. However, since the predetermined compression length is "3", the maximum value of the offset value may be limited to the value "3". Accordingly, as described with reference to fig. 3, the setter 530 may set offset values "1" to "3" for unmapped data corresponding to logical addresses (LBAs) of "1" to "3". Then, the setter 530 may set the offset value to "1" to "3" instead of "4" to "6" for the unmapped data corresponding to the logical address of "4" to "6". When the offset value is set as described with reference to fig. 6A, a single piece of compressed unmapped data may be generated. However, when the offset value is set as described with reference to fig. 6C, 2 pieces of compressed unmapped data may be generated. However, this is merely an example that will not limit the scope of the present invention.

Fig. 7 is a flowchart for describing an operation of the controller 130 according to an embodiment of the present disclosure. What is described with reference to fig. 6A to 7 will be the operation of the controller 130.

It is assumed that a non-mapping command for all mapping data recorded in the first mapping table 610 is provided from the host 102 to the controller 130.

In step S701, the memory 144 may update the first mapping table 610 to the second mapping table 650 in response to a non-mapping command provided from the host 102.

In step S703, the counter 510 may count the number of pieces of unmapped data recorded in the second mapping table 650.

In step S705, the counter 510 may compare the number of counted pieces of the non-mapping data with a predetermined threshold. The counter 510 may provide the comparison result to the setter 530.

When the number of counted pieces of non-mapping data is less than the predetermined threshold value (step S705: NO), the process may be repeated from step S701 onward.

When the counted number of pieces of the unmapped data is equal to or greater than the predetermined threshold value (step S705: YES), the setter 530 may set offset values for the unmapped data in step S707, respectively. For example, as described with reference to fig. 6A to 6C, the setter 530 may set a logical address corresponding to the unmapped data to an offset value of the unmapped data. The setter 530 may provide the offset value to the compressor 550.

In step S709, the compressor 550 may compress the unmapped data to have a predetermined compression length based on the offset value. The compressor 550 may provide the compressed unmapped data to the memory 144.

In step S711, the memory 144 may store the compressed unmapped data into the map cache.

In other words, the operation of the controller 130 according to an embodiment of the present disclosure may include: detecting unmapped data in the mapping table (e.g., S703 and S705); adding offset values to the respective unmapped data (e.g., S707); and compressing the unmapped data based on the appended offset value (e.g., S709).

Hereinafter, a data processing system and an electronic device, which may be implemented with the memory system 110 including the memory device 150 and the controller 130, which have been described with reference to fig. 1 to 7, will be described in detail with reference to fig. 8 to 16.

Fig. 8 to 16 are diagrams schematically illustrating application examples of the data processing system of fig. 1 to 7 according to various embodiments.

FIG. 8 is a diagram schematically illustrating an example of a data processing system including a memory system according to an embodiment. Figure 8 schematically illustrates a memory card system 6100 that includes a memory system in accordance with an embodiment.

Referring to fig. 8, a memory card system 6100 may include a memory controller 6120, a memory device 6130, and a connector 6110.

More specifically, the memory controller 6120 may be connected to the memory device 6130 and may be configured to access the memory device 6130. The memory device 6130 may be implemented by a non-volatile memory (NVM). By way of example, and not limitation, the memory controller 6120 may be configured to control read operations, write operations, erase operations, and background operations to the memory device 6130. The memory controller 6120 may be configured to provide an interface between the memory device 6130 and a host (not shown) and/or drive firmware for controlling the memory device 6130. That is, the memory controller 6120 may correspond to the controller 130 in the memory system 110 described with reference to fig. 1 to 7, and the memory device 6130 may correspond to the memory device 150 described with reference to fig. 1 to 7.

Thus, as shown in FIG. 1, the memory controller 6120 may include Random Access Memory (RAM), a processor, a host interface, a memory interface, and error correction code components. Memory controller 130 may also include the elements described in FIG. 1.

The memory controller 6120 may communicate with an external device (e.g., the host 102 of fig. 1) through the connector 6110. For example, as described with reference to fig. 1, the memory controller 6120 may be configured to communicate with external devices through one or more of various communication protocols such as: universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (pcie), Advanced Technology Attachment (ATA), serial ATA, parallel ATA, Small Computer System Interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), firewire, Universal Flash Storage (UFS), wireless fidelity (Wi-Fi or WiFi), and bluetooth. Accordingly, the memory system and the data processing system according to embodiments may be applied to wired and/or wireless electronic devices or in particular mobile electronic devices.

The memory device 6130 can be implemented by a nonvolatile memory. For example, memory device 6130 may be implemented by various non-volatile memory devices such as erasable programmable rom (eprom), electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase-change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), and spin transfer torque magnetic RAM (STT-RAM). Memory device 6130 may include multiple dies (die) as in memory device 150 of fig. 1.

The memory controller 6120 and the memory device 6130 may be integrated into a single semiconductor device. For example, the memory controller 6120 and the memory device 6130 may configure a Solid State Drive (SSD) by being integrated into a single semiconductor device. In addition, the memory controller 6120 and the memory device 6130 may configure memory cards such as PC cards (e.g., Personal Computer Memory Card International Association (PCMCIA)), Compact Flash (CF) cards, smart media cards (e.g., SM and SMC), memory sticks, multimedia cards (e.g., MMC, RS-MMC, MMCmicro, and eMMC), Secure Digital (SD) cards (e.g., SD, miniSD, microSD, and SDHC), and Universal Flash Storage (UFS).

Fig. 9 is a diagram schematically illustrating another example of a data processing system 6200 including a memory system according to an embodiment.

Referring to fig. 9, a data processing system 6200 may include a memory device 6230 having one or more non-volatile memories (NVMs) and a memory controller 6220 for controlling the memory device 6230. As described with reference to fig. 1, the data processing system 6200 may be used as a storage medium such as a memory card (CF, SD, micro-SD, or the like) or a USB device. The memory device 6230 may correspond to the memory device 150 in the memory system 110 described in fig. 1 to 7, and the memory controller 6220 may correspond to the controller 130 in the memory system 110 described in fig. 1 to 7.

The memory controller 6220 may control read, write, or erase operations to the memory device 6230 in response to requests by the host 6210, and the memory controller 6220 may include one or more Central Processing Units (CPUs) 6221, a buffer memory such as a Random Access Memory (RAM)6222, an Error Correction Code (ECC) circuit 6223, a host interface 6224, and a memory interface such as an NVM interface 6225.

The CPU 6221 may control operations on the memory device 6230, such as a read operation, a write operation, a file system management operation, and a bad page management operation. The RAM6222 can operate under the control of the CPU 6221, and functions as a work memory, a buffer memory, or a cache memory. When the RAM6222 is used as a working memory, data processed by the CPU 6221 may be temporarily stored in the RAM 6222. When RAM6222 is used as a buffer memory, RAM6222 can be used to buffer data sent from the host 6210 to the memory device 6230 or from the memory device 6230 to the host 6210. When RAM6222 is used as cache memory, RAM6222 can assist the memory device 6230 in high-speed operations.

The ECC circuit 6223 may correspond to the ECC component 138 of the controller 130 shown in fig. 1. As described with reference to fig. 1, the ECC circuit 6223 may generate an Error Correction Code (ECC) for correcting failed or erroneous bits of data provided from the memory device 6230. ECC circuitry 6223 may perform error correction coding on the data provided to memory device 6230, thereby forming data having parity bits. The parity bits may be stored in memory device 6230. The ECC circuit 6223 may perform error correction decoding on the data output from the memory device 6230. In this case, the ECC circuit 6223 may correct errors using parity bits. For example, as described with reference to fig. 1, the ECC circuit 6223 may correct errors using a Low Density Parity Check (LDPC) code, a Bose-Chaudhri-hocquenghem (bch) code, a turbo code, a Reed-Solomon code, a convolutional code, a Recursive Systematic Code (RSC), or a coded modulation such as Trellis Coded Modulation (TCM) or Block Coded Modulation (BCM).

Memory controller 6220 can send data or signals to and/or receive data or signals from host 6210 through host interface 6224 and can send data or signals to and/or receive data or signals from memory device 6230 through NVM interface 6225. The host interface 6224 may be connected to the host 6210 by a Parallel Advanced Technology Attachment (PATA) bus, a Serial Advanced Technology Attachment (SATA) bus, a Small Computer System Interface (SCSI), a Universal Serial Bus (USB), a peripheral component interconnect express (PCIe), or a NAND interface. The memory controller 6220 may have a wireless communication function using a mobile communication protocol such as wireless fidelity (WiFi) or Long Term Evolution (LTE). The memory controller 6220 may connect to an external device (e.g., the host 6210) or another external device and then transmit and/or receive data to/from the external device. Since the memory controller 6220 is configured to communicate with an external device through one or more of various communication protocols, the memory system and the data processing system according to the embodiment may be applied to wired and/or wireless electronic devices or particularly mobile electronic devices.

FIG. 10 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 10 schematically illustrates a Solid State Drive (SSD) to which the memory system according to the embodiment is applied.

Referring to fig. 10, the SSD6300 may include a controller 6320 and a memory device 6340 including a plurality of nonvolatile memories (NVMs). The controller 6320 may correspond to the controller 130 in the memory system 110 of fig. 1, and the memory device 6340 may correspond to the memory device 150 in the memory system of fig. 1.

More specifically, the controller 6320 may be connected to the memory device 6340 through a plurality of channels CH1 through CHi. The controller 6320 may include one or more processors 6321, Error Correction Code (ECC) circuitry 6322, a host interface 6324, a buffer memory 6325, and a memory interface such as a non-volatile memory interface 6326.

The buffer memory 6325 may temporarily store data supplied from the host 6310 or data supplied from a plurality of flash NVMs included in the memory device 6340, or temporarily store metadata of the plurality of flash NVMs, for example, mapping data including a mapping table. The buffer memory 6325 may be implemented by volatile memory such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, low power DDR (lpddr) SDRAM, and graphics RAM (gram), or non-volatile memory such as ferroelectric RAM (fram), resistive RAM (RRAM or ReRAM), spin transfer torque magnetic RAM (STT-MRAM), and phase change RAM (pram). For descriptive purposes, fig. 10 illustrates the buffer memory 6325 as being present in the controller 6320, but the buffer memory 6325 may be located or arranged outside the controller 6320.

The ECC circuit 6322 may calculate an Error Correction Code (ECC) value of data to be programmed to the memory device 6340 during a programming operation, perform an error correction operation on data read from the memory device 6340 based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device 6340 during a failed data recovery operation.

The host interface 6324 may provide an interface function with an external device (e.g., a host 6310), and the nonvolatile memory interface 6326 may provide an interface function with the memory device 6340 connected through a plurality of channels.

Further, a plurality of SSDs 6300 to which the memory system 110 of fig. 1 is applied may be provided to implement a data processing system, for example, a Redundant Array of Independent Disks (RAID) system. The RAID system may include a plurality of SSDs 6300 and a RAID controller for controlling the plurality of SSDs 6300. When the RAID controller performs a programming operation in response to a write command provided from the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 according to a plurality of RAID levels in the SSDs 6300 (i.e., RAID level information of the write command provided from the host 6310), and may output data corresponding to the write command to the selected SSDs 6300. Further, when the RAID controller performs a read operation in response to a read command provided by the host 6310, the RAID controller may select one or more memory systems or SSDs 6300 according to a plurality of RAID levels in the SSD6300 (i.e., RAID level information of the read command provided from the host 6310), and provide data read from the selected SSDs 6300 to the host 6310.

FIG. 11 is a diagram schematically illustrating another example of a data processing system including a memory system, according to an embodiment. Fig. 11 schematically illustrates an embedded multimedia card (eMMC)6400 to which a memory system according to an embodiment is applied.

Referring to fig. 11, the eMMC 6400 may include a controller 6430 and a memory device 6440 implemented by one or more NAND flash memories. The controller 6430 may correspond to the controller 130 in the memory system 110 of fig. 1, and the memory device 6440 may correspond to the memory device 150 in the memory system 110 of fig. 1.

More specifically, the controller 6430 may be connected to the memory device 6440 through a plurality of channels. The controller 6430 may include one or more cores 6432, a host interface (I/F)6431, and a memory interface such as a NAND interface (I/F) 6433.

The core 6432 may control operation of the eMMC 6400 and the host interface 6431 may provide interface functions between the controller 6430 and the host 6410. The NAND interface 6433 may provide an interface function between the memory device 6440 and the controller 6430. For example, the host interface 6431 may function as a parallel interface, e.g., an MMC interface as described with reference to fig. 1. In addition, the host interface 6431 may be used as a serial interface, for example, Ultra High Speed (UHS) -I and UHS-II interfaces.

Fig. 12 to 15 are diagrams schematically illustrating other examples of a data processing system including a memory system according to an embodiment. Fig. 12 to 15 schematically illustrate a Universal Flash Storage (UFS) system to which the memory system according to the embodiment is applied.

Referring to fig. 12-15, UFS system 6500 may include a host 6510, UFS device 6520, and UFS card 6530; UFS system 6600 may include host 6610, UFS device 6620, and UFS card 6630; UFS system 6700 may include a host 6710, UFS device 6720, and UFS card 6730; and UFS system 6800 may include host 6810, UFS device 6820, and UFS 6830. Host 6510, 6610, 6710, 6810 can function as an application processor for wired and/or wireless electronic devices or, in particular, mobile electronic devices, and UFS device 6520, 6620, 6720, 6820 can function as an embedded UFS device. UFS cards 6530, 6630, 6730, 6830 may function as external embedded UFS devices or removable UFS cards.

Hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 in respective UFS systems 6500, 6600, 6700, and 6800 may communicate with external devices (e.g., wired and/or wireless electronic devices or, in particular, mobile electronic devices) via the UFS protocol. UFS devices 6520, 6620, 6720, 6820 and UFS cards 6530, 6630, 6730, 6830 may be implemented by memory system 110 shown in fig. 1. For example, in UFS systems 6500, 6600, 6700, 6800, UFS devices 6520, 6620, 6720, 6820 may be implemented in the form of a data processing system 6200, SSD6300, or eMMC 6400 described with reference to fig. 9 through 11, and UFS cards 6530, 6630, 6730, 6830 may be implemented in the form of a memory card system 6100 described with reference to fig. 8.

Further, in UFS systems 6500, 6600, 6700, and 6800, hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820, and UFS cards 6530, 6630, 6730, 6830 may communicate with each other through UFS interfaces, such as MIPI M-PHY and MIPI UniPro (unified protocol) in MIPI (mobile industry processor interface). Further, UFS devices 6520, 6620, 6720, 6820 and UFS cards 6530, 6630, 6730, 6830 may communicate with each other through various protocols other than the UFS protocol, such as universal memory bus (USB) flash drive (UFD), multimedia card (MMC), Secure Digital (SD), mini-SD, and micro-SD.

In UFS system 6500 shown in fig. 12, each of host 6510, UFS device 6520, and UFS card 6530 may include UniPro. The host 6510 may perform a switching operation to communicate with at least one of the UFS device 6520 and the UFS card 6530. Host 6510 may communicate with UFS device 6520 or UFS card 6530 through a link layer switch at UniPro (e.g., an L3 switch). In this case, UFS device 6520 and UFS card 6530 may communicate with each other through a link layer switch at UniPro of host 6510. In the example, for convenience of description, a configuration in which one UFS device 6520 and one UFS card 6530 are connected to a host 6510 has been illustrated. However, multiple UFS devices and multiple UFS cards may be connected to host 6510 in parallel or in a star, and multiple UFS cards may be connected to UFS device 6520 in parallel or in a star, or connected to UFS device 6520 in series or in a chain. Here, the star form refers to an arrangement in which a single device is coupled with a plurality of other devices or cards for centralized control.

In UFS system 6600 shown in fig. 13, each of host 6610, UFS device 6620, and UFS card 6630 may include UniPro, and host 6610 may communicate with UFS device 6620 or UFS card 6630 through switching module 6640 that performs switching operations (e.g., through switching module 6640 that performs link-layer switching (e.g., L3 switching) at UniPro). UFS device 6620 and UFS card 6630 may communicate with each other through a link layer switch at UniPro by switch module 6640. In the example, for convenience of description, a configuration has been exemplified in which one UFS device 6620 and one UFS card 6630 are connected to the switching module 6640. However, multiple UFS devices and multiple UFS cards may be connected to switching module 6640 in parallel or in a star format, and multiple UFS cards may be connected to UFS device 6620 in series or in a chain format.

In UFS system 6700 shown in fig. 14, each of host 6710, UFS device 6720, and UFS card 6730 may include UniPro. The host 6710 may communicate with the UFS device 6720 or UFS card 6730 through a switching module 6740 that performs a switching operation (e.g., a switching module 6740 that performs a link layer switch (e.g., an L3 switch) at UniPro). In this case, UFS device 6720 and UFS card 6730 may communicate with each other through link-layer switching of switching module 6740 at UniPro, and switching module 6740 may be integrated with UFS device 6720 as one module inside or outside UFS device 6720. In the example, for convenience of description, a configuration in which one UFS device 6720 and one UFS card 6730 are connected to a switching module 6740 has been exemplified. However, a plurality of modules each including the switching module 6740 and the UFS device 6720 may be connected to the main machine 6710 in parallel or in a star form, or connected to each other in series or in a chain form. Further, multiple UFS cards may be connected in parallel or in a star format to UFS device 6720.

In UFS system 6800 shown in fig. 15, each of host 6810, UFS device 6820, and UFS card 6830 may include a M-PHY and UniPro. UFS device 6820 may perform a switching operation to communicate with host 6810 and UFS card 6830. UFS device 6820 may communicate with host 6810 or UFS card 6830 through a switchover operation (e.g., through a target Identifier (ID) switchover operation) between the M-PHY and UniPro modules used to communicate with host 6810 and the M-PHY and UniPro modules used to communicate with UFS card 6830. Here, the host 6810 and the UFS card 6830 can communicate with each other through target ID switching between the M-PHY of the UFS device 6820 and the UniPro module. In the embodiment, for convenience of description, a configuration in which one UFS device 6820 is connected to the host 6810 and one UFS card 6830 is connected to the UFS device 6820 has been illustrated. However, multiple UFS devices may be connected to host 6810 in parallel or in a star, or connected to host 6810 in series or in a chain, and multiple UFS cards may be connected to UFS device 6820 in parallel or in a star, or connected to UFS device 6820 in series or in a chain.

FIG. 16 is a diagram schematically illustrating another example of a data processing system including a memory system according to an embodiment. Fig. 16 is a diagram schematically illustrating a user system 6900 to which a memory system according to an embodiment is applied.

Referring to fig. 16, the user system 6900 may include a user interface 6910, a memory module 6920, an application processor 6930, a network module 6940, and a storage module 6950.

More specifically, the application processor 6930 may drive components (e.g., an Operating System (OS)) included in the user system 6900, and include a controller, an interface, and a graphics engine that control the components included in the user system 6900. The application processor 6930 may be provided as a system on chip (SoC).

The memory module 6920 may serve as a main memory, a working memory, a buffer memory, or a cache memory for the user system 6900. Memory module 6920 may include volatile Random Access Memory (RAM) such as Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate (DDR) SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, or LPDDR3 SDRAM, or non-volatile RAM such as phase change RAM (PRAM), resistive RAM (ReRAM), Magnetoresistive RAM (MRAM), or Ferroelectric RAM (FRAM). For example, the application processor 6930 and the memory module 6920 may be packaged and installed based on package (PoP).

The network module 6940 may communicate with external devices. For example, the network module 6940 may support not only wired communication, but also various wireless communication protocols such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), worldwide interoperability for microwave access (Wimax), Wireless Local Area Network (WLAN), Ultra Wide Band (UWB), bluetooth, wireless display (WI-DI), and the like, so as to communicate with wired/wireless electronic devices or particularly mobile electronic devices. Accordingly, the memory system and the data processing system according to the embodiments of the present invention may be applied to wired/wireless electronic devices. The network module 6940 can be included in the application processor 6930.

The storage module 6950 can store data (e.g., data received from the application processor 6930) and can then send the stored data to the application processor 6930. The storage module 6950 may be implemented by a nonvolatile semiconductor memory device such as a phase-change ram (pram), a magnetic ram (mram), a resistive ram (reram), a NAND flash memory, a NOR flash memory, and a 3D NAND flash memory, and may be provided as a removable storage medium (such as a memory card or an external drive) of the user system 6900. The storage module 6950 may correspond to the memory system 110 described with reference to fig. 1. Further, the storage module 6950 may be implemented as an SSD, eMMC, and UFS as described above with reference to fig. 10-15.

The user interface 6910 may include an interface for inputting data or commands to the application processor 6930 or outputting data to an external device. For example, the user interface 6910 may include user input interfaces such as keyboards, keypads, buttons, touch panels, touch screens, touch pads, touch balls, cameras, microphones, gyroscope sensors, vibration sensors, and piezoelectric elements, and user output interfaces such as Liquid Crystal Displays (LCDs), Organic Light Emitting Diode (OLED) display devices, active matrix OLED (amoled) display devices, LEDs, speakers, and motors.

In addition, when the memory system 110 of fig. 1 is applied to a mobile electronic device of the user system 6900, the application processor 6930 may control the operation of the mobile electronic device, and the network module 6940 may serve as a communication module for controlling wired and/or wireless communication with an external device. The user interface 6910 may display data processed by the processor 6930 on a display and touch module of the mobile electronic device or support functionality to receive data from a touch pad.

Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Cross Reference to Related Applications

This application claims priority to korean patent application No. 10-2018-.