阅读说明：本技术 一种铁电材料可重构场效应晶体管 (Ferroelectric material reconfigurable field effect transistor ) 是由 孙子涵 田明 王昌锋 李相龙 孙亚宾 李小进 石艳玲 廖端泉 曹永峰 于 2019-10-15 设计创作，主要内容包括：本发明公开了一种铁电材料可重构场效应晶体管,该晶体管包括：沟道、设置在沟道一端的漏极及沟道另一个端的源极、设置在沟道外侧的栅极介电缓冲层、包裹在栅极介电缓冲层外侧的铁电材料层、分别设置在源极和漏极端且铁电材料层外侧的控制栅极以及极性栅极、用于控制栅极和极性栅极与源极和漏极电学隔离的内边墙及外边墙。本发明置于栅极介电缓冲层外侧的铁电材料层能在其下方沟道处产生的极化电荷,提高了栅极对沟道的控制能力,增大了相同栅极电压下的开启电压,降低了器件的亚阈值摆幅,减小了器件的静态功耗。栅极介电缓冲层隔离了沟道与铁电材料,阻挡二者的相互扩散并不对铁电材料层的极化特性产生影响。(The invention discloses a ferroelectric material reconfigurable field effect transistor, which comprises: the gate-type transistor comprises a channel, a drain arranged at one end of the channel, a source arranged at the other end of the channel, a gate dielectric buffer layer arranged outside the channel, a ferroelectric material layer wrapped outside the gate dielectric buffer layer, a control gate and a polarity gate which are respectively arranged at the source and the drain end and outside the ferroelectric material layer, and an inner side wall and an outer side wall which are used for electrically isolating the control gate and the polarity gate from the source and the drain. The ferroelectric material layer arranged on the outer side of the gate dielectric buffer layer can generate polarization charges at a channel below the ferroelectric material layer, so that the control capability of the gate on the channel is improved, the starting voltage under the same gate voltage is increased, the subthreshold swing of a device is reduced, and the static power consumption of the device is reduced. The gate dielectric buffer layer isolates the channel from the ferroelectric material, and prevents the mutual diffusion of the channel and the ferroelectric material from influencing the polarization characteristic of the ferroelectric material layer.)

1. A ferroelectric material reconfigurable field effect transistor, the transistor comprising:

a channel (1);

a drain (7) disposed at one end of the channel (1) and a source (8) disposed at the other end of the channel;

a gate dielectric buffer layer (2) disposed outside the channel (1);

a ferroelectric material layer (3) wrapped outside the gate dielectric buffer layer (2);

a control gate (9) and a polarity gate (4) respectively arranged at the source (8) and drain (7) ends and outside the ferroelectric material layer (3);

an inner sidewall (5) and an outer sidewall (6) for electrically isolating the control gate (9), the polarity gate (4) and the source (8), the drain (7);

wherein:

the channel (1) is a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire, a gallium nitride nanowire, an indium phosphide nanowire or a carbon nanotube;

the gate dielectric buffer layer (2) is silicon dioxide, hafnium oxide, silicon oxynitride material or a combined stack of the materials which are deposited and wrapped on the outer side of the channel (1);

the ferroelectric material layer (3) is a perovskite-type ferroelectric, a lithium niobate-type ferroelectric, a tungsten bronze-type ferroelectric or a bismuth-layer-shaped perovskite-structure ferroelectric material which is deposited and wraps the gate dielectric buffer layer (2);

the source electrode (8) and the drain electrode (7) are made of one or a combination of more of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;

the control grid (9) and the polar grid (4) are made of aluminum, copper, silver, gold, polycrystalline silicon, tantalum nitride or titanium nitride which is deposited on the outer side of the ferroelectric material layer and formed by photoetching and etching;

the inner side wall (5) on one side of the source electrode (8) and the drain electrode (7) is made of one or a combination of more of hafnium oxide, silicon nitride, silicon oxynitride and silicon carbonitride;

the outer side wall (6) on one side of the source electrode (8) and the drain electrode (7) is made of one or a combination of silicon dioxide, phosphorosilicate glass, borophosphosilicate glass and air.

2. The ferroelectric-material reconfigurable field effect transistor according to claim 1, characterized in that the dielectric buffer layer (2) is located between the channel (1) and the layer of ferroelectric material (3) and has a length not exceeding the length of the nanowire channel (1).

3. The ferroelectric material reconfigurable field effect transistor of claim 1, wherein the perovskite-type ferroelectric is BaTiO₃(ii) a The lithium niobate type ferroelectric is LiNbO₃、LiTaO₃Or BiFeO₃(ii) a The tungsten bronze type ferroelectric is PbTa₂O₆(ii) a The ferroelectric of the bismuth layered perovskite structure is SrBi₂Ta₂O₉Or Bi₄Ti₃O₁₂。

Technical Field

The invention belongs to digital logic and a memory device in a CMOS (complementary metal-oxide-semiconductor transistor) very large integrated circuit (VLSI), and particularly relates to a field effect transistor with a reconfigurable ferroelectric material.

Background

With the increasing development of society and economy, the size of semiconductor devices is gradually reduced, and especially in recent years, the feature size of semiconductor devices seems to have reached its physical limit. Economic development has not yet stopped requiring semiconductor technology, and more new devices are emerging. One of them is a Reconfigurable Field Effect Transistor (RFET). In such reconfigurable transistor devices, the carrier polarity of the current in the on-state can be changed by controlling the voltage on the gate. That is, one RFET device can realize both the functions of an N-type field effect transistor and a P-type field effect transistor, and the use of the RFET device is expected to reduce the number of transistors when designing a complex circuit.

The RFET structure generally includes a Source (Source), a Drain (Drain), a Control Gate (Control Gate), and a polar Gate (Program G)ate) and a Nanowire (Nanowire) channel capable of forming a schottky barrier with a source and a drain, wherein the source and the drain are made of metal silicide, the channel is made of undoped or low-doped silicon nanowires, and side walls (spacers) are adopted on the outer sides of the silicon nanowires for electrical isolation. The RFET device is cooperatively controlled by a Control Gate (Control Gate) and a polar Gate (ProgramGate). When controlling the gate bias (V)_{Control Gate}) When the negative voltage is increased to the positive voltage and the drain electrode and the polar grid electrode are kept in constant positive bias, the energy band at the channel adjacent to the source end begins to bend downwards gradually, electrons are injected into the nanowire channel through source tunneling, and the device has the characteristic of an N-type field effect transistor; when controlling the gate bias (V)_{Control Gate}) When the voltage is reduced to negative voltage from positive voltage, and the drain electrode and the polar grid electrode are kept in constant negative bias, the energy band at the channel position adjacent to the source end begins to bend upwards gradually, holes are injected into the nanowire channel through source tunneling, and the device is characterized by a P-type field effect transistor.

Due to the special working mode of the RFET, the general structure of the RFET has higher current switching ratio, but the defect of lower on-state current from tunneling current causes that the delay time of an RFET device with the general structure in a combinational logic gate circuit is longer, and the RFET device is difficult to be applied to technologies such as radio frequency, microwave and the like. In addition, for a small-sized device such as an RFET, the integration degree is increased due to the small size, and the power consumption of the device is sacrificed, and the performance of the device operating in a subthreshold region is also sacrificed.

Disclosure of Invention

The invention aims to solve the problems that the existing reconfigurable field effect transistor with a general structure is low in on-state driving current, high in sub-threshold swing amplitude and high in power consumption, and provides a reconfigurable field effect transistor based on a ferroelectric material (negative capacitance effect) in order to improve the starting current of the device, reduce the power consumption of the device and improve the switching performance. The transistor structure can improve the on-state current under the same grid voltage and reduce the sub-threshold swing amplitude of the device, thereby improving the amplification capacity of the device, reducing the power consumption, improving the switching performance of the device, reducing the delay time of the logic gate of the integrated circuit and improving the characteristic frequency of the device.

The specific technical scheme for realizing the purpose of the invention is as follows:

a ferroelectric material reconfigurable field effect transistor, the transistor comprising:

a channel;

a drain electrode arranged at one end of the channel and a source electrode arranged at the other end of the channel;

a gate dielectric buffer layer disposed outside the channel;

the ferroelectric material layer wraps the outer side of the gate dielectric buffer layer;

a control gate and a polarity gate respectively disposed at the source and drain terminals and outside the ferroelectric material layer;

and the inner side wall and the outer side wall are used for electrically isolating the control grid electrode and the polar grid electrode from the source electrode and the drain electrode.

Wherein:

the channel is a silicon nanowire, a germanium-silicon nanowire, a gallium arsenide nanowire, a gallium nitride nanowire, an indium phosphide nanowire or a carbon nanotube;

the gate dielectric buffer layer is silicon dioxide, hafnium oxide, silicon oxynitride material or a combined stack of the materials which are deposited and wrapped on the outer side of the channel;

the ferroelectric material layer is a perovskite-type ferroelectric, a lithium niobate-type ferroelectric, a tungsten bronze-type ferroelectric or a bismuth-layer-shaped perovskite-structure ferroelectric deposited and wrapped on the gate dielectric buffer layer;

the source electrode and the drain electrode can be made of one or a combination of titanium silicide, nickel silicide, cobalt silicide, titanium nitride and tantalum nitride;

the control grid and the polar grid can be made of aluminum, copper, silver, gold, polysilicon, tantalum nitride or titanium nitride deposited on the outer side of the ferroelectric material layer and formed by photoetching and etching;

the inner side wall material on one side of the source electrode and the drain electrode is one or a combination of several of hafnium oxide, silicon nitride, silicon oxynitride and silicon carbonitride;

the outer wall material on one side of the source electrode and the drain electrode is one or a combination of silicon dioxide, phosphorosilicate glass, borophosphosilicate glass and air.

The perovskite type ferroelectric is BaTiO₃(ii) a The lithium niobate type ferroelectric is LiNbO₃、LiTaO₃Or BiFeO₃(ii) a The tungsten bronze type ferroelectric is PbTa₂O₆(ii) a The ferroelectric of the bismuth layered perovskite structure is SrBi₂Ta₂O₉Or Bi₄Ti₃O₁₂。

Because a layer of ferroelectric material is added between the grid dielectric layer and the grid, the ferroelectric material with negative capacitance property can generate polarization under an external electric field, a large amount of polarization charges are induced on the silicon surface, and the surface potential of the silicon is changed. On one hand, polarization charges generated by induction form a positive feedback relation with the grid voltage, so that the effect of voltage amplification is achieved, on the other hand, the change of the silicon surface potential is faster than that of the grid voltage when the grid voltage is smaller, so that the control capability of the grid electrode on a transistor channel is improved. The voltage amplification effect and the improvement of the grid control capability can reduce the sub-threshold swing (SS) at room temperature, thereby reducing the static power consumption of the device. In the expression (1) of SS, V_gsFor gate voltage bias, I_dIn order to provide for a leakage current of the device,

potential of semiconductor silicon, C_sIs a semiconductor silicon capacitor, C_insIs a capacitor of a dielectric layer, and is,the term is about 60mV/decade at room temperature, and it is critical to obtain smaller values of the capacitance term to achieve smaller subthreshold swings. Capacitance C of conventional gate oxide_insIs positive, but the ferroelectric material has a negative capacitance effect. Using negative capacitance (C) of ferroelectric material_ins<0) It is possible to make SS less than 60mV/decade at room temperature. When the ferroelectric material is in direct contact with the substrate silicon, elemental diffusion occurs between them to generate a large number of interface states, so that the interface characteristics between the ferroelectric and the silicon substrate are deteriorated. High-k insulation between ferroelectric material and substrate siliconThe material of the layer can be used as the structure of the buffer layer to block the diffusion of atoms, and simultaneously, the negative capacitance characteristic of the ferroelectric layer can not be influenced.

Because the addition of the ferroelectric material plays a role in voltage amplification, the RFET adopting the ferroelectric material shows higher drain current under the same gate voltage, and higher gain is provided for the operation of the RFET device. Compared with the reconfigurable field effect transistor with a common structure, the switching performance and the control capability of grid voltage to current of the reconfigurable field effect transistor made of the ferroelectric material are enhanced to a certain extent. When the RFET made of the ferroelectric material is adopted, the power consumption of a device can be effectively reduced, the logic delay time in a digital integrated circuit is reduced, and the working frequency in an analog integrated circuit is improved.

Drawings

FIG. 1 is a cross-sectional view of the present invention taken along the direction of the channel;

FIG. 2 is a cross-sectional view of the present invention at the location of the control gate, perpendicular to the channel direction;

FIG. 3 is a cross-sectional view of the present invention at the location of a sidewall of the source, perpendicular to the channel direction;

FIG. 4 is a graph of transfer characteristics characterizing the N-type state according to the present invention;

FIG. 5 is a graph of the transfer characteristics of the present invention characterizing the P-type state;

FIG. 6 is a flow chart of the present invention.

Detailed Description

The invention is described in detail below with reference to the figures and examples.

Referring to fig. 1-3, the present invention includes a nanowire channel 1, a gate dielectric buffer layer 2, a ferroelectric material layer 3, a polar gate 4, a drain, a source-side inner wall 5, a drain, a source-side outer wall 6, a drain 7, a source 8, and a control gate 9; the inner side wall 5 at one side of the drain and the source electrode is made of different materials from the outer side wall 6 at one side of the drain and the source electrode.

A field effect transistor based on a ferroelectric material reconfigurable structure comprises a central nanowire channel 1, a gate dielectric buffer layer 2 wrapped on the outer side of the channel 1, a source electrode 8 at one end of the channel 1, a drain electrode 7 at the other end of the channel 1, a ferroelectric material layer 3 wrapped on the outer side of the gate dielectric buffer layer 2, a control gate electrode 9 and a polarity gate electrode 4 respectively wrapped on two ends of the ferroelectric material layer 3, and an inner side wall 5 and an outer side wall 6 which are arranged between the source electrode 8 and the control gate electrode 9 and between the drain electrode 4 and the polarity gate electrode 4.

The channel 1 is made of silicon nanowires, germanium nanowires, silicon germanium nanowires, gallium arsenide nanowires, gallium nitride nanowires, indium phosphide nanowires or carbon nanotubes; the gate dielectric buffer layer 2 is silicon dioxide, hafnium oxide, silicon oxynitride material or a combination stack of the materials which are deposited and wrapped on the outer side of the channel 1; the ferroelectric material layer 3 is a perovskite-type ferroelectric, a lithium niobate-type ferroelectric, a tungsten bronze-type ferroelectric or a bismuth-layer-shaped perovskite-structure ferroelectric deposited and wrapped on the outer side of the channel 1, and the ferroelectric material layer 3 deposited and wrapped on the outer side of the channel 1; the source electrode 8 and the drain electrode 7 can be made of titanium silicide, nickel silicide, cobalt silicide, titanium nitride, tantalum nitride or a combination of the above materials; the control grid 9 and the polar grid 4 can be made of aluminum, copper, silver, gold, polysilicon, tantalum nitride and titanium nitride deposited on the outer side of the ferroelectric layer and formed by photoetching and etching; the inner side wall 5 on one side of the source (drain) electrode is made of hafnium oxide, silicon nitride, silicon oxynitride, silicon carbonitride or a combination of the materials; the outer wall 6 on the source (drain) side is made of silicon dioxide, phosphorosilicate glass, borophosphosilicate glass, air or a combination of the materials.

The ferroelectric material has a negative capacitance due to its hysteretic nature. Under the action of an applied electric field, the polarization of the ferroelectric material is reversed in two opposite thermodynamic stable states. As the reconfigurable field effect transistor based on the negative capacitance property of the ferroelectric material utilizes the ferroelectric film material to replace the traditional MOS transistor gate oxide, the ferroelectric film material generates polarization under the action of an external electric field, a large amount of polarization charges are induced on two ends (namely the silicon surface) of the ferroelectric material, and the surface potential of silicon is changed. On the one hand induced polarizationThe charge and the grid voltage form a positive feedback relation, thereby playing a role of 'voltage amplification', and on the other hand, the potential change of the silicon surface is faster than the change of the grid voltage when the grid voltage is smaller, thereby improving the control capability of the grid electrode on the channel of the transistor. The voltage amplification effect and the improvement of the grid control capability can reduce the sub-threshold swing (SS) at room temperature, thereby reducing the static power consumption of the device. In the expression (1) of the SS,

the term is about 60mV/decade at room temperature, and it is critical to obtain smaller values of the capacitance term to achieve smaller subthreshold swings. Capacitance C of conventional gate oxide_insIs positive, but the ferroelectric material has a negative capacitance effect. Using negative capacitance (C) of ferroelectric material_ins<0) It is possible to make SS less than 60mV/decade at room temperature. For the structure using the ferroelectric material to directly replace the gate oxide, since the ferroelectric material and the substrate silicon are in direct contact, element diffusion occurs between them to generate a large number of interface states, so that the interface characteristics between the ferroelectric and the silicon substrate are deteriorated. The high-k insulating layer material between the ferroelectric material and the substrate silicon can be used as a buffer layer structure to block the diffusion of atoms, and meanwhile, the negative capacitance characteristic of the ferroelectric layer cannot be influenced.

Referring to fig. 4, it can be seen from the N-type electrical characteristics exhibited by the reconfigurable field effect transistor based on the negative capacitance characteristics of the ferroelectric material of the present invention that the on-state current of the reconfigurable field effect transistor is improved compared to that of the reconfigurable field effect transistor of a general structure. When the RFET adopts a general structure and is not added with the ferroelectric thin film layer, the on-state current of the RFET is 1.954 multiplied by 10 when the RFET shows N-type electrical characteristics¹μ A/μm, the minimum holding voltage of the on-state current is 1V, and the subthreshold swing SS is 97.1 mV/decade; RFET adopts the ferroelectric material (negative capacitance) structure of the invention, and when the ferroelectric layer is added between the grid and the grid oxide layer, the RFET shows N-type electrical characteristics and the on-state current isIdentity value (I)_ds＝1.954×10¹μ a/μm), the gate voltage is 0.89V, and the subthreshold swing SS is 87.7 mV/decade. Referring to fig. 5, it can be seen from the P-type electrical characteristics exhibited by the reconfigurable field effect transistor based on the negative capacitance characteristics of the ferroelectric material of the present invention that when the RFET adopts a general structure and does not incorporate the ferroelectric thin film layer, the on-state current is 2.0092 × 10 when it exhibits the P-type electrical characteristics¹μ A/μm, the minimum holding voltage under the on-state current is-1V, and the subthreshold swing SS is 75.3 mV/decade; the RFET adopts the structure of the invention, when a ferroelectric layer is added between the grid and the grid oxide layer, the RFET presents P-type electrical characteristics, when the on-state current is the same value, the grid voltage is-0.93V, and the subthreshold swing SS is 68.5 mV/decade. Therefore, the addition of the ferroelectric material plays a role in voltage amplification, and the RFET adopting the ferroelectric material shows higher drain current under the same gate voltage, so that higher gain is provided for the RFET device to work in an N-type or P-type electrical state. Compared with the reconfigurable field effect transistor with a common structure, the switching performance and the control capability of grid voltage to current of the reconfigurable field effect transistor made of the ferroelectric material are enhanced to a certain extent. When the ferroelectric material RFET is adopted, the logic delay time in a digital integrated circuit can be reduced, and the working frequency in an analog integrated circuit can be improved.

Referring to fig. 6, the manufacturing process of the present invention:

in the figure (a), a nanowire channel 1 is prepared;

in the figure (b), preparing a metal silicide source electrode 8 and a drain electrode 7 and annealing;

in the figure (c), a high-k insulating material buffer layer (a gate oxide dielectric layer) 2 grows, and photoetching and etching are carried out;

in the figure (d), a ferroelectric thin film layer 3 is grown, and photoetching and etching are carried out;

in the figure (e), two metal gate electrodes 4, 9 are formed by deposition, photolithography and etching;

in the figure (f), inner and outer sidewalls 5, 6 are deposited.

After the device is prepared, the control grid, the polar grid, the source electrode and the drain electrode are led out through the tungsten plug, so that the function of an electrical switch can be realized; the four deposits are leveled by chemical mechanical polishing, and the devices of the invention are connected together by metal connecting wires by adopting a post Damascus process of a CMOS (complementary metal oxide semiconductor) super-large scale circuit.