阅读说明：本技术 能改善反向恢复特性的屏蔽栅mos结构及其制作方法 (Shielding grid MOS structure capable of improving reverse recovery characteristic and manufacturing method thereof ) 是由 吴宗宪 陈彦豪 于 2019-11-07 设计创作，主要内容包括：本发明涉及一种能改善反向恢复特性的屏蔽栅MOS结构及其制作方法,它包括第一导电类型重掺杂衬底、第一导电类型外延层、第二导电类型上体区、第一导电类型源极区、绝缘介质层、源极金属层、源极接触孔、源极接触金属、第二导电类型下体区、栅氧化层、栅极导电多晶硅与屏蔽栅。本发明通过在屏蔽栅两侧设置阶梯形氧化层和沟槽底层注入第二导电类型体区,可降低电场峰值分布,进而提高器件耐压；与传统屏蔽栅器件结构相比,本发明的器件具有更低的导通电阻、更低的输入和输出寄生电容值、更低的反向恢复电流峰值和恢复软度特性；本发明的器件可减小芯片面积,降低芯片成本。(The invention relates to a shielded gate MOS structure capable of improving reverse recovery characteristics and a manufacturing method thereof. According to the invention, the stepped oxide layers are arranged on the two sides of the shielding grid, and the second conductive type body region is injected into the bottom layer of the groove, so that the electric field peak value distribution can be reduced, and the withstand voltage of the device can be further improved; compared with the traditional shielding grid device structure, the device has the characteristics of lower on-resistance, lower input and output parasitic capacitance values, lower reverse recovery current peak value and recovery softness; the device of the invention can reduce the area of the chip and the cost of the chip.)

1. A shielding grid MOS structure capable of improving reverse recovery characteristics comprises a cellular region and a terminal protection region, wherein the cellular region is positioned in the central region of a device and is formed by connecting a plurality of MOS device unit bodies in parallel; the method is characterized in that:

the MOS device unit body comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped substrate (1) and a first conductive type epitaxial layer (2) fixed on the upper surface of the first conductive type heavily doped substrate (1), a second conductive type upper body region (13) is arranged on the upper surface of the first conductive type epitaxial layer (2), a first conductive type source region (14) is arranged on the upper surface of the second conductive type upper body region (13), an insulating medium layer (15) is arranged on the upper surface of the first conductive type source region (14), a source metal layer (17) is arranged on the upper surface of the insulating medium layer (15), a source contact hole (11) is arranged on the outer side of the insulating medium layer (15) and the first conductive type source region (14), a source contact metal (16) is filled in the source contact hole (11), and the upper end of the source contact metal (16) is connected with the source metal layer (17), the lower end of the source contact metal (16) is connected with the second conductive type upper body region (13);

a gate oxide groove (3) is formed in the lower part of the upper surface of the first conductive type source electrode region (14), in the direction from top to bottom, the gate oxide groove (3) sequentially penetrates through the first conductive type source electrode region (14), the second conductive type upper body region (13), the first conductive type epitaxial layer (2) and the second conductive type lower body region (4), the lower end of the gate oxide groove (3) is located in the second conductive type lower body region (4), a gate oxide layer (5) is filled in the gate oxide groove (3), a spherical second conductive type lower body region (4) is arranged outside the lower end of the gate oxide layer (5), and the gate oxide layer (5) is surrounded by the second conductive type lower body region (4);

follow grid conductive polysilicon groove (10) have been seted up downwards to the upper surface of gate oxide (5), are filled up grid conductive polysilicon (12) in grid conductive polysilicon groove (10), are equipped with shielding grid cavity (6) that are the notch cuttype in grid conductive polysilicon (12) below grid gate oxide (5), and on the direction from last down, the internal diameter of shielding grid cavity (6) is and reduces the setting step by step, fills up shielding grid (9) in shielding grid cavity (6).

2. The shielded gate MOS structure with improved reverse recovery characteristics as claimed in claim 1, wherein the height of each step in said shielded gate cavity (6) is 1 ~ 3 um.

3. The shielded gate MOS structure with improved reverse recovery characteristics as claimed in claim 1, wherein the gate oxide layer (5) between said gate conductive polysilicon (12) and said shielded gate (9) has a thickness of 1000A ~ 5000A.

4. The shielded gate MOS structure with improved reverse recovery characteristics as claimed in claim 1, wherein said gate oxide trench (3) has a depth of 4 ~ 10 um.

5. The shielded gate MOS structure having improved reverse recovery characteristics as claimed in claim 1, wherein: and when the first conductive type heavily doped substrate (1), the first conductive type epitaxial layer (2) and the first conductive type source region (14) are N-type, the second conductive type lower body region (4) and the second conductive type upper body region (13) are P-type.

6. The shielded gate MOS structure having improved reverse recovery characteristics as claimed in claim 1, wherein: and when the first conductive type heavily doped substrate (1), the first conductive type epitaxial layer (2) and the first conductive type source region (14) are of a P type, the second conductive type lower body region (4) and the second conductive type upper body region (13) are of an N type.

7. A method for manufacturing a shielded gate MOS structure capable of improving reverse recovery characteristics comprises the following steps:

providing a first conductive type heavily doped substrate (1), and growing a first conductive type epitaxial layer (2) on the upper surface of the first conductive type heavily doped substrate (1);

etching downwards from the upper surface of the first conductive type epitaxial layer (2) through the shielding of the graphical photoetching plate to form a gate oxide groove (3);

injecting a second conductive type by adopting an ion injection mode, forming a spherical lower body area (4) of the second conductive type at the bottom of the gate oxide groove (3) after the well is pushed, and surrounding the gate oxide groove (3) by the lower body area (4) of the second conductive type;

adopting thermal oxidation or HDP technology to grow an oxidation material in the gate oxide layer groove (3), wherein the oxidation material fills the gate oxide layer groove (3) to form a gate oxide layer (5);

etching the gate oxide layer (5) through shielding of the graphical photoetching plate, and forming a stepped shielding gate cavity (6) in the gate oxide layer (5);

depositing polycrystalline silicon on the upper surface of the first conductive type epitaxial layer (2) and in the shielding grid cavity (6), etching back the polycrystalline silicon, and only keeping the polycrystalline silicon in the step-shaped groove to form a shielding grid (9);

etching the gate oxide layers (5) on two sides above the shielding gate (9) by adopting a wet etching process, controlling the etching depth, and removing the gate oxide layers (5) above the shielding gate (9);

step eight, adopting a thermal oxidation process to re-grow a gate oxide layer (5) in the etching cavity above the shielding gate (9), wherein the etching cavity is filled with the gate oxide layer (5);

step nine, etching the gate oxide layer (5) above the shielding gate (9) through shielding of the graphical photoetching plate to form a gate conductive polysilicon groove (10);

step ten, depositing polycrystalline silicon in the grid conductive polycrystalline silicon groove (10), wherein the polycrystalline silicon fills the grid conductive polycrystalline silicon groove (10) to form grid conductive polycrystalline silicon (12);

step eleven, under the shielding of the graphical photoetching plate, injecting second conductive type impurities into the upper surface of the first conductive type epitaxial layer (2) on the outer side of the gate oxide layer groove (3) to form a second conductive type upper body area (13); under the shielding of a graphical photoetching plate, injecting first conductive type impurities into the upper surface of the second conductive type upper body region (13), forming a first conductive type source region (14) after well pushing, and then etching the first conductive type source region (14) to form a source contact hole (11);

and a twelfth step of depositing an insulating dielectric layer (15) on the upper surface of the first conductive type source region (14), the upper surface of the gate oxide layer (5) and the upper surface of the gate conductive polysilicon (12), filling metal in the upper surface of the insulating dielectric layer (15) and the source contact hole (11), and performing dry etching on the metal to form a source metal layer (17) and a source contact metal (16).

8. The method of claim 7, wherein the step of forming the shielded gate MOS structure with improved reverse recovery comprises: in the fourth step, the gate oxide layer (5) grows on the upper surface of the first conductive type epitaxial layer (2) and in the gate oxide layer groove (3), the gate oxide layer (5) on the upper surface of the first conductive type epitaxial layer (2) is removed through wet etching, and only the gate oxide layer (5) in the gate oxide layer groove (3) is reserved.

9. The method of claim 7, wherein the step of forming the shielded gate MOS structure with improved reverse recovery comprises: and in the step eight, a gate oxide layer (5) is re-grown on the upper surface of the first conduction type epitaxial layer (2) and in the etching cavity above the shielding gate (9).

10. The method of claim 7, wherein the step of forming the shielded gate MOS structure with improved reverse recovery comprises: in the step ten, firstly, polycrystalline silicon is deposited in the gate oxide layer (5) and the gate conductive polycrystalline silicon groove (10) on the upper surface of the first conductive type epitaxial layer (2), and then the polycrystalline silicon and the oxide layer on the gate oxide layer (5) on the upper surface of the first conductive type epitaxial layer (2) are etched, so that the upper surface of the first conductive type epitaxial layer (2) is exposed.

Technical Field

The invention relates to a shielding grid MOS structure capable of improving reverse recovery characteristics and a manufacturing method thereof, belonging to the technical field of MOS.

Background

Trench MOS (metal-oxide semiconductor field effect transistor) devices are increasingly used in high-current dc-to-dc power conversion or synchronous rectification circuits, such as green power, electric vehicles, and battery management. However, the trench MOS device is also faced with the energy efficiency problem due to the simultaneous increase of on-resistance and gate charge while pursuing miniaturization.

Disclosure of Invention

One of the objectives of the present invention is to overcome the deficiencies in the prior art, and to provide a shielded gate MOS structure that can improve the device withstand voltage, improve the reverse recovery characteristics, and have lower on-resistance, input and output parasitic capacitance values, reverse recovery current peak value, and recovery softness characteristics.

Another object of the present invention is to provide a method for fabricating a shielded gate MOS structure with improved reverse recovery characteristics.

According to the technical scheme provided by the invention, the shielding grid MOS structure of the stepped oxide layer capable of improving the reverse recovery characteristic comprises a cellular area and a terminal protection area, wherein the cellular area is positioned in the central area of a device and is formed by connecting a plurality of MOS device unit bodies in parallel;

the MOS device unit body comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped substrate and a first conductive type epitaxial layer fixed on the upper surface of the first conductive type heavily doped substrate, a second conductive type upper body region is arranged on the upper surface of the first conductive type epitaxial layer, a first conductive type source region is arranged on the upper surface of the second conductive type upper body region, an insulating medium layer is arranged on the upper surface of the first conductive type source region, a source metal layer is arranged on the upper surface of the insulating medium layer, a source contact hole is arranged on the outer side of the insulating medium layer and the first conductive type source region, source contact metal is filled in the source contact hole, the upper end of the source contact metal is connected with the source metal layer, and the lower end of the source contact metal is connected with the second conductive type upper body region;

a gate oxide groove is formed in the lower surface of the first conduction type source electrode region, and sequentially penetrates through the first conduction type source electrode region, the second conduction type upper body region, the first conduction type epitaxial layer and the second conduction type lower body region in the direction from top to bottom;

follow the upper surface of gate oxide has seted up the electrically conductive polycrystalline silicon groove of grid downwards, fills up the electrically conductive polycrystalline silicon of grid in the electrically conductive polycrystalline silicon groove of grid, is equipped with the shielding bars cavity that is the notch cuttype in the gate oxide of the electrically conductive polycrystalline silicon of grid below, and on from last direction down, the internal diameter of shielding bars cavity is and dwindles the setting step by step, fills up the shielding bars in the shielding bars cavity.

Further, the height of each step in the shield grid cavity is 1 ~ 3 um.

Further, the thickness of the gate oxide layer between the gate conductive polysilicon and the shield gate is 1000A ~ 5000A.

Further, the depth of the gate oxide layer groove is 4 ~ 10 um.

Further, when the first conductive type heavily doped substrate, the first conductive type epitaxial layer and the first conductive type source region are N-type, the second conductive type lower body region and the second conductive type upper body region are P-type.

Further, when the first conductive type heavily doped substrate, the first conductive type epitaxial layer and the first conductive type source region are P-type, the second conductive type lower body region and the second conductive type upper body region are N-type.

A method for manufacturing a shielded gate MOS structure capable of improving reverse recovery characteristics comprises the following steps:

providing a first conductive type heavily doped substrate, and growing a first conductive type epitaxial layer on the upper surface of the first conductive type heavily doped substrate;

etching downwards from the upper surface of the first conductive type epitaxial layer through the shielding of the graphical photoetching plate to form a gate oxide layer groove;

injecting a second conductive type by adopting an ion injection mode, forming a spherical lower body area of the second conductive type at the bottom of the gate oxide groove after the drive-in and surrounding the gate oxide groove by the lower body area of the second conductive type;

growing an oxidation material in the gate oxide layer groove by adopting a thermal oxidation or HDP process, wherein the oxidation material fills the gate oxide layer groove to form a gate oxide layer;

etching the gate oxide layer through shielding of the graphical photoetching plate, and forming a stepped shielding gate cavity in the gate oxide layer;

depositing polycrystalline silicon on the upper surface of the first conductive type epitaxial layer and in the cavity of the shielding gate, back-etching the polycrystalline silicon, and only reserving the polycrystalline silicon in the step-shaped groove to form the shielding gate;

etching the gate oxide layers on two sides above the shielding gate by adopting a wet etching process, controlling the etching depth and removing the gate oxide layers above the shielding gate;

step eight, adopting a thermal oxidation process to re-grow a gate oxide layer in the etching cavity above the shielding gate, wherein the etching cavity is filled with the gate oxide layer;

etching the gate oxide layer above the shielding gate through the shielding of the graphical photoetching plate to form a gate conductive polysilicon groove;

step ten, depositing polycrystalline silicon in the grid conductive polycrystalline silicon groove, wherein the polycrystalline silicon fills the grid conductive polycrystalline silicon groove to form grid conductive polycrystalline silicon;

step eleven, under the shielding of the graphical photoetching plate, injecting second conductive type impurities into the upper surface of the first conductive type epitaxial layer on the outer side of the gate oxide layer to form a second conductive type upper body region; under the shielding of the graphical photoetching plate, injecting first conductive type impurities into the upper surface of the second conductive type upper body region, pushing a well to form a first conductive type source region, and etching the first conductive type source region to form a source contact hole;

and step twelve, depositing an insulating medium layer on the upper surface of the first conductive type source electrode region, the upper surface of the gate oxide layer and the upper surface of the grid conductive polycrystalline silicon, filling metal in the upper surface of the insulating medium layer and the source contact hole, and performing dry etching on the metal to form a source metal layer and source contact metal.

Further, in the fourth step, gate oxide layers are grown on the upper surface of the first conductive type epitaxial layer and in the gate oxide layer groove, the gate oxide layer on the upper surface of the first conductive type epitaxial layer is removed through wet etching, and only the gate oxide layer in the gate oxide layer groove is reserved.

Further, in the eighth step, a gate oxide layer is re-grown in the etching cavity above the upper surface of the first conductivity type epitaxial layer and the shield gate.

Further, in the step ten, polysilicon is firstly deposited in the gate oxide layer and the gate conductive polysilicon groove on the upper surface of the first conductive type epitaxial layer, and then the polysilicon and the oxide layer on the gate oxide layer on the upper surface of the first conductive type epitaxial layer are etched, so that the upper surface of the first conductive type epitaxial layer is exposed.

The invention has the following advantages:

1. according to the invention, the stepped oxide layers are arranged on the two sides of the shielding grid, and the second conductive type body region is injected into the bottom layer of the groove, so that the electric field peak value distribution can be reduced, and the withstand voltage of the device can be further improved;

2. compared with the traditional shielding grid device structure, the device has lower on-resistance;

3. compared with the traditional shielding grid device structure, the device has lower input and output parasitic capacitance values;

4. compared with the traditional shielding grid device structure, the device has the characteristics of lower reverse recovery current peak value and recovery softness;

5. compared with the traditional shielding grid device, the device can reduce the area of a chip and reduce the cost of the chip.

Drawings

FIG. 1 is a block diagram of a first step of the present invention.

FIG. 2 is a block diagram of step two of the present invention.

FIG. 3 is a block diagram of step three of the present invention.

FIG. 4 is a block diagram of step four of the present invention.

Fig. 5 is a block diagram of step five of the present invention.

Fig. 6 is a block diagram of step six of the present invention.

Fig. 7 is a block diagram of step seven of the present invention.

Fig. 8 is a block diagram of step eight of the present invention.

Fig. 9 is a block diagram of step nine of the present invention.

Fig. 10 is a block diagram of step ten of the present invention.

FIG. 11 is a block diagram of step eleven of the present invention.

FIG. 12 is a block diagram of step twelve of the present invention.

Fig. 13 is a schematic cross-sectional view of a conventional shielded gate MOS cell.

Fig. 14 is a schematic cross-sectional view of a prior art stepped shield gate MOS cell body.

Detailed Description

The present invention will be further described with reference to the following specific examples.

The invention can improve the shielding grid MOS structure of the step type oxide layer of the reverse recovery characteristic, it includes cellular area and terminal protection area, cellular area locate at center area of the device, cellular area connect in parallel by several MOS device unit bodies;

the MOS device unit body comprises a semiconductor substrate, the semiconductor substrate comprises a first conductive type heavily doped substrate 1 and a first conductive type epitaxial layer 2 fixed on the upper surface of the first conductive type heavily doped substrate 1, a second conductivity type upper body region 13 is provided on the upper surface of the first conductivity type epitaxial layer 2, a first conductivity type source region 14 is provided on the upper surface of the second conductivity type upper body region 13, an insulating dielectric layer 15 is provided on the upper surface of the first conductive type source region 14, a source metal layer 17 is provided on the upper surface of the insulating dielectric layer 15, a source contact hole 11 is formed outside the insulating dielectric layer 15 and the first conductive type source region 14, source contact metal 16 is filled in the source contact hole 11, the upper end of the source contact metal 16 is connected with a source metal layer 17, and the lower end of the source contact metal 16 is connected with the second conductive type upper body region 13;

a gate oxide groove 3 is formed downwards from the upper surface of the first conductive type source electrode region 14, in the direction from top to bottom, the gate oxide groove 3 sequentially penetrates through the first conductive type source electrode region 14, the second conductive type upper body region 13, the first conductive type epitaxial layer 2 and the second conductive type lower body region 4, the lower end of the gate oxide groove 3 is positioned in the second conductive type body region 4, the gate oxide 5 is filled in the gate oxide groove 3, a spherical second conductive type lower body region 4 is arranged outside the lower end of the gate oxide 5, and the second conductive type lower body region 4 surrounds the gate oxide 5;

follow the upper surface of gate oxide 5 has seted up the electrically conductive polycrystalline silicon recess of grid 10 downwards, is filled up the electrically conductive polycrystalline silicon 12 of grid in the electrically conductive polycrystalline silicon recess 10 of grid, is equipped with the shielding grid cavity 6 that is the notch cuttype in gate oxide 5 of the electrically conductive polycrystalline silicon 12 below of grid, and on from last direction down, the internal diameter of shielding grid cavity 6 is the reduction setting step by step, is filled up shielding grid 9 in shielding grid cavity 6.

The height of each step in the shield grid cavity 6 is 1 ~ 3 um.

The thickness of the gate oxide layer 5 between the gate conductive polysilicon 12 and the shield gate 9 is 1000A ~ 5000A.

The depth of the gate oxide layer groove 3 is 4 ~ 10 um.

When the first conductive type heavily doped substrate 1, the first conductive type epitaxial layer 2 and the first conductive type source region 14 are N-type, the second conductive type lower body region 4 and the second conductive type upper body region 13 are P-type.

When the first conductive type heavily doped substrate 1, the first conductive type epitaxial layer 2 and the first conductive type source region 14 are P-type, the second conductive type lower body region 4 and the second conductive type upper body region 13 are N-type.

In order to further achieve the above technical object, the present invention further provides a method for manufacturing a shielded gate MOS structure having a step oxide layer with improved reverse recovery characteristics, comprising the steps of:

providing a first conductive type heavily doped substrate 1, and growing a first conductive type epitaxial layer 2 on the upper surface of the first conductive type heavily doped substrate 1;

etching downwards from the upper surface of the first conductive type epitaxial layer 2 through the shielding of the graphical photoetching plate to form a gate oxide groove 3;

injecting a second conductive type in an ion injection mode, forming a spherical lower body area 4 of the second conductive type at the bottom of the gate oxide groove 3 after trap pushing, and enabling the lower body area 4 of the second conductive type to surround the gate oxide groove 3;

adopting thermal oxidation or HDP process to grow oxide material in the gate oxide layer groove 3, wherein the oxide material fills the gate oxide layer groove 3 to form a gate oxide layer 5;

etching the gate oxide layer 5 through shielding of the graphical photoetching plate, and forming a stepped shielding gate cavity 6 in the gate oxide layer 5;

depositing polycrystalline silicon on the upper surface of the first conductive type epitaxial layer 2 and in the shielding grid cavity 6, back-etching the polycrystalline silicon, and only keeping the polycrystalline silicon in the step-shaped groove to form a shielding grid 9;

etching the gate oxide layers 5 on two sides above the shielding gate 9 by adopting a wet etching process, controlling the etching depth, and removing the gate oxide layers 5 above the shielding gate 9;

step eight, adopting a thermal oxidation process to re-grow the gate oxide layer 5 in the etching cavity above the shielding gate 9, wherein the etching cavity is filled with the gate oxide layer 5;

etching the gate oxide layer 5 above the shielding gate 9 through shielding of the graphical photoetching plate to form a gate conductive polysilicon groove 10;

step ten, depositing polycrystalline silicon in the grid conductive polycrystalline silicon groove 10, wherein the polycrystalline silicon fills the grid conductive polycrystalline silicon groove 10 to form grid conductive polycrystalline silicon 12;

step eleven, under the shielding of the graphical photoetching plate, injecting second conductive type impurities into the upper surface of the first conductive type epitaxial layer 2 at the outer side of the gate oxide layer 5 to form a second conductive type upper body region 13; under the shielding of the patterned photoetching plate, injecting first conductive type impurities into the upper surface of the second conductive type upper body region 13 to form a first conductive type source region 14, and then etching the first conductive type source region 14 to form a source contact hole 11;

and a twelfth step of depositing an insulating medium layer 15 on the upper surface of the first conductive type source region 14, the upper surface of the gate oxide layer 5 and the upper surface of the gate conductive polysilicon 12, filling metal in the upper surface of the insulating medium layer 15 and the source contact hole 11, and performing dry etching on the metal to form a source metal layer 17 and a source contact metal 16.

Further, in the fourth step, the gate oxide layer 5 grows on the upper surface of the first conductive type epitaxial layer 2 and in the gate oxide layer groove 3, the gate oxide layer 5 on the upper surface of the first conductive type epitaxial layer 2 is removed through wet etching, and only the gate oxide layer 5 in the gate oxide layer groove 3 is reserved.

Further, in the eighth step, the gate oxide layer 5 is re-grown in the etching cavity above the upper surface of the first conductivity type epitaxial layer 2 and the shielding gate 9.

Further, in the step ten, polysilicon is firstly deposited in the gate oxide layer 5 and the gate conductive polysilicon groove 10 on the upper surface of the first conductive type epitaxial layer 2, and then the polysilicon and the oxide layer on the gate oxide layer 5 on the upper surface of the first conductive type epitaxial layer 2 are etched, so that the upper surface of the first conductive type epitaxial layer 2 is exposed.

Compared with the traditional shielded gate structure (shown in FIG. 13) and the traditional stepped oxide layer shielded gate structure (shown in FIG. 14), the device has higher breakdown voltage when withstanding voltage. Because the stepped gate oxide layer 5 is adopted outside the existing shielded gate structure, and the spherical second conductive type lower body region 4 is surrounded outside the stepped oxide layer, the electric field distribution formed by the regions among the second conductive type upper body region 13, the second conductive type lower body region 4 and the bottom of the gate oxide layer groove 3 can be greatly optimized, so that the electric field distribution of the peak electric field on the surface of the device can be more smooth and uniform, and the peak position of the device is not easy to be punctured when the device is in voltage resistance, thereby effectively improving the breakdown voltage of the device;

after the device is conducted, compared with the traditional shielding grid structure and the traditional stepped oxide layer shielding grid structure, under the condition of the same withstand voltage, the device can adopt the first conductive type epitaxial layer 2 with higher doping, so that the resistance of the first conductive type epitaxial layer 2 is reduced, and the on-resistance of the device is reduced;

after the device is conducted, compared with the traditional shielding gate structure and the traditional stepped oxide layer shielding gate structure, the spherical lower body region 4 of the second conductive type is injected between the bottom of the stepped gate oxide layer 5 and the epitaxial layer 2 of the first conductive type, and the structure of the spherical lower body region 4 of the second conductive type P is optimized, so that the device can improve the reverse recovery characteristic, particularly reduce the peak value of reverse current, and better recover the softness, thereby reducing the switching loss of the device; based on the above, the device has smaller chip area and smaller switching loss, and the cost performance of the device is improved.

The invention is divided into two layers of structures in the groove of the conventional groove MOS device, the upper layer is a grid electrode and a grid oxide layer of conventional conductive polysilicon, the lower layer is a shielding grid 9, and stepped grid oxide layers 5 are adopted at two sides of the shielding grid 9, so that the electric field peak value near the grid oxide groove 3 can be reduced, the voltage endurance capability of the device is improved, the on-resistance of the device can be reduced, the input and output parasitic capacitance of the device can be reduced, and the switching characteristic of the device can be optimized. Meanwhile, the step-type gate oxide layer 5 is further protected by surrounding a spherical second conductive type lower body region 4 outside the step-type gate oxide layer 5, and when the device operates in a reverse bias state, reverse charges can be optimized, the reverse recovery current peak value and the recovery softness are effectively reduced, and the reverse switching loss is reduced.