阅读说明：本技术 薄膜晶体管及其制造方法 (Thin film transistor and method of manufacturing the same ) 是由 翟玉浩 于 2019-09-16 设计创作，主要内容包括：本申请提供一种薄膜晶体管及其制备方法,所述薄膜晶体管包括基板、栅极、栅极绝缘层、半导体单元、源极和漏极。所述栅极、栅极绝缘层、半导体单元、源极和漏极依次设置于所述基板上,所述源极覆盖部分所述栅极绝缘层和所述半导体单元的一端,所述源极包括若干第一通槽,所述漏极包括若干第二通槽,所述第一通槽和所述第二通槽贯穿所述漏极和所述漏极以暴露所述栅极绝缘层和所述半导体单元。在所述薄膜晶体管中的源极和漏极中设置若干所述通槽,减少了器件的裂纹,进而提高了器件的性能。(The application provides a thin film transistor and a preparation method thereof. The grid, the grid insulating layer, the semiconductor unit, the source electrode and the drain electrode are sequentially arranged on the substrate, the source electrode covers a part of the grid insulating layer and one end of the semiconductor unit, the source electrode comprises a plurality of first through grooves, the drain electrode comprises a plurality of second through grooves, and the first through grooves and the second through grooves penetrate through the drain electrode and the drain electrode to expose the grid insulating layer and the semiconductor unit. The through grooves are formed in the source electrode and the drain electrode of the thin film transistor, so that cracks of the device are reduced, and the performance of the device is improved.)

1. A thin film transistor, comprising:

a substrate;

a gate disposed on the substrate;

a gate insulating layer covering the substrate and the gate electrode;

the semiconductor unit is arranged on the grid insulating layer and comprises a first semiconductor region, a second semiconductor region and a third semiconductor region, and the first semiconductor region and the third semiconductor region of the semiconductor unit are positioned at two ends of the second semiconductor region;

a source electrode covering a portion of the gate insulating layer and the first semiconductor region of the semiconductor unit, the source electrode including a first region and a second region, the first region of the source electrode being electrically connected to the second region, the first region of the source electrode including a plurality of first through-trenches and/or first through-holes penetrating the first region of the source electrode to expose the gate insulating layer and the semiconductor unit; and

the drain electrode covers a part of the gate insulating layer and the first semiconductor region of the semiconductor unit, the drain electrode comprises a third region and a fourth region, the third region of the drain electrode is electrically connected with the fourth region, the third region of the drain electrode comprises a plurality of second through grooves and/or second through holes, and the second through grooves and/or the second through holes penetrate through the third region of the drain electrode to expose the gate insulating layer and the semiconductor unit.

2. The thin film transistor of claim 1, wherein the width of the first plurality of through trenches and/or first vias is between 1 micron and 3 microns, and the width of the second plurality of through trenches and/or second vias is between 1 micron and 3 microns.

3. The thin film transistor of claim 1, wherein the source and drain electrodes have a length of 100-200 microns.

4. The thin film transistor of claim 1, wherein the source and drain electrodes are made of a material comprising one or a combination of Mo, Al, Ti, Cu, and ITO.

5. The thin film transistor according to claim 1, wherein the number of the first through-grooves and/or the first through-holes of the source electrode is 4 to 50, and the number of the second through-grooves and/or the second through-holes of the drain electrode is 4 to 50.

6. A method for manufacturing a thin film transistor includes:

providing a substrate;

forming a gate electrode on the substrate;

forming a gate insulating layer on the substrate and the gate electrode;

forming a semiconductor unit on the gate insulating layer, wherein the semiconductor unit comprises a first semiconductor region, a second semiconductor region and a third semiconductor region, and the first semiconductor region and the third semiconductor region are positioned at two ends of the second semiconductor region; and

forming a source electrode and a drain electrode on the gate insulating layer and the semiconductor unit, wherein the source electrode covers a part of the gate insulating layer and the first semiconductor region of the semiconductor unit, the source electrode comprises a first region and a second region, the first region of the source electrode is electrically connected with the second region of the source electrode, the first region of the source electrode comprises a plurality of first through grooves and/or first through holes, the first through grooves and/or the first through holes penetrate through the first region of the source electrode to expose the gate insulating layer and the semiconductor unit, the drain electrode covers a part of the gate insulating layer and the third semiconductor region of the semiconductor unit, the drain electrode comprises a third region and a fourth region, the third region of the drain electrode is electrically connected with the fourth region of the drain electrode, and the third region of the drain electrode comprises a plurality of second through grooves and/or second through holes, the second through-trench and/or the second through-hole penetrates the first region of the drain electrode to expose the gate insulating layer and the semiconductor unit.

7. The method for manufacturing the thin film transistor according to claim 6, wherein the width of the plurality of first through grooves and/or the first through holes is 1 micron to 3 microns, and the width of the plurality of second through grooves and/or the second through holes is 1 micron to 3 microns.

8. The method of claim 6, wherein the source electrode and the drain electrode have a length of 100 to 200 μm.

9. The method for manufacturing a thin film transistor according to claim 6, wherein the material of the source electrode and the drain electrode comprises one or a combination of Mo, Al, Ti, Cu and ITO.

10. The method for manufacturing the thin film transistor according to claim 6, wherein the number of the first through grooves and/or the first through holes of the source electrode is 4 to 50, and the number of the second through grooves and/or the second through holes of the drain electrode is 4 to 50.

Technical Field

The application relates to the field of display, in particular to a thin film transistor and a manufacturing method thereof.

Background

With the continuous development of electronic display technology, flexible display devices have become the most promising new generation of display technology due to their advantages of light weight, small thickness, long service life, flexibility, etc., however, in the process of bending or folding the source and drain electrodes of the flexible substrate, due to the external force, cracks are likely to appear and diffuse to the channel, resulting in the decrease of the electrical connectivity of the source and drain electrodes, thereby affecting the performance of the device.

Disclosure of Invention

The application provides a thin film transistor and a manufacturing method thereof, which are used for improving the performance of a device.

The present application provides a thin film transistor, which includes:

a substrate;

a gate disposed on the substrate;

a gate insulating layer covering the substrate and the gate electrode;

the semiconductor unit is arranged on the grid insulating layer and comprises a first semiconductor region, a second semiconductor region and a third semiconductor region, and the first semiconductor region and the third semiconductor region of the semiconductor unit are positioned at two ends of the second semiconductor region;

a source electrode covering a portion of the gate insulating layer and the first semiconductor region of the semiconductor unit, the source electrode including a first region and a second region, the first region of the source electrode being electrically connected to the second region, the first region of the source electrode including a plurality of first through-trenches and/or first through-holes penetrating the first region of the source electrode to expose the gate insulating layer and the semiconductor unit; and

the drain electrode covers a part of the gate insulating layer and the first semiconductor region of the semiconductor unit, the drain electrode comprises a third region and a fourth region, the third region of the drain electrode is electrically connected with the fourth region, the third region of the drain electrode comprises a plurality of second through grooves and/or second through holes, and the second through grooves and/or the second through holes penetrate through the third region of the drain electrode to expose the gate insulating layer and the semiconductor unit.

In the thin film transistor provided by the application, the width of the plurality of first through grooves and/or the first through holes is 1 micrometer to 3 micrometers, and the width of the plurality of second through grooves and/or the second through holes is 1 micrometer to 3 micrometers.

In the thin film transistor provided by the application, the length of the source electrode and the drain electrode is 100-200 microns.

In the thin film transistor provided by the application, the material of the source electrode and the drain electrode comprises one or a combination of Mo, Al, Ti, Cu and ITO.

In the thin film transistor provided by the application, the number of the first through grooves and/or the first through holes of the source electrode is 4-50, and the number of the second through grooves and/or the second through holes of the drain electrode is 4-50.

The application provides a preparation method of a thin film transistor, which comprises the following steps:

providing a substrate;

forming a gate electrode on the substrate;

forming a gate insulating layer on the substrate and the gate electrode;

forming a semiconductor unit on the gate insulating layer, wherein the semiconductor unit comprises a first semiconductor region, a second semiconductor region and a third semiconductor region, and the first semiconductor region and the third semiconductor region are positioned at two ends of the second semiconductor region; and

forming a source electrode and a drain electrode on the gate insulating layer and the semiconductor unit, wherein the source electrode covers a part of the gate insulating layer and the first semiconductor region of the semiconductor unit, the source electrode comprises a first region and a second region, the first region of the source electrode is electrically connected with the second region of the source electrode, the first region of the source electrode comprises a plurality of first through grooves and/or first through holes, the first through grooves and/or the first through holes penetrate through the first region of the source electrode to expose the gate insulating layer and the semiconductor unit, the drain electrode covers a part of the gate insulating layer and the third semiconductor region of the semiconductor unit, the drain electrode comprises a third region and a fourth region, the third region of the drain electrode is electrically connected with the fourth region of the drain electrode, and the third region of the drain electrode comprises a plurality of second through grooves and/or second through holes, the second through-trench and/or the second through-hole penetrates the first region of the drain electrode to expose the gate insulating layer and the semiconductor unit. In the preparation method of the thin film transistor provided by the application, the groove diameters of the plurality of first through grooves and the plurality of second through grooves are 1-3 micrometers.

In the preparation method of the thin film transistor provided by the application, the width of the plurality of first through grooves and/or the first through holes is 1 micron to 3 microns, and the width of the plurality of second through grooves and/or the second through holes is 1 micron to 3 microns.

In the preparation method of the thin film transistor provided by the application, the length of the source electrode and the drain electrode is 100-200 microns.

In the preparation method of the thin film transistor provided by the application, the material of the source electrode and the drain electrode comprises one or a combination of more of Mo, Al, Ti, Cu and ITO.

In the preparation method of the thin film transistor provided by the application, the number of the first through grooves and/or the first through holes of the source electrode is 4-50, and the number of the second through grooves and/or the second through holes of the drain electrode is 4-50.

The application provides a thin film transistor and a preparation method thereof. The grid electrode, the grid electrode insulating layer, the semiconductor unit and the source and drain electrodes are sequentially arranged on the substrate, the source electrode covers a part of the grid electrode insulating layer and one end of the semiconductor unit, the source electrode comprises a first area and a second area, the first area of the source electrode is electrically connected with the second area, the first area of the source electrode comprises a plurality of first through grooves and/or first through holes, the first through grooves and/or the first through holes penetrate through the first area of the source electrode to expose the grid electrode insulating layer and the semiconductor unit, the drain electrode covers a part of the grid electrode insulating layer and the other end of the semiconductor unit, the drain electrode comprises a third area and a fourth area, the third area of the drain electrode is electrically connected with the fourth area, the third area of the drain electrode comprises a plurality of second through grooves and/or second through holes, and the second through grooves and/or the second through holes penetrate through the third area of the drain electrode to expose the grid electrode insulating layer And the semiconductor unit. In the application, the through grooves and/or the through holes are/is arranged in the thin film transistor, so that cracks of a device are reduced, and the performance of the device is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a structural cross-sectional view of a thin film transistor provided in the present application.

Fig. 2 is a top view of a first structure of a thin film transistor provided in the present application.

Fig. 3 is a top view of a second structure of a thin film transistor provided in the present application.

Fig. 4 is a top view of a third structure of a thin film transistor provided in the present application.

Fig. 5 is a schematic flow chart of a method for manufacturing a thin film transistor provided in the present application.

Fig. 6 is a cross-sectional flow diagram illustrating a method for fabricating a thin film transistor according to the present disclosure.

Detailed Description

The technical solution in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application, are within the scope of protection of the present application.

Referring to fig. 1, fig. 1 is a structural cross-sectional view of a thin film transistor provided in the present application. The present application provides a thin film transistor 10. The thin film transistor 10 includes a substrate 100, a gate electrode 200, a gate insulating layer 300, a semiconductor unit 400, a source electrode 500, and a drain electrode 600.

The gate electrode 200, the gate insulating layer 300, and the semiconductor unit 400 are sequentially disposed on the substrate 100. The semiconductor unit 400 includes a first semiconductor region 410, a second semiconductor region 420, and a third semiconductor region 430. The first semiconductor region 410, the second semiconductor region 420 and the third semiconductor region 430 of the semiconductor unit 400 are connected. The first semiconductor region 410 and the third semiconductor region 430 of the semiconductor unit 400 are located at both ends of the second semiconductor region 420.

The gate electrode 200 may be made of chromium (Cr), an alloy material of chromium, or a molybdenum-tantalum alloy, aluminum (Al), and an aluminum alloy material. The material of the gate insulating layer 300 includes SiO_x、Al₂O₃Or SiN_xAnd the like. The material of the semiconductor unit 400 includes Indium Gallium Zinc Oxide (IGZO).

The source electrode 500 covers a portion of the gate insulating layer 300 and the first semiconductor region 410 of the semiconductor unit 400. The drain electrode 600 covers a portion of the gate insulating layer 300 and the third semiconductor region 430 of the semiconductor unit 400.

Length L of the source electrode₁Is 100-200 microns. Length L of the drain electrode₂Is 100-200 microns. The source electrode and the drain electrode are made of one or a combination of Mo, Al, Ti, Cu and ITO.

Referring to fig. 2, fig. 2 is a top view of a first structure of a thin film transistor according to the present disclosure. The source electrode 500 includes a first region 510 and a second region 520. The first region 510 of the source electrode 500 is electrically connected to the second region 520 of the source electrode 500. The first region 510 of the source electrode 520 includes a number of first through-slots and/or first through-holes 530. In this embodiment, the first region 510 of the source 520 includes a plurality of first through slots 530. The number of the first through grooves of the first region 510 of the source electrode 500 is 4-50. Each of the first through trenches 530 penetrates the first region 510 of the source electrode 500 to expose the gate insulating layer 300 and the first semiconductor region 410 of the semiconductor unit 400. The width W of each of the first through slots 530₁Is 1 micron to 3 microns. The penetrating direction of each of the first through grooves 530 may penetrate the source electrode 500 at an angle. In the present embodiment, the first through-trench 530 penetrates the source 500 in a direction perpendicular to the width direction of the semiconductor unit 400.

The source electrode 500 and the drain electrode 600 are in phaseAnd (4) setting. The drain electrode 600 includes a third region 610 and a fourth region 620. The third region 610 of the drain electrode 600 is electrically connected to the fourth region 620 of the drain electrode 600. The third region 610 of the drain 600 includes a plurality of second through-slots and/or second through-holes 630. In this embodiment, the third region 610 of the drain 600 includes a plurality of second through grooves 630. The number of the second through grooves 630 of the third region 610 is 4 to 50. The second through trench 630 penetrates the third region 610 of the drain 600 to expose the gate insulating layer 300 and the third semiconductor region 430 of the semiconductor unit 400. The width W of each of the second through slots 630₂Is 1 micron to 3 microns. The penetrating direction of each of the second through-grooves 630 and/or the second through-holes may penetrate the drain electrode 600 at an angle. In this embodiment, the second through groove 630 penetrates the drain 600 in a direction perpendicular to the width direction of the semiconductor unit 400.

Referring to fig. 3, fig. 3 is a top view of a second structure of a thin film transistor according to the present application. In one embodiment, the first via 513 penetrates the first region 511 of the source 501 parallel to the width direction of the semiconductor unit 401 and exposes the gate insulating layer 300 and the first semiconductor region 410 of the semiconductor unit 400. The width W of the first via 513 of the source 501₃Is 1 micron to 3 microns. The second via 613 penetrates the third region 611 of the drain 601 in parallel to the width direction of the semiconductor unit 401 to expose the gate insulating layer 300 and the third semiconductor region 430 of the semiconductor unit 400. The width W of the second via 613 of the drain 601₄Is 1 micron to 3 microns. The length L of the source 501₃Is 100-200 microns. The length L of the drain 601₄Is 100-200 microns.

Referring to fig. 4, fig. 4 is a top view of a third structure of a thin film transistor provided in the present application. In one embodiment, the first via 524 penetrates the first region 521 of the source 502 perpendicular to the width direction of the semiconductor unit 402. The first through-trench 523 penetrates the first region 521 of the source 502 perpendicularly to the width direction of the semiconductor unit 402. The first via 524 of the source 502Width W of₆Is 1 micron to 3 microns. The width W of the first through groove 523 of the source 502₅Is 1 micron to 3 microns. The second via 624 penetrates the third region 621 of the drain 602 perpendicular to the width direction of the semiconductor unit 402. The second through groove 623 penetrates the third region 621 of the drain 602 perpendicular to the width direction of the semiconductor unit 402. Width W of the second via 624 of the drain 602₈Is 1 micron to 3 microns. The width W of the second through groove 623 of the drain 602₇Is 1 micron to 3 microns. Length L of the source electrode₅Is 100-200 microns. Length L of the drain electrode₆Is 100-200 microns.

Referring to fig. 5, fig. 5 is a schematic flow chart of a method for manufacturing a thin film transistor according to the present application. The application also provides a manufacturing method of the display device. The method comprises the following steps:

20. a substrate 100 is provided.

The substrate 100 is used for carrying the structure of the device. The material for preparing the substrate 100 is not limited.

30. A gate electrode 200 is formed on the substrate 100.

Referring to fig. 6, fig. 6 is a cross-sectional flow diagram illustrating a method for fabricating a thin film transistor according to the present disclosure. And depositing a metal electrode bottom gate layer on the substrate 100 by adopting a physical vapor deposition process. And performing yellow light process and etching process on the metal electrode bottom gate layer to form a gate 200 with a pattern.

The material of the gate electrode 200 includes chromium (Cr), an alloy material of chromium or a molybdenum-tantalum alloy, aluminum (Al), an aluminum alloy, and the like.

40. A gate insulating layer 300 is formed on the substrate 100 and the gate electrode 200.

Vapor deposition of SiO using plasma enhanced chemistry₂As the gate insulating layer 300. The gate insulating layer 300 covers the substrate 100 and the gate electrode 200 on the substrate 100.

The material of the gate insulating layer 300 includes SiO_x、Al₂O₃Or SiN_xAnd the like.

50. A semiconductor unit 400 is formed on the gate insulating layer 300, the semiconductor unit including a first semiconductor region 401, a second semiconductor region 402, and a third semiconductor region 403, the first semiconductor region 401 and the third semiconductor region 403 being located at both ends of the second semiconductor region 402.

A first metal layer is deposited on the gate insulating layer 300 using a physical vapor deposition process. After the first metal layer is degraded, the first metal layer is subjected to a yellow light process and an etching process to form a semiconductor unit 400 having a pattern.

The material of the semiconductor unit 400 includes Indium Gallium Zinc Oxide (IGZO).

60. Forming a source electrode 500 and a drain electrode 600 on the gate insulating layer 300 and the semiconductor unit 400, wherein the source electrode 500 covers a portion of the gate insulating layer 300 and the first semiconductor region 401 of the semiconductor unit 400, the source electrode 500 includes a first region 510 and a second region 520, the first region 510 of the source electrode 500 is electrically connected to the second region 520 of the source electrode 500, the first region 510 of the source electrode 500 includes a plurality of first through-grooves and/or first through-holes 530, the first through-grooves and/or first through-holes 530 penetrate through the first region 510 of the source electrode 500 to expose the gate insulating layer 300 and the semiconductor unit 400, the drain electrode 600 covers a portion of the gate insulating layer 300 and the third semiconductor region 403 of the semiconductor unit 400, the drain electrode 600 includes a third region 610 and a fourth region 620, and the third region 610 of the drain electrode 600 is electrically connected to the fourth region 620 of the drain electrode 600, the third region 610 of the drain electrode 600 includes a plurality of second through-grooves and/or second through-holes 630, and the second through-grooves and/or second through-holes 630 penetrate the third region 610 of the drain electrode 600 to expose the gate insulating layer 300 and the semiconductor unit 400.

Referring to fig. 2, fig. 2 is a top view of a first structure of a thin film transistor according to the present disclosure. A second metal layer is deposited on the gate insulating layer 300 and the semiconductor unit 400 using a physical vapor deposition process. Performing a yellow light process and an etching process on the second metal layer, wherein the second metal layer forms a source electrode 500And a drain electrode 600. The source electrode and the drain electrode are made of one or a combination of Mo, Al, Ti, Cu and ITO. Length L of the source electrode₁Is 100-200 microns. Length L of the drain electrode₂Is 100-200 microns.

The source electrode 500 is formed to cover a portion of the gate insulating layer 300 and the first semiconductor region 401 of the semiconductor unit 400. The source electrode 500 includes a first region 510 and a second region 520. The first region 510 of the source electrode 500 is electrically connected to the second region 520 of the source electrode 500. The first region 510 of the source electrode 520 includes a number of first through-slots and/or first through-holes 530. The first through-trench 530 and/or the first via penetrates the first region 510 of the source electrode 500 to expose the gate insulating layer 300 and the semiconductor unit 400. The width W of each of the first through slots and/or first through holes 530₁Is 1 micron to 3 microns. The number of the first through grooves and/or the first through holes 530 of the first region 510 of the source electrode 500 is 4-50. The penetrating direction of each of the first through grooves and/or the first through holes 530 may penetrate the source electrode 500 at an angle. In the present embodiment, the first through trenches 530 penetrate the first region 510 of the source electrode 500 in a direction perpendicular to the width direction of the semiconductor unit 400, and expose the gate insulating layer 300 and the first semiconductor region 401 of the semiconductor unit 400. The width W of each of the first through slots 530₁Is 1 micron to 3 microns. The number of the first through grooves 530 of the first region 510 of the source electrode 500 is 4 to 50.

The drain electrode 600 is disposed opposite to the source electrode 500. The drain electrode 600 is formed to cover a portion of the gate insulating layer 300 and the third semiconductor region 430 of the semiconductor unit 400. The drain electrode 600 includes a third region 610 and a fourth region 620. The third region 610 of the drain electrode 600 is electrically connected to the fourth region 620 of the drain electrode 600. The third region 610 of the drain 600 includes a plurality of second through-slots and/or second through-holes 630. The second through-trench and/or the second via 630 penetrates the third region 610 of the drain electrode 600 to expose the gate insulating layer 300 and the semiconductor unit 400. Of the second through slot and/or second through hole 630 of the third region 610The number is 4-50. The width W of each second through groove and/or second through hole 630₂Is 1 micron to 3 microns. The penetrating direction of each of the second through-grooves 630 and/or the second through-holes may penetrate the drain electrode 600 at an angle.

In the present embodiment, the second through recesses 630 penetrate the third region 610 of the drain 600 in a direction perpendicular to the width direction of the semiconductor unit 400, and expose the gate insulating layer 300 and the third semiconductor region 403 of the semiconductor unit 400. The number of the second through grooves 630 of the third region 610 is 4 to 50. The width W of each second through groove₂Is 1 micron to 3 microns

The application provides a thin film transistor and a preparation method thereof. The grid electrode, the grid electrode insulating layer, the semiconductor unit and the source and drain electrodes are sequentially arranged on the substrate, the source electrode covers a part of the grid electrode insulating layer and one end of the semiconductor unit, the source electrode comprises a first area and a second area, the first area of the source electrode is electrically connected with the second area, the first area of the source electrode comprises a plurality of first through grooves and/or first through holes, the first through grooves and/or the first through holes penetrate through the first area of the source electrode to expose the grid electrode insulating layer and the semiconductor unit, the drain electrode covers a part of the grid electrode insulating layer and the other end of the semiconductor unit, the drain electrode comprises a third area and a fourth area, the third area of the drain electrode is electrically connected with the fourth area, the third area of the drain electrode comprises a plurality of second through grooves and/or second through holes, and the second through grooves and/or the second through holes penetrate through the third area of the drain electrode to expose the grid electrode insulating layer And the semiconductor unit. In the application, the through grooves and/or the through holes are/is arranged in the thin film transistor, so that cracks of a device are reduced, and the performance of the device is improved.

The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.