阅读说明：本技术 一种基于全自旋逻辑器件的2-4线译码器及其控制方法 (2-4 line decoder based on full spin logic device and control method thereof ) 是由 王森 张永锋 王晓袁 杨影 范洪亮 于 2019-10-24 设计创作，主要内容包括：本发明公开了一种基于全自旋逻辑器件的2-4线译码器及其控制方法,译码器包括一个使能控制端S、两个输入端A<Sub>1</Sub>、A<Sub>0</Sub>和4个5输入择少逻辑门M5；使能控制端S与4个5输入择少逻辑门M5的输入端In3连接；输入端A<Sub>1</Sub>与第一5输入择少逻辑门M5、第二5输入择少逻辑门M5的输入端In2连接；输入端A<Sub>1</Sub>经第一反相器分别与第三5输入择少逻辑门M5、第四5输入择少逻辑门M5的输入端In2连接；输入端A<Sub>0</Sub>与第一5输入择少逻辑门M5、第三5输入择少逻辑门M5的输入端In1连接；输入端A<Sub>0</Sub>经第二反相器分别与第二5输入择少逻辑门M5、第四5输入择少逻辑门M5的输入端In1连接。本发明具有超高集成度、超低功耗、抗辐射和非易失性以及可持续缩小等优点。(The invention discloses a 2-4 line decoder based on full spin logic device and control method thereof, wherein the decoder comprises an enabling control end S and two input ends A 1 、A 0 And 4 5 input select less logic gates M5; the enable control terminal S is connected with the input terminals In3 of the 4 5-input selection less logic gates M5; input terminal A 1 The input ends In2 of the first and second 5-input selection less logic gates M5 and M5 are connected; input terminal A 1 The first inverter is respectively connected with the input ends In2 of a third 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5; input terminal A 0 The input ends In1 of the first and third 5-input selection less logic gates M5 and M5 are connected; input terminal A 0 And respectively connected with the input ends In1 of a second 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a second inverter. The invention has ultrahigh integration level, ultralow power consumption, radiation resistance and uneasinessLoss of consistency and sustainable reduction.)

1. A 2-4 line decoder based on full spin logic devices, comprising: the decoder is constructed by full spin logic devices; the core module of the decoder is a five-input selection less logic gate; the decoder inputs signals by using an input interface circuit based on a magnetic tunnel junction; the decoder comprises an enabling control terminal S and at least two input terminals A₁、A₀And at least 4 5-input select-less logic gates M5;

the 5-input selection-less logic gate M5 comprises an input end In1, In2, In3, In4, In5 and an output end Out 1;

the enabling control end S is respectively connected with input ends In3 input interfaces of 4 5-input selection less logic gates M5;

input terminal A₁One path is respectively connected with input ports In2 of input ends of a first 5-input selection less logic gate M5 and a second 5-input selection less logic gate M5;

input terminal A₁The other path of the input signal is respectively connected with the input ports In2 of the input ends of a third 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a first inverter;

input terminal A₀One path is respectively connected with the output of the first 5 input selection less logic gate M5 and the third 5 input selection less logic gate M5The input end In1 is connected with an input interface;

input terminal A₀The other path of the input signal is respectively connected with the input ports In1 of the input ends of a second 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a second inverter;

the input end In4 and the input end In5 of the four 5-input selection less logic gates M5 respectively input logic 1;

the output signal of the first 5-input selection-less logic gate M5 is Y₀；

The output signal of the second 5-input selection-less logic gate M5 is Y₁；

The output signal of the third 5-input select-less logic gate M5 is Y₂；

The output signal of the fourth 5-input select-less logic gate M5 is Y₃。

2. The full spin logic device based 2-4 line decoder of claim 1, wherein: the select few logic gates in the decoder may be replaced with select many logic gates.

3. A control method of 2-4 line decoder based on full spin logic device according to claim 1, wherein the control method comprises the following steps:

s1, during 0-2 ns, at S, A₁And A₀A 0.1V negative voltage is added on the end to ensure that the direction of the magnetic moment of the MTJ free layer is consistent with that of the fixed layer, thereby realizing resetting; the operating voltage V applied to the ASL at this time_ASLWhen the voltage is equal to 0V, selecting few logic gates to be out of work;

s2, during 2-4 ns, the decoding function is required to be S, A₁And A₀The high level and the low level are input on the end, the high level is 0.1V, the low level is 0V, the high level represents that logic 1 is input, and the low level represents that logic 0 is input; the direction of the magnetic moment of the MTJ free layer connected with the input low level end is unchanged, the direction of the magnetic moment of the MTJ free layer is the same as that of the fixed layer, and the direction of the magnetic moment of the MTJ free layer connected with the input high level end is opposite to that of the fixed layer; at the same time, the operating voltage V is applied to the ASL_ASLWhen the voltage is equal to 0V, selecting few logic gates to be out of work;

s3, in the period of 4-6 ns, S, A₁And A₀Operating voltage V on terminal_MTJThe magnetic moment directions of the MTJ free layers are all kept unchanged at 0V, and input signals are provided for the selection less logic gates; applying a positive voltage, V, to the ASL_ASLThe ASL can be driven to work when the voltage is 5mV, a few logic gates are selected to start working, and the magnetic moment direction of the output end is determined according to the magnetic moment directions of 5 input ends;

s4, during 6-8 ns, at S, A₁And A₀Terminal is applied with a negative voltage, V_MTJ-0.1V, voltage V on ASL_ASLAnd repeating the process in the period of 0-2 ns when the voltage is 0V, and resetting the magnetic moment of the input end.

Technical Field

The invention relates to the field of circuit systems, in particular to a 2-4 line decoder involved in a digital circuit.

Background

At present, the mainstream 2-4 line decoder mainly uses the voltage level to represent binary information, and the basic component of the decoder is a bipolar transistor or a metal oxide semiconductor field effect transistor. Such as a common 74LS139 type 2-4 line decoder, adopts a bipolar process, and the working voltage of a power supply is about 5V. The 74HC139 type 2-4 line decoder is manufactured by adopting a metal oxide semiconductor field effect transistor process, and the working voltage of a power supply is generally 2V-6V.

The electrons have two intrinsic properties of charge and spin, and the existing 2-4-line decoder mainly uses the electron charge to represent binary information, because the problems of electron tunneling, power dissipation, transmission delay and the like are approaching to the physical limit. The spin electronic device utilizes the electron spin to represent information, and has the advantages of ultra-low power consumption, radiation resistance, non-volatility and the like. In addition, an All Spin Logic (ASL) device uses electron Spin in information processing, transmission, storage and other processes, and does not need to add an additional hardware structure to continuously convert Spin information and charge information, so that the All Spin Logic (ASL) device is expected to be an important candidate of a next-generation electronic device.

At present, the research on the circuit structure design based on the ASL device is relatively less, the known circuit mainly comprises an inverter, a selective multi-logic gate, a full adder, an RS trigger, a D trigger and the like, but a decoder which is an important component in a logic circuit is not reported yet, so that in view of the above, the invention designs a 2-4-line decoder based on the ASL device, the decoder is provided with an enabling control end for controlling the permission of decoding or the prohibition of decoding, and the function of the 2-4-line decoder can be conveniently expanded.

Disclosure of Invention

The invention aims to provide a 2-4 line decoder based on full spin logic devices, which can be used for code conversion, data distribution, memory addressing, logic expression representation and the like.

In order to realize the purpose, the following technical scheme is adopted: the core module of the decoder is a five-input selection less logic gate, and an input interface circuit based on a Magnetic Tunnel Junction (MTJ) is used for inputting signals so as to avoid a fan-out structure and a long spin channel, wherein the decoder comprises an enabling control end S and at least two input ends A₁、A₀And at least 4 5-input select-less logic gates M5;

the 5-input selection-less logic gate M5 comprises an input end In1, In2, In3, In4, In5 and an output end Out 1;

the enabling control end S is respectively connected with input ends In3 input interfaces of 4 5-input selection less logic gates M5;

input terminal A₁One path is respectively connected with input ports In2 of input ends of a first 5-input selection less logic gate M5 and a second 5-input selection less logic gate M5;

input terminal A₁The other path of the input signal is respectively connected with the input ports In2 of the input ends of a third 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a first inverter;

input terminal A₀One path is respectively connected with input ports In1 of input ends of a first 5-input selection less logic gate M5 and a third 5-input selection less logic gate M5;

input terminal A₀The other path of the input signal is respectively connected with the input ports In1 of the input ends of a second 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a second inverter;

the input end In4 and the input end In5 of the four 5-input selection less logic gates M5 respectively input logic 1;

the output signal of the first 5-input selection-less logic gate M5 is Y₀；

The output signal of the second 5-input selection-less logic gate M5 is Y₁；

The output signal of the third 5-input select-less logic gate M5 is Y₂；

The output signal of the fourth 5-input select-less logic gate M5 is Y3.

Further, the select-less logic gates in the decoder may be replaced with select-more logic gates.

In addition, the invention provides a control method of a 2-4 line decoder based on a full spin logic device, which comprises the following steps:

s1, during 0-2 ns, at S, A₁And A₀A negative voltage (-0.1V or so) is added on the end to ensure that the direction of the magnetic moment of the MTJ free layer is consistent with the direction of the magnetic moment of the fixed layer, thereby realizing resetting; the operating voltage V applied to the ASL at this time_ASLWhen the voltage is equal to 0V, selecting few logic gates to be out of work;

s2, during 2-4 ns, the decoding function is required to be S, A₁And A₀The high and low level is input on the terminal (the high level is generally about 0.1V, the low level is 0V, the high level represents the input of logic 1, and the low level represents the input of logic 0); the direction of the magnetic moment of the MTJ free layer connected with the input low level end is unchanged, the direction of the magnetic moment of the MTJ free layer is the same as that of the fixed layer, and the direction of the magnetic moment of the MTJ free layer connected with the input high level end is opposite to that of the fixed layer; at the same time, the operating voltage V is applied to the ASL_ASLWhen the voltage is equal to 0V, selecting few logic gates to be out of work;

s3, in the period of 4-6 ns, S, A₁And A₀Operating voltage V on terminal_MTJThe magnetic moment direction of the MTJ free layer is kept unchanged at 0V, and an input signal is provided for the selection less logic gate; adding positive voltage to the ASL, selecting few logic gates to start working, and determining the magnetic moment direction of an output end according to the magnetic moment directions of 5 input ends;

s4, during 6-8 ns, at S, A₁And A₀Terminal applied negative voltage (V)_MTJabout-0.1V), voltage V on ASL_ASLAnd repeating the process in the period of 0-2 ns when the voltage is 0V, and resetting the magnetic moment of the input end.

Compared with the prior art, the invention has the following advantages:

1. different from a decoder constructed by the traditional CMOS device technology, the 2-4 line decoder is constructed based on a full spin logic device, utilizes electron spin to represent information, has the advantages of ultrahigh integration level, ultralow power consumption, radiation resistance, nonvolatility, sustainable reduction and the like, and is expected to be an important candidate of the next generation of electronic devices.

2. The traditional CMOS device technology mainly constructs a decoder based on a NAND gate, and although ASL devices can construct common logic units such as a NAND gate, a NOR gate and the like, the basic units of the ASL devices are inverters and a majority/minority logic gate. The invention utilizes 5 inputs to select few logic gates to construct the 2-4 line decoder, and the structure is greatly simplified compared with the traditional method of constructing the decoder based on NAND gates and the like.

3. The invention has 4 total 5-input selection-less logic gates, and each selection-less logic gate needs an input S, A₁And A₀If one input signal is used for simultaneously providing input for 4 select-less logic gates, a fan-out structure is needed for shunting the signal, and the length of a channel for transmitting the spin current is longer. One of the troublesome problems of the ASL device is that the spin current decreases sharply with the increase of the spin channel length, and the operating voltage of the device needs to be increased to enable the circuit to operate normally, which results in a sharp increase in the power consumption of the circuit and a significant decrease in the operating speed. In order to solve the problem, the invention adopts an input interface circuit based on the magnetic tunnel junction, so that each less-selected logic gate adopts independent input, a fan-out structure is avoided, and the length of a spin channel is reduced. Additionally, for input S, A₁And A₀The original variable or the inverse variable is realized by utilizing different magnetic moment directions of the fixed layers of the magnetic tunnel junctions, and the number of inverters is greatly reduced.

Drawings

Fig. 1 is a logic circuit diagram of the present invention.

Fig. 2 is an overall layout of the present invention.

Fig. 3 is a diagram of an ASL device with an input interface according to the present invention.

FIG. 4 is a schematic plan view of a 5-input select-less logic gate of the present invention.

FIG. 5(a) is a block diagram of the decoder output Y of the present invention₀And (4) partial layout.

FIG. 5(b) is the decoder output Y of the present invention₁And (4) partial layout.

FIG. 5(c) is the decoder output Y of the present invention₂And (4) partial layout.

FIG. 5(d) is the decoder output Y of the present invention₃And (4) partial layout.

Fig. 6 is a graph of input signal and operating voltage waveforms in accordance with the present invention.

Fig. 7 is a logic circuit diagram of a 3-8 line decoder constructed in accordance with the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings:

as shown in fig. 1, the decoder according to the present invention comprises an enable control terminal S, at least two input terminals a₁、A₀And at least 4 5-input select-less logic gates M5; a1 is an inverter; a2 is an input select few logic gate;

the 5-input selection-less logic gate M5 comprises an input end In1, In2, In3, In4, In5 and an output end Out 1;

the enabling control end S is respectively connected with input ends In3 input interfaces of 4 5-input selection less logic gates M5;

input terminal A₁One path is respectively connected with input ports In2 of input ends of a first 5-input selection less logic gate M5 and a second 5-input selection less logic gate M5;

input terminal A₁The other path of the input signal is respectively connected with the input ports In2 of the input ends of a third 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a first inverter;

input terminal A₀One path is respectively connected with input ports In1 of input ends of a first 5-input selection less logic gate M5 and a third 5-input selection less logic gate M5;

input terminal A₀The other path of the input signal is respectively connected with the input ports In1 of the input ends of a second 5 input selection less logic gate M5 and a fourth 5 input selection less logic gate M5 through a second inverter;

the input end In4 and the input end In5 of the four 5-input selection less logic gates M5 respectively input logic 1;

the output signal of the first 5-input selection-less logic gate M5 is Y₀；

The output signal of the second 5-input selection-less logic gate M5 is Y₁；

Third stepThe output signal of the 5-input selection-less logic gate M5 is Y₂；

The output signal of the fourth 5-input select-less logic gate M5 is Y3.

Wherein, two input ends of the five-input selection less logic gate are set to be 1, three-input not AND operation can be realized, and the logic expression is

From equation (1) and FIG. 1, the expression of four output ends is given as

The functional tables can be obtained from the formulae (2) to (5), and are shown in Table 1.

TABLE 12-4 line decoder function Table

As can be seen from table 1, the decoder has two inputs a₁And A₀In total 4 combination states, 4 output signals Y can be decoded₀～Y₃And 2-4 line decoding function is realized. In addition, when the enable control end S of the decoder is logic 0, the decoder is in an operating state, and when the control end S is logic 1, the output is all 0, and the decoder does not operate. The 2-4 line decoder can be expanded in function through the control terminal S, such as 3-8 line decoder, 4-16 line decoder, and the like.

Taking A3-8 line decoder as an example, as shown in fig. 7, the decoder includes three input terminals a2, a1, a0, two 2-4 line decoders, and an inverter a 1;

the input end A2 is connected with an enable control end S of the first 2-4 line decoder, and the input end A2 is connected with the enable control end S of the second 2-4 line decoder through an inverter a 1;

the input end A1 is respectively connected with A1 of the first 2-4 line decoder and the second 2-4 line decoder;

the input end A0 is respectively connected with A0 of the first 2-4 line decoder and the second 2-4 line decoder;

the output signal of the first 5-input selection-less logic gate M5 in the first 2-4 line decoder is Y0;

the output signal of the second 5-input selection-less logic gate M5 in the first 2-4 line decoder is Y1;

the output signal of the third 5 input selection less logic gate M5 in the first 2-4 line decoder is Y2;

the output signal of the fourth 5-input select-less logic gate M5 in the first 2-4 line decoder is Y3.

The output signal of the first 5-input selection-less logic gate M5 in the second 2-4 line decoder is Y4;

the output signal of the second 5-input selection-less logic gate M5 in the second 2-4 line decoder is Y5;

the output signal of the third 5 input selection less logic gate M5 in the second 2-4 line decoder is Y6;

the output signal of the fourth 5 input selection less logic gate M5 in the second 2-4 line decoder is Y7;

in an ASL circuit, binary information is not characterized by the high and low of a voltage, but by the direction of magnetic moment of a magnet. Therefore, not only a voltage signal needs to be applied to drive the circuit to operate, but also an initial magnetic moment direction needs to be set for the magnet to input a signal. For circuits such as decoders that require multiple identical inputs, the input interface circuitry may be used to avoid long spin channels, i.e., to provide input signals to the ASL circuits through metal lines and Magnetic Tunnel Junctions (MTJs). Thus, a 2-4 line decoder is implemented using an input interface and 5 input select few logic gates, as shown in FIG. 2.

The functions thereof will be explained below.

(1) Input interface circuit

The input interface circuit is shown in fig. 3, in which the magnetic moment of the fixed layer of the MTJ remains unchanged, and the free layer of the MTJ serves as an input end of the ASL device, and by applying voltages with different polarities to the MTJ, the magnetic moment direction of the free layer of the MTJ can be changed, so that a logic 0 or a logic 1 can be input to the ASL device (assuming that the magnetic moment direction points to the-x axis to represent a logic 0, and the direction points to the + x axis to represent a logic 1). In fig. 3, 1 is a fixed layer, 2 is a free layer, 3 is an output-side magnetic body, 4 is a ground, 5 is a channel, 6 is an insulating layer, and 7 is a tunnel layer.

The voltage source V on the MTJ is required to allow the input interface circuit to operate properly_MTJAnd a voltage source V on the ASL_ASLRespectively act independently. First, a voltage source V is applied across the MTJ_MTJAt this time, let V_ASL0V. When the voltage of the voltage source V_MTJWhen the voltage is positive, the free layer magnetic moment is opposite to the fixed layer, and when the voltage is V_MTJWhen negative, the free layer magnetic moment is the same as the pinned layer. Let V after the writing of free layer magnetic moment is completed_MTJ0V, in which case a voltage source V is applied to the free layer and the output end magnet_ASLWhen the voltage source voltage V is_ASLWhen the current is positive, the magnetic moment of the output end is opposite to that of the free layer, so that the function of an inverter is realized; when the voltage of the voltage source V is_ASLWhen the magnetic moment of the output end is negative, the magnetic moment of the output end is the same as that of the free layer, and the function of a buffer is realized.

(2) 5-input less-selection logic gate circuit

The 5-input select-less logic gate is a core device for realizing logic operation, as shown In fig. 4, In 1-In 5 respectively represent 5 input terminals, and Out1 represents an output terminal. The arrows indicate the magnetic moment direction, wherein the double arrows indicate the magnetic moment direction to be determined, and the single arrows indicate that the magnetic moment direction is fixed. The input ends In1, In2 and In3 are respectively connected with the input end S, A through input interfaces₁And A₀And the magnetic moment direction is determined by the polarity of the voltage applied to the MTJ and the magnetic moment direction of the MTJ fixed layer. While the magnetic moment directions of the input terminals In4 and In5 point In the + x-axis direction, indicating an input logic 1. By adding to the magnetUpper positive operating voltage V_ASLThe above structure can realize the logic function shown in the formula (1). In fig. 4, 1 denotes a magnet and 2 denotes a channel.

(3)2-4 line decoder circuit

As can be seen from the logic circuit diagram shown in fig. 1, to implement a 2-4-line decoder, both the original variable and the inverse variable are required, and the input of the original variable and the inverse variable is implemented by using the different orientations of the magnetic moments of the MTJ fixed layer in the input interface, so that an additional inverter is avoided, and the circuit structure is greatly simplified. The specific implementation is that if the input signal appears in an original variable form, the fixed layer magnetic moment of the input interface points to the-x axis, and if the input signal appears in an inverse variable form, the fixed layer magnetic moment of the input interface points to the + x axis.

As shown in the formula (2), the output terminal Y₀All three input variables of (a) are in the original variable form, so that all three magnetic moments of the MTJ fixed layer point to the-x axis direction, and the structure is shown in FIG. 5 (a). And according to the formula (3), the output terminal Y₁Input variables S and A of₁Is present in the form of the original variable, and A₀In inverse quantitative form, and thus with S and A₁The MTJ pinned layer has its magnetic moment pointing in the-x direction and connected with A₀The end-connected MTJ pinned layer magnetic moment points in the + x-axis direction, and the structure is shown in fig. 5 (b). Similarly, the formula (4) shows that₀End-coupled MTJ pinned layer magnetic moments pointing in the-x direction, and₁the magnetic moment of the MTJ fixed layer connected with the end points to the + x-axis direction and outputs Y₂FIG. 5(c) shows the structure of (1). As shown in formula (5), the magnetic moment of the MTJ pinned layer connected to the S terminal points to the-x axis and to A₀And A₁The magnetic moment of the MTJ fixed layer connected with the end points to the + x-axis direction and outputs Y₃FIG. 5(d) shows the structure of (A).

In addition, the input terminals In4 and In5 are both input 1, and therefore, In the In4 and In5 input terminals of the four select-less logic gates In fig. 5, the magnetic moments of the magnets are both fixedly directed In the + x-axis direction. The four circuits shown in fig. 5 are connected together in the manner shown in fig. 2 to form a complete 2-4 line decoder.

(4) Signal control flow of 2-4 line decoder

The switching time of the MTJ free layer magnetic moment and the ASL device signal propagation delay time are typically in the order of nanoseconds. The operating voltage of the MTJ is typically less than 1V, while the operating voltage of the ASL is typically in millivolts. Therefore, for convenience of explanation, assume that each signal has a duration of 2ns, a voltage amplitude applied to the MTJ is 0.1V, and a voltage amplitude applied to the ASL device is 5 mV.

For the 2-4 line decoder to work properly, appropriate control signals are applied to the circuit, and the input signals and the working voltage sequence are shown in fig. 6. As can be seen in fig. 6:

let S, A let during 0-2 ns₁And A₀Voltage V on terminal_MTJis-0.1V, i.e. at S, A₁And A₀A negative voltage is applied to the terminal. At this time, the current flowing through the MTJ flows from bottom to top, so that the MTJ free layer magnetic moment direction coincides with the pinned layer magnetic moment direction, which may be referred to as reset. This voltage V_MTJIs a reset signal for resetting the magnetic moment at the input. At the same time, the operating voltage V is applied to the ASL_ASLAnd when the voltage is equal to 0V, the selection less logic gate does not work.

During 2-4 ns, S and A₀The voltage on the terminals is zero, and A₁The voltage on the terminals is 0.1V. At this time, with S and A₀The magnetic moment direction of the end-connected MTJ free layer is unchanged and is the same as that of the fixed layer and A₁The magnetic moment direction of the MTJ free layer connected with the end is opposite to that of the fixed layer.

S, A during 2-4 ns₁And A₀The total of 8 combinations of high and low voltages on the terminals represents 8 input cases at the 3 inputs of the 2-4 line decoder, and only one case of "010" input in table 1 is shown in fig. 6. At the same time, the operating voltage V is applied to the ASL_MTJStill 0V, select few logic gates not work.

S, A during 4-6 ns₁And A₀Operating voltage V on terminal_MTJAnd (5) 0V, wherein the magnetic moment directions of the MTJ free layers are all kept unchanged, and an input signal is provided for the selection-less logic gate. And the voltage V applied to the ASL_ASLStarting to work by selecting less logic gates according to the magnetic moment squares of 5 input endsAnd so on to determine the output end magnetic moment direction. In the case of this figure, Y is output₀、Y₁And Y₃All pointing in the-x direction and outputting Y₂The magnetic moment of the magnetic encoder points to the + x-axis direction, and the decoding function is realized.

S, A during 6-8 ns₁And A₀Voltage V on terminal_MTJ-0.1V, voltage V on ASL_ASLAnd repeating the process in the period of 0-2 ns when the voltage is 0V, and resetting the magnetic moment of the input end.

The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements of the technical solution of the present invention by those skilled in the art should fall within the protection scope defined by the claims of the present invention without departing from the spirit of the present invention.