阅读说明：本技术 灵敏放大器电路、存储器 (Sensitive amplifier circuit and memory ) 是由 徐依然 马继荣 黄金煌 于 2021-08-03 设计创作，主要内容包括：本申请涉及电路集成技术领域,公开一种灵敏放大器电路,包括：参考单元电流生成电路,用于生成参考单元电流和参考电压；电流比较电路,与参考单元电流生成电路电连接,电流比较电路用于将参考单元电流转换成参考电流,在读取存储阵列的情况下生成单元电流,并根据参考电流和单元电流形成读取电压；锁存电路,通过连接电路分别与电流比较电路和参考单元电流生成电路电连接,锁存电路用于获取参考电压和读取电压的电压差并对电压差进行正反馈得到逻辑信号；连接电路,用于在读取存储阵列的情况下将参考单元电流生成电路和锁存电路导通。由于锁存电路进行正反馈的响应时间较短,从而提高了存储器的读取速度。本申请还公开一种存储器。(The application relates to the technical field of circuit integration, and discloses a sensitive amplifier circuit, which comprises: a reference cell current generating circuit for generating a reference cell current and a reference voltage; a current comparison circuit electrically connected to the reference cell current generation circuit, the current comparison circuit for converting the reference cell current into a reference current, generating a cell current in a case of reading the memory array, and forming a read voltage according to the reference current and the cell current; the latch circuit is electrically connected with the current comparison circuit and the reference unit current generation circuit through the connecting circuit respectively, and is used for acquiring the voltage difference between the reference voltage and the reading voltage and performing positive feedback on the voltage difference to obtain a logic signal; and a connection circuit for turning on the reference cell current generation circuit and the latch circuit in the case of reading the memory array. The response time of the latch circuit for positive feedback is short, so that the reading speed of the memory is improved. The application also discloses a memory.)

1. A sense amplifier circuit, comprising:

a reference cell current generating circuit for generating a reference cell current and a reference voltage;

a current comparison circuit electrically connected to the reference cell current generation circuit, the current comparison circuit configured to convert the reference cell current into a reference current, generate a cell current in a case of reading the memory array, and form a read voltage according to the reference current and the cell current;

the latch circuit is electrically connected with the current comparison circuit and the reference unit current generation circuit respectively through a connecting circuit, and is used for acquiring the voltage difference between the reference voltage and the reading voltage and performing positive feedback on the voltage difference to obtain a logic signal;

the connection circuit is used for conducting the reference unit current generation circuit and the latch circuit under the condition of reading the memory array, and conducting the current comparison circuit and the latch circuit.

2. The sense amplifier circuit of claim 1, wherein the connection circuit comprises:

the drain electrode of the first NMOS tube is respectively connected with the source electrode of the second NMOS tube and the source electrode of the third NMOS tube, and the source electrode of the first NMOS tube is grounded;

the grid electrode of the second NMOS tube is electrically connected with the current comparison circuit, and the drain electrode of the second NMOS tube is connected with the latch circuit;

and the grid electrode of the third NMOS tube is electrically connected with the reference unit current generating circuit, and the drain electrode of the third NMOS tube is connected with the latch circuit.

3. The sense amplifier circuit of claim 2, wherein the latch circuit comprises:

a grid electrode of the third PMOS tube is respectively connected with a grid electrode of a fourth NMOS tube and a drain electrode of a fifth NMOS tube, a source electrode of the third PMOS tube is connected with a source electrode of the fourth PMOS tube, and a drain electrode of the third PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube;

the drain electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube;

the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube;

the source electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube;

and the buffer module is respectively and electrically connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, and is used for receiving and outputting logic signals.

4. The sense amplifier circuit of claim 3, further comprising a third equalization circuit, the third equalization circuit comprising:

a gate of the first PMOS transistor is connected to a gate of a second PMOS transistor, a source of the first PMOS transistor is connected to a source of the second PMOS transistor, a source of the third PMOS transistor and a source of the fourth PMOS transistor, respectively, and a drain of the first PMOS transistor is connected to a gate of the third PMOS transistor, a drain of the fourth PMOS transistor, a gate of the fourth NMOS transistor and a drain of the fifth NMOS transistor, respectively;

and the drain electrode of the second PMOS tube is respectively connected with the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube, the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the buffer module.

5. The sense amplifier circuit of claim 1, wherein the reference cell current generation circuit comprises:

a memory cell current generation circuit for generating a memory cell current;

the first pre-charging circuit is used for providing pre-charging voltage for the current generating circuit of the storage unit and providing pre-charging voltage for a connecting node of the fifth PMOS tube and the connecting circuit;

and the grid electrode of the fifth PMOS tube is respectively connected with the first pre-charging circuit, the current comparison circuit and the connecting circuit, the grid electrode of the fifth PMOS tube is also electrically connected with the drain electrode of the fifth PMOS tube, the source electrode of the fifth PMOS tube is connected with a power supply, and the fifth PMOS tube is used for providing voltage for the connecting node of the first pre-charging circuit and the connecting circuit, reversing the current of the storage unit, generating the current of the reference unit and transmitting the current to the current comparison circuit.

6. The sense amplifier circuit of claim 5, wherein the current comparison circuit comprises:

the input end of the trimming circuit is respectively connected with the first pre-charging circuit, the connecting circuit, the grid electrode of the fifth PMOS tube and the drain electrode of the fifth PMOS tube, the output end of the trimming circuit is respectively connected with the second pre-charging circuit and the connecting circuit, and the trimming circuit is used for trimming the reference unit current to generate the reference current;

one end of the second pre-charging circuit is connected with the unit current generating circuit, the other end of the second pre-charging circuit is respectively connected with the trimming circuit and the connecting circuit, and the second pre-charging circuit is used for providing pre-charging voltage for the unit current generating circuit and providing pre-charging voltage for a connecting node of the trimming circuit and the connecting circuit;

the unit current generation circuit is connected with the connecting circuit through the second pre-charging circuit and is used for generating unit current; and forming a reading voltage at a node where the second pre-charging circuit and the trimming circuit are connected with the connecting circuit according to the reference current and the unit current.

7. The sense amplifier circuit of claim 6, further comprising:

one end of the first equalization circuit is connected with the first pre-charging circuit, the grid electrode of the fifth PMOS tube, the drain electrode of the fifth PMOS tube and the connecting circuit respectively, the other end of the first equalization circuit is connected with the trimming circuit, the second pre-charging circuit and the connecting circuit respectively, and the first equalization circuit is used for balancing the node of the connecting circuit connected with the first pre-charging circuit and the node of the connecting circuit connected with the second pre-charging circuit to the same voltage.

8. The sense amplifier circuit of claim 7, further comprising:

and one end of the second equalizing circuit is respectively connected with the storage unit current generating circuit and the first pre-charging circuit, the other end of the second equalizing circuit is respectively connected with the unit current generating circuit and the second pre-charging circuit, and the second equalizing circuit is used for balancing the node of the storage unit current generating circuit connected with the first pre-charging circuit and the node of the unit current generating circuit connected with the second pre-charging circuit to the same voltage.

9. The sense amplifier circuit of claim 8, further comprising:

a first initialization circuit, one end of which is connected to the memory cell current generation circuit, the first pre-charge circuit and the second equalization circuit, and the other end of which is grounded, wherein the first initialization circuit is used for initializing the voltage of a connection node of the memory cell current generation circuit and the first pre-charge circuit to a preset voltage when reading of the memory array is finished;

and one end of the second initialization circuit is connected with the unit current generation circuit, the second pre-charge circuit and the second equalization circuit respectively, the other end of the second initialization circuit is grounded, and the second initialization circuit is used for initializing the voltage of a connection node of the unit current generation circuit and the second pre-charge circuit to a preset voltage under the condition that the reading of the memory array is finished.

10. A memory comprising the sense amplifier circuit of any of claims 1 to 9.

Technical Field

The present invention relates to the field of circuit integration technologies, and for example, to a sense amplifier circuit and a memory.

Background

When the task of reading the content of the memory is carried out, the sensitive amplifier adjusts the bit line voltage to a fixed value so as to stabilize the bit line voltage as soon as possible, and further can sense stable bit line current during reading, and the sensitive amplifier senses the signal change on the bit line and obtains a logic signal by amplifying the signal change so as to read the data stored in the memory unit. The sense amplifier circuit is an important component of the memory and directly influences the reading speed of the memory.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art:

in the prior art, a sense amplifier circuit performs voltage comparison signal change through a comparator to obtain data stored in a memory cell, and the sense amplifier circuit with the structure has a slow reading speed due to the fact that the comparator needs a certain reaction time, so that the reading speed of a memory is influenced.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.

The embodiment of the disclosure provides a sense amplifier circuit and a memory, so as to improve the reading speed of the memory.

In some embodiments, the sense amplifier circuit comprises: a reference cell current generating circuit for generating a reference cell current and a reference voltage; a current comparison circuit electrically connected to the reference cell current generation circuit, the current comparison circuit for converting the reference cell current into a reference current, generating a cell current in a case of reading the memory array, and forming a read voltage according to the reference current and the cell current; the latch circuit is electrically connected with the current comparison circuit and the reference unit current generation circuit through the connecting circuit respectively, and is used for acquiring the voltage difference between the reference voltage and the reading voltage and performing positive feedback on the voltage difference to obtain a logic signal; and the connecting circuit is used for conducting the reference unit current generating circuit and the latch circuit and conducting the current comparing circuit and the latch circuit when the memory array is read.

In some embodiments, the memory includes the sense amplifier circuit described above.

The sense amplifier circuit and the memory provided by the embodiment of the disclosure can realize the following technical effects: a reference cell current and a reference voltage generated by a reference cell current generation circuit; the current comparison circuit converts the reference unit current into a reference current, generates a unit current under the condition of reading the memory array, forms a read voltage according to the reference current and the unit current, and the latch circuit acquires the voltage difference between the reference voltage and the read voltage and performs positive feedback on the voltage difference to obtain a logic signal. Compared with the prior sensitive amplifier circuit in which the comparator needs longer response time, the latch circuit has faster response speed for performing positive feedback on the voltage difference, namely the latch circuit has shorter response time for performing positive feedback, thereby improving the reading speed of the memory.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:

FIG. 1 is a schematic diagram of a sense amplifier circuit according to an embodiment of the present disclosure;

fig. 2 is a timing diagram of a sense amplifier circuit during a read operation according to an embodiment of the disclosure.

Reference numerals:

1: a first NMOS (N-Metal-Oxide-Semiconductor) tube; 2: a second NMOS transistor; 3: a third NMOS transistor; 4: a third PMOS (positive channel Metal Oxide Semiconductor) transistor; 5: a fourth PMOS tube; 6: a fourth NMOS transistor; 7: a fifth NMOS transistor; 8: a first not gate; 9: a second not gate; 10: a first PMOS tube; 11: a second PMOS tube; 12: a fifth PMOS tube; 13: a sixth PMOS tube; 14: a seventh PMOS tube; 15: an eighth PMOS tube; 16: a ninth PMOS tube; 17: a tenth PMOS tube; 18: an eleventh PMOS tube; 19: a twelfth PMOS tube; 20: a thirteenth PMOS tube; 21: a fourteenth PMOS tube; 22: a fifteenth PMOS tube; 23: a first capacitor; 24: a reference flash memory cell; 25: an eighth NMOS transistor; 26: a seventh NMOS transistor; 27: a sixth NMOS transistor; 28: a second capacitor; 29: a flash memory unit; 30: an eleventh NMOS tube; 31: a tenth NMOS transistor; 32: a ninth NMOS transistor; 33: a twelfth NMOS tube; 34: a sixteenth PMOS tube; 35: a seventeenth PMOS tube; 36: a thirteenth NMOS tube; 37: a fourteenth NMOS transistor; 38: a fifteenth NMOS transistor; 39: a twenty-third NMOS transistor; 40: an eighteenth PMOS tube; 41: a nineteenth PMOS tube; 42: a sixteenth NMOS tube; 43: a seventeenth NMOS transistor; 44: an eighteenth NMOS tube; 45: a twentieth PMOS tube; 46: a nineteenth NMOS tube; 47: a twenty-first PMOS tube; 48: a twentieth NMOS transistor; 49: a twenty-second NMOS transistor; 50: a twenty-first NMOS transistor; 51: a latch circuit; 52: a connection circuit; 53: a third equalization circuit; 54: a trimming circuit; 55: a cell current generation circuit; 56: a first pre-charge circuit; 57: a second precharge circuit; 58: a first equalization circuit; 59: a second equalization circuit; 60: a first initialization circuit; 61: a second initialization circuit; 62: a memory cell current generation circuit.

Detailed Description

So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.

The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.

In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the disclosed embodiments and their examples and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art according to specific situations.

The term "plurality" means two or more unless otherwise specified.

In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

With reference to fig. 1, an embodiment of the present disclosure provides a sense amplifier circuit, including: a reference cell current generation circuit, a current comparison circuit, a latch circuit 51, and a connection circuit 52. A reference cell current generating circuit for generating a reference cell current and a reference voltage; a current comparison circuit electrically connected to the reference cell current generation circuit, the current comparison circuit for converting the reference cell current into a reference current, generating a cell current in a case of reading the memory array, and forming a read voltage according to the reference current and the cell current; the latch circuit 51 is electrically connected with the current comparison circuit and the reference unit current generation circuit 62 through the connection circuit 52, and the latch circuit 51 is used for acquiring the voltage difference between the reference voltage and the reading voltage and performing positive feedback on the voltage difference to obtain a logic signal; and a connection circuit 52 for turning on the reference cell current generation circuit and the latch circuit and turning on the current comparison circuit and the latch circuit in the case of reading the memory array.

By adopting the sensitive amplifier circuit provided by the embodiment of the disclosure, the reference unit current and the reference voltage are generated by the reference unit current generation circuit; the current comparison circuit converts the reference unit current into a reference current, generates a unit current under the condition of reading the memory array, forms a read voltage according to the reference current and the unit current, and the latch circuit acquires the voltage difference between the reference voltage and the read voltage and performs positive feedback on the voltage difference to obtain a logic signal. Compared with the prior sensitive amplifier circuit in which the comparator needs longer response time, the latch circuit has faster response speed for performing positive feedback on the voltage difference, namely the latch circuit has shorter response time for performing positive feedback, thereby improving the reading speed of the memory.

Optionally, the connection circuit 52 includes: the NMOS transistor comprises a first NMOS transistor 1, a second NMOS transistor 2 and a third NMOS transistor 3. The drain electrode of the first NMOS tube 1 is respectively connected with the source electrode of the second NMOS tube 2 and the source electrode of the third NMOS tube 3, and the source electrode of the first NMOS tube 1 is grounded; the grid electrode of the second NMOS tube 2 is electrically connected with the current comparison circuit, and the drain electrode of the second NMOS tube 2 is connected with the latch circuit 51; the gate of the third NMOS transistor 3 is electrically connected to the reference cell current generating circuit, and the drain of the third NMOS transistor 3 is connected to the latch circuit 51.

Under the condition of reading the memory array, the second NMOS tube and the current comparison circuit are in a conduction state, and the second NMOS tube and the latch circuit are in a conduction state, so that the current comparison circuit and the latch circuit are conducted. Under the condition of reading the memory array, the third NMOS tube and the reference unit current generating circuit are in a conducting state, and the third NMOS tube and the latch circuit are in a conducting state; the reference cell current generation circuit and the latch circuit are made conductive.

Alternatively, the latch circuit 51 includes: a third PMOS tube 4, a fourth PMOS tube 5, a fourth NMOS tube 6, a fifth NMOS tube 7 and a buffer module. The grid electrode of the third PMOS tube 4 is respectively connected with the grid electrode of the fourth NMOS tube 6 and the drain electrode of the fifth NMOS tube 7, the source electrode of the third PMOS tube 4 is connected with the source electrode of the fourth PMOS tube 5, and the drain electrode of the third PMOS tube 4 is respectively connected with the grid electrode of the fourth PMOS tube 5, the drain electrode of the fourth NMOS tube 6 and the grid electrode of the fifth NMOS tube 7; the drain electrode of the fourth PMOS tube 5 is connected with the grid electrode of the third PMOS tube 4; the source electrode of the fourth NMOS tube 6 is connected with the drain electrode of the second NMOS tube 2; the source electrode of the fifth NMOS tube 7 is connected with the drain electrode of the third NMOS tube 3. The buffer module is respectively and electrically connected with the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube, the drain electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube, and the buffer module is used for receiving and outputting logic signals. Optionally, the buffer module enhances the driving capability of the received logic signal and outputs the logic signal.

Optionally, the buffer module comprises: a first not gate 8 and a second not gate 9. The input end of the first not gate 8 is electrically connected with the drain electrode of the third PMOS transistor 4, the gate electrode of the fourth PMOS transistor 5, the drain electrode of the fourth NMOS transistor 6 and the gate electrode of the fifth NMOS transistor 7, respectively, and the output end of the first not gate 8 is electrically connected with the input end of the second not gate 9.

The obtained voltage difference between the reference voltage and the reading voltage is amplified through the latch circuit, positive feedback is achieved, and a logic signal is obtained. Meanwhile, the logic signal is buffered and output through the buffer module, and the reduction of the reading speed of the memory due to the overlarge load of a device for receiving the logic signal is avoided.

Optionally, the sense amplifier circuit further includes a third equalization circuit 53, and the third equalization circuit 53 includes: a first PMOS transistor 10 and a second PMOS transistor 11. The grid electrode of the first PMOS tube 10 is connected with the grid electrode of the second PMOS tube 11, the source electrode of the first PMOS tube 10 is respectively connected with the source electrode of the second PMOS tube 11, the source electrode of the third PMOS tube 4 and the source electrode of the fourth PMOS tube 5, and the drain electrode of the first PMOS tube 10 is respectively connected with the grid electrode of the third PMOS tube 4, the drain electrode of the fourth PMOS tube 5, the grid electrode of the fourth NMOS tube 6 and the drain electrode of the fifth NMOS tube 7; the drain electrode of the second PMOS transistor 11 is connected to the gate electrode of the fourth NMOS transistor 6, the gate electrode of the fifth NMOS transistor 7, the drain electrode of the third PMOS transistor 4, the gate electrode of the fourth PMOS transistor 5, and the buffer module, respectively. Optionally, the drain of the second PMOS transistor 11 is connected to the input terminal of the first not gate 8.

The third equalizing circuit enables the internal nodes of the latch circuit to be initially at the same potential, so that the latch circuit is in a sensitive state of voltage comparison, under the condition that the reading voltage and the reference voltage are different, the voltage difference can be quickly obtained, and the voltage difference is subjected to positive feedback to obtain a logic signal. The internal nodes of the latch circuit are initially set to the same potential through the third equalizing circuit, so that the speed of the latch circuit is increased when the voltage difference between the reading voltage and the reference voltage is acquired, and the reading speed of the memory is increased.

Optionally, the reference cell current generation circuit includes: the memory cell current generating circuit 62, the first pre-charge circuit 56 and the fifth PMOS transistor 12. One end of the first pre-charge circuit 56 is connected with the storage unit current generation circuit 62, the other end of the first pre-charge circuit 56 is connected with the fifth PMOS transistor 12 and the connection circuit 52, the gate of the fifth PMOS transistor 12 is connected with the first pre-charge circuit 56, the current comparison circuit and the connection circuit 52, the gate of the fifth PMOS transistor 12 is further electrically connected with the drain of the fifth PMOS transistor 12, and the source of the fifth PMOS transistor 12 is connected with the power supply; the memory unit current generating circuit is used for generating a memory unit current, the first pre-charging circuit is used for providing a pre-charging voltage for the memory unit current generating circuit and providing the pre-charging voltage for a connecting node of a fifth PMOS pipe and the connecting circuit, and the fifth PMOS pipe is used for providing a voltage for the connecting node of the first pre-charging circuit and the connecting circuit and reversing the memory unit current so as to generate a reference unit current and supply the reference unit current to the current comparing circuit. And forming a reference voltage at a connection node of the fifth PMOS tube and the connecting circuit, and transmitting the reference voltage to the latch circuit through the connecting circuit.

Optionally, the first precharge circuit 56 includes: a first clamp circuit and a twelfth NMOS transistor 33. The first clamp circuit includes: a sixteenth PMOS transistor 34, a seventeenth PMOS transistor 35, a thirteenth NMOS transistor 36, a fourteenth NMOS transistor 37, and a fifteenth NMOS transistor 38. The source electrode of the sixteenth PMOS transistor 34 is connected to the power supply, and the drain electrode of the sixteenth PMOS transistor 34 is connected to the source electrode of the seventeenth PMOS transistor 35; the grid electrode of the seventeenth PMOS tube 35 is respectively connected with the grid electrode of the thirteenth NMOS tube 36, the source electrode of the fifteenth NMOS tube 38 and the memory cell current generating circuit 62, and the drain electrode of the seventeenth PMOS tube 35 is respectively connected with the drain electrode of the fourteenth NMOS tube 37 and the grid electrode of the fifteenth NMOS tube 38; the source of the thirteenth NMOS tube 36 is grounded; the source of the fourteenth NMOS transistor 37 is grounded; the drain electrode of the fifteenth NMOS tube 38 is connected to the source electrode of the twelfth NMOS tube 33, the gate electrode of the fifth PMOS tube 12, the drain electrode of the fifth PMOS tube 12 and the gate electrode of the third NMOS tube 3, respectively; the drain of the twelfth NMOS transistor 33 is grounded.

Alternatively, the memory cell current generation circuit 62 includes: a first capacitor 23, a reference flash cell 24 and a first column decoding circuit. The first column decoding circuit includes: sixth NMOS transistor 27, seventh NMOS transistor 26, eighth NMOS transistor 25. The drain of the sixth NMOS transistor 27 is connected to the gate of the seventeenth PMOS transistor 35, the gate of the thirteenth NMOS transistor 36 and the source of the fifteenth NMOS transistor 38, respectively, and the source of the sixth NMOS transistor 27 is connected to the drain of the seventh NMOS transistor 26; the source electrode of the seventh NMOS transistor 26 is connected to the drain electrode of the eighth NMOS transistor 25; the source of the eighth NMOS transistor 25 is connected to one end of the first capacitor 23 and the first end of the reference flash memory cell 24, respectively; the other end of the first capacitor 23 is grounded; the second terminal of the reference flash cell 24 is grounded. Optionally, the gate of the sixth NMOS transistor 27, the gate of the seventh NMOS transistor 26, and the gate of the eighth NMOS transistor 25 are respectively connected to a third decoder, and the third end of the reference flash memory cell 24 is connected to the third decoder, where the third decoder is used to select the content of the reference flash memory cell to be read.

Optionally, the current comparison circuit comprises: a trimming circuit 54, a second precharge circuit 57, and a cell current generation circuit 55. The input end of the trimming circuit 54 is respectively connected with the first pre-charging circuit 56, the connecting circuit 52, the grid of the fifth PMOS transistor 12 and the drain of the fifth PMOS transistor 12, the output end of the trimming circuit 54 is respectively connected with the second pre-charging circuit 57 and the connecting circuit 52, one end of the second pre-charging circuit 57 is connected with the unit current generating circuit 55, the other end of the second pre-charging circuit 57 is respectively connected with the trimming circuit 54 and the connecting circuit 52, the unit current generating circuit 55 is connected with the connecting circuit 52 through the second pre-charging circuit 57, and the unit current generating circuit is used for generating unit current; the trimming circuit is used for trimming the reference unit current to generate the reference current, the second pre-charging circuit is used for providing a pre-charging voltage for the unit current generating circuit and providing the pre-charging voltage for a connecting node of the trimming circuit and the connecting circuit, and a reading voltage is formed at a node of the second pre-charging circuit, which is connected with the trimming circuit and the connecting circuit, according to the reference current and the unit current.

In the case of reading the memory array, the trimming circuit trims the reference cell current to generate the reference current. The read voltage is charged to a high potential in case the reference current is greater than the cell current, and to a low potential in case the reference current is less than the cell current. The reference current and the cell current are compared by a current comparison circuit to obtain a read voltage. Optionally, the voltage of the high potential is greater than the voltage of the low potential.

Optionally, the trimming circuit 54 includes: a sixth PMOS transistor 13, a seventh PMOS transistor 14, an eighth PMOS transistor 15, a ninth PMOS transistor 16, a tenth PMOS transistor 17, an eleventh PMOS transistor 18, a twelfth PMOS transistor 19, a thirteenth PMOS transistor 20, a fourteenth PMOS transistor 21, and a fifteenth PMOS transistor 22. The grid electrode of the sixth PMOS transistor 13 is connected to the grid electrode of the third NMOS transistor 3, the drain electrode of the fifteenth NMOS transistor 38, the source electrode of the twelfth NMOS transistor 33, the grid electrode of the fifth PMOS transistor 12, the drain electrode of the fifth PMOS transistor 12, the grid electrode of the seventh PMOS transistor 14, the grid electrode of the eighth PMOS transistor 15, the grid electrode of the ninth PMOS transistor 16 and the grid electrode of the tenth PMOS transistor 17 respectively; a source electrode of the sixth PMOS transistor 13, a source electrode of the seventh PMOS transistor 14, a source electrode of the eighth PMOS transistor 15, a source electrode of the ninth PMOS transistor 16, and a source electrode of the tenth PMOS transistor 17 are respectively connected to a power supply, a drain electrode of the sixth PMOS transistor 13 is connected to a source electrode of the eleventh PMOS transistor 18, a drain electrode of the seventh PMOS transistor 14 is connected to a source electrode of the twelfth PMOS transistor 19, a drain electrode of the eighth PMOS transistor 15 is connected to a source electrode of the thirteenth PMOS transistor 20, a drain electrode of the ninth PMOS transistor 16 is connected to a source electrode of the fourteenth PMOS transistor 21, and a drain electrode of the tenth PMOS transistor 17 is connected to a source electrode of the fifteenth PMOS transistor 22; the drain electrode of the eleventh PMOS transistor 18 is connected to the drain electrode of the twelfth PMOS transistor 19, the drain electrode of the thirteenth PMOS transistor 20, the drain electrode of the fourteenth PMOS transistor 21, the drain electrode of the fifteenth PMOS transistor 22, the second NMOS transistor 2 and the second precharge circuit 57, respectively. Optionally, a gate of the eleventh PMOS transistor 18, a gate of the twelfth PMOS transistor 19, a gate of the thirteenth PMOS transistor 20, a gate of the fourteenth PMOS transistor 21, and a gate of the fifteenth PMOS transistor 22 are respectively connected to a first decoder, where the first decoder is configured to control conduction of the eleventh PMOS transistor, the twelfth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, and the fifteenth PMOS transistor.

Optionally, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor are used for amplifying the reference unit current in proportion; and the eleventh PMOS tube, the twelfth PMOS tube, the thirteenth PMOS tube, the fourteenth PMOS tube and the fifteenth PMOS tube are used for controlling the on and off of the circuit.

The reference current proportional to the reference unit current is generated through the trimming circuit, the reference current proportion is adjustable, the reference current is uniformly distributed in the middle of the storage array and has the same bias condition with the selected storage unit in the reading process, and therefore the reference current can change along with the changes of the process, the temperature and the power supply voltage, the influence of the process, the temperature and the power supply voltage on the reference current is further reduced, the comparison window of the reference current and the unit current is enlarged, and the reading speed of the memory is further improved.

In some embodiments, by presetting the ratios of the sizes of the fifth PMOS transistor and the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor, the ratio of the trimming circuit to the reference unit current amplification is respectively: 2.5%, 5%, 10%, 20%, 40%, through making up the opening state of eleventh PMOS pipe, twelfth PMOS pipe, thirteenth PMOS pipe, fourteenth PMOS pipe and fifteenth PMOS pipe, make the reference current can be in the scope of 2.5% ~77.5% ~ s.

Alternatively, the second precharge circuit 57 includes: a second clamp and a twenty-third NMOS transistor 39. Optionally, the second clamp circuit comprises: an eighteenth PMOS transistor 40, a nineteenth PMOS transistor 41, a sixteenth NMOS transistor 42, a seventeenth NMOS transistor 43, and an eighteenth NMOS transistor 44. The source electrode of the eighteenth PMOS tube 40 is connected with the power supply, and the drain electrode of the eighteenth PMOS tube 40 is connected with the source electrode of the nineteenth PMOS tube 41; the grid electrode of the nineteenth PMOS transistor 41 is connected to the grid electrode of the sixteenth NMOS transistor 42, the source electrode of the eighteenth NMOS transistor 44 and the unit current generating circuit 55, respectively, and the drain electrode of the nineteenth PMOS transistor 41 is connected to the drain electrode of the sixteenth NMOS transistor 42, the drain electrode of the seventeenth NMOS transistor 43 and the grid electrode of the eighteenth NMOS transistor 44, respectively; the source of the seventeenth NMOS transistor 43 is grounded; the source of the sixteenth NMOS transistor 42 is grounded; the drain electrode of the eighteenth NMOS tube 44 is respectively connected with the source electrode of the twenty-third NMOS tube 39, the drain electrode of the eleventh PMOS tube 18, the drain electrode of the twelfth PMOS tube 19, the drain electrode of the thirteenth PMOS tube 20, the drain electrode of the fourteenth PMOS tube 21, the drain electrode of the fifteenth PMOS tube 22 and the gate electrode of the third NMOS tube 2; the drain of the twenty-third NMOS transistor 39 is grounded.

Alternatively, the cell current generation circuit 55 includes: the flash memory comprises a second capacitor 28, a flash memory unit 29 and a second column decoding circuit, wherein the second column decoding circuit comprises a ninth NMOS transistor 32, a tenth NMOS transistor 31 and an eleventh NMOS transistor 30. The drain of the ninth NMOS transistor 32 is connected to the gate of the nineteenth PMOS transistor 41, the gate of the sixteenth NMOS transistor 42, and the source of the eighteenth NMOS transistor 44, respectively, and the source of the ninth NMOS transistor 32 is connected to the drain of the tenth NMOS transistor 31; the source electrode of the tenth NMOS transistor 31 is connected to the drain electrode of the eleventh NMOS transistor 30; the source of the eleventh NMOS transistor 30 is connected to one end of the second capacitor 28 and the first end of the flash memory cell 29, respectively; the other end of the second capacitor 28 is grounded; the second terminal of the flash memory cell 29 is grounded. Optionally, the gate of the ninth NMOS transistor 32, the gate of the tenth NMOS transistor 31, and the gate of the eleventh NMOS transistor 30 are respectively connected to a second decoder, and the third end of the flash memory cell 29 is connected to the second decoder, where the second decoder is used to select the content of the flash memory cell to be read.

Optionally, the sense amplifier circuit further comprises: a first equalization circuit 58. One end of the first equalizing circuit 58 is connected to the first pre-charging circuit 56, the gate of the fifth PMOS transistor 12, the drain of the fifth PMOS transistor 12 and the connecting circuit 52, respectively, the other end of the first equalizing circuit 58 is connected to the trimming circuit 54, the second pre-charging circuit 57 and the connecting circuit 52, respectively, and the first equalizing circuit is configured to balance the node of the first pre-charging circuit connecting circuit and the node of the second pre-charging circuit connecting circuit to the same voltage.

Optionally, the first equalization circuit 58 includes: a twentieth PMOS transistor 45 and a nineteenth NMOS transistor 46. The source electrode of the twentieth PMOS transistor 45 is connected to the drain electrode of the nineteenth NMOS transistor 46, the drain electrode of the eleventh PMOS transistor 18, the drain electrode of the twelfth PMOS transistor 19, the drain electrode of the thirteenth PMOS transistor 20, the drain electrode of the fourteenth PMOS transistor 21, the drain electrode of the fifteenth PMOS transistor 22, the source electrode of the twenty-third NMOS transistor 39, the drain electrode of the eighteenth NMOS transistor 44 and the gate electrode of the third NMOS transistor 2, and the source electrode of the nineteenth NMOS transistor 46 is connected to the drain electrode of the twentieth PMOS transistor 45, the gate electrode of the fifth PMOS transistor 12, the drain electrode of the fifth PMOS transistor 12, the source electrode of the twelfth NMOS transistor 33, the gate electrode of the third NMOS transistor 3 and the drain electrode of the fifteenth NMOS transistor 38.

Optionally, the sense amplifier circuit further comprises: a second equalization circuit 59. One end of the second equalizing circuit 59 is connected to the memory cell current generating circuit 62 and the first precharge circuit 56, respectively, the other end of the second equalizing circuit 59 is connected to the cell current generating circuit 55 and the second precharge circuit 57, respectively, and the second equalizing circuit is configured to balance the node where the memory cell current generating circuit is connected to the first precharge circuit and the node where the cell current generating circuit is connected to the second precharge circuit to the same voltage.

Optionally, the second equalization circuit 59 includes: twenty-first PMOS transistor 47 and twenty-second NMOS transistor 48. The source electrode of the twenty-first PMOS transistor 47 is connected to the drain electrode of the twentieth NMOS transistor 48, the second initialization circuit, the gate electrode of the nineteenth PMOS transistor 41, the gate electrode of the sixteenth NMOS transistor 42, the source electrode of the eighteenth NMOS transistor 44, and the drain electrode of the ninth NMOS transistor 32; the drain of the twenty-first PMOS transistor 47 is connected to the source of the twentieth NMOS transistor 48, the gate of the seventeenth PMOS transistor 35, the gate of the thirteenth NMOS transistor 36, the source of the fifteenth NMOS transistor 38, and the drain of the sixth NMOS transistor 27.

In the pre-charging stage, the node of the first pre-charging circuit connecting circuit and the node of the second pre-charging circuit connecting circuit are balanced to the same voltage by the memory through the first equalizing circuit, and the node of the storage unit current generating circuit connecting the first pre-charging circuit and the node of the unit current generating circuit connecting the second pre-charging circuit are balanced to the same voltage by the second equalizing circuit, so that errors caused by voltage mismatch can be reduced, and the reading accuracy of the memory is improved.

Optionally, the sense amplifier circuit further comprises: a first initialization circuit and a second initialization circuit. One end of the first initialization circuit is respectively connected with the storage unit current generation circuit, the first pre-charging circuit and the second equalization circuit, the other end of the first initialization circuit is grounded, and the first initialization circuit is used for initializing the voltage of a connection node of the storage unit current generation circuit and the second pre-charging circuit to a preset voltage under the condition that the storage array is read; one end of the second initialization circuit is respectively connected with the unit current generation circuit, the second pre-charging circuit and the second equalization circuit, the other end of the second initialization circuit is grounded, and the second initialization circuit is used for initializing the voltage of a connection node of the unit current generation circuit and the second pre-charging circuit to a preset voltage under the condition that the reading of the storage array is finished.

When the reading of the memory array is finished, the latch circuit continues to operate to latch the read memory contents. The first initializing circuit initializes a voltage of a connection node of the memory cell current generating circuit and the second precharging circuit to a preset voltage, for example, 0. The second initializing circuit initializes a voltage of a connection node of the cell current generating circuit and the second precharging circuit to a preset voltage, for example, 0. Thus, the storage array can be ready for next reading, and the reading speed is improved.

Optionally, the first initialization circuit 60 includes: a twenty-second NMOS transistor 49. The drain of the twenty-second NMOS transistor 49 is connected to the drain of the twenty-first PMOS transistor 47, the source of the twentieth NMOS transistor 48, the gate of the seventeenth PMOS transistor 35, the gate of the thirteenth NMOS transistor 36, the source of the fifteenth NMOS transistor 38, and the drain of the sixth NMOS transistor 27, respectively, and the source of the twenty-second NMOS transistor 49 is grounded.

Optionally, the second initialization circuit 61 includes: the twenty-first NMOS transistor 50. The drain of the twenty-first NMOS transistor 50 is connected to the source of the twenty-first PMOS transistor 47, the drain of the twentieth NMOS transistor 48, the gate of the nineteenth PMOS transistor 41, the gate of the sixteenth NMOS transistor 42, the source of the eighteenth NMOS transistor 44, and the drain of the ninth NMOS transistor 32, respectively, and the source of the twenty-first NMOS transistor 50 is grounded.

In the case of reading the memory array, the read timing generation circuit is connected to the gate of the twentieth PMOS transistor 45, the gate of the nineteenth NMOS transistor 46, the gate of the twentieth NMOS transistor 39, the gate of the twelfth NMOS transistor 33, the gate of the first NMOS transistor 1, the gate of the first PMOS transistor 10, the gate of the second PMOS transistor 11, the gate of the eighteenth PMOS transistor 40, the gate of the seventeenth NMOS transistor 43, the gate of the twentieth NMOS transistor 48, the gate of the twenty first NMOS transistor 50, the gate of the twenty second NMOS transistor 49, the gate of the twenty first PMOS transistor 47, the gate of the sixteenth PMOS transistor 34, and the gate of the fourteenth NMOS transistor 37, respectively. The read timing generation circuit generates an RE pulse signal, which generates a detection signal ATD, and then generates a plurality of read control signals, such as PRE, PREb, SENb, SEN, and LAT. The read timing generation circuit sends the generated PRE control signal to the nineteenth NMOS transistor 46, the twenty-third NMOS transistor 39, the twelfth NMOS transistor 33, and the twentieth NMOS transistor 48; sending a PREb control signal to a twentieth PMOS tube 45, an eighteenth PMOS tube 40 and a twenty-first PMOS tube 47; sending a SENB control signal with a level completely opposite to that of SEN to an eighteenth PMOS tube 40, a seventeenth NMOS tube 43, a twenty-first NMOS tube 50, a twenty-second NMOS tube 49, a sixteenth PMOS tube 42 and a fourteenth NMOS tube 37; and sending the LAT control signal to a first NMOS transistor 1, a first PMOS transistor 10 and a second PMOS transistor 11.

In some embodiments, fig. 2 is a timing diagram of sense amplifier circuits in the case of a read operation of the memory, and in the case of receiving an ADDRESS signal ADDRESS, the second decoder starts selecting the contents of the flash memory cell to be read, and the third decoder starts selecting the contents of the reference flash memory cell to be read. The read timing generation circuit generates a detection signal ATD upon receiving the RE pulse signal, and then generates a plurality of read control signals, such as PRE, PREb, SENb, SEN, and LAT. In the precharge stage, i.e. when PRE is a positive pulse and PREb is a negative pulse, under the control of the second clamp circuit, the cell current generating circuit is precharged to a target voltage, for example, 0.4V to 0.8V, the target voltage is approximately equal to the threshold voltage of the tenth NMOS, the cell current generating circuit is also clamped to the target voltage by the first clamp circuit to form the reference cell current Irefcell, and the connection node between the connection circuit and the fifth PMOS transistor is charged to a high voltage by the twelfth NMOS. Under the condition that the first equalizing circuit is started, the voltage of a node of the first pre-charging circuit connecting connection circuit is equal to that of a node of the second pre-charging circuit connecting connection circuit, and under the condition that the second equalizing circuit is started, the voltage of the node of the storage unit current generating circuit connecting the first pre-charging circuit and the voltage of the node of the unit current generating circuit connecting the second pre-charging circuit are balanced to be equal to the same voltage, so that the stability and reliability of a current comparison stage are ensured, and the error caused by voltage mismatch is reduced.

When the PRE-charge stage is finished, namely PRE is low level, PREb is high level, namely under the condition of reading the memory array, the twenty-third NMOS tube and the twelfth NMOS tube are turned off, the current flowing through the eighteenth NMOS tube is unit current Isense, the current flowing through the fifteenth NMOS tube and the fifth PMOS tube is reference unit current Irefcell, the reference unit current is reversed through the fifth PMOS tube, the reversed reference voltage current is input to the trimming circuit, and the reference current Iref is generated through the trimming circuit. The read voltage at the Node E of the connection of the second precharge circuit and the connection circuit is completely determined by the memory cell current Isense and the reference current Iref. When Iref>Node E point voltage in IsenseIs charged to a high potential E (0); when Iref<Node E point voltage in IsenseIs pulled to the low potential E (1).

Under the condition that the latch control signal LAT is at a low level, the third equalizing circuit enables the internal nodes of the latch circuit to be at the same potential initially, under the condition that the latch control signal LAT is at a high level, due to the fact that the voltages of the internal nodes of the latch circuit are consistent, the latch circuit is in a sensitive state of voltage comparison, under the condition that the reading voltage and the reference voltage are different, the voltage difference can be obtained quickly, and the voltage difference is subjected to positive feedback to obtain the logic signal. The internal nodes of the latch circuit are initially set to the same potential through the third equalizing circuit, so that the speed of the latch circuit is increased when the voltage difference between the reading voltage and the reference voltage is acquired, and the reading speed of the memory is increased.

The reference current and the unit current are compared through the current comparison circuit to generate a read voltage REFE, after a large voltage difference is generated between the read voltage and the reference voltage, the LAT signal is pulled high, at the moment, the first PMOS tube and the first PMOS tube are in a closed state, and the first NMOS tube is in an open state. Because the reading voltage and the reference voltage are different, the current flowing through the second NMOS tube and the third NMOS tube is different, and finally the latch circuit can amplify the current difference and output a correct logic signal at the output end of the latch circuit, namely the DOUT end.

Alternatively, the read time Taa of the memory is obtained by calculating Taa = Tpre + T1+ T2. Where Taa is the read time, Tpre is the precharge time, T2 is the delay time of the latch circuit output, and T1 is the setup time of the read voltage. Because the latch circuit has faster response time when performing positive feedback, compared with the existing sensitive amplifier circuit, the value of T2 is greatly reduced, and the reading time is further reduced. And an additional output latch circuit is not needed, so that the reading speed of the memory is improved.

The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.