阅读说明：本技术 显示装置 (Display device ) 是由 李宗璨 李炫旭 朴相俊 宋明勳 洪光泽 于 2021-04-08 设计创作，主要内容包括：提供了一种显示装置。所述显示装置包括：多个第一堤,设置在基底上以在第一方向上延伸并且彼此间隔开；多个第一图案,设置在多个第一堤之间并且在第一方向上彼此间隔开；第一电极和第二电极,在第一方向上延伸并且设置在多个第一堤的不同的第一堤上并彼此间隔开；第一绝缘层,与多个第一图案叠置,设置在基底上,并且与第一电极和第二电极部分地叠置；以及多个发光元件,设置在第一绝缘层上,使得多个发光元件中的每个的第一端和第二端分别设置在第一电极和第二电极上。(A display device is provided. The display device includes: a plurality of first banks disposed on the substrate to extend in a first direction and spaced apart from each other; a plurality of first patterns disposed between the plurality of first banks and spaced apart from each other in a first direction; first and second electrodes extending in a first direction and disposed on different first banks of the plurality of first banks and spaced apart from each other; a first insulating layer overlapping the plurality of first patterns, disposed on the substrate, and partially overlapping the first and second electrodes; and a plurality of light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the plurality of light emitting elements are disposed on the first electrode and the second electrode, respectively.)

1. A display device, the display device comprising:

a plurality of first banks disposed on the substrate to extend in a first direction and spaced apart from each other;

A plurality of first patterns disposed between the plurality of first banks and spaced apart from each other in the first direction;

first and second electrodes extending in the first direction, disposed on different ones of the plurality of first banks, and spaced apart from each other;

a first insulating layer overlapping the plurality of first patterns, disposed on the substrate, and partially overlapping the first and second electrodes; and

a plurality of light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the plurality of light emitting elements are disposed on the first electrode and the second electrode, respectively, the plurality of light emitting elements including a first light emitting element disposed between the plurality of first patterns and not overlapping the plurality of first patterns in a thickness direction of the display device.

2. The display device according to claim 1,

the plurality of light emitting elements further include a second light emitting element overlapping the plurality of first patterns in the thickness direction of the display device,

a distance between the first light emitting element and the substrate is smaller than a distance between the second light emitting element and the substrate.

3. The display device according to claim 1, wherein a thickness of the plurality of first patterns is greater than a thickness of the first electrode and a thickness of the second electrode.

4. The display device of claim 3, wherein the thickness of the plurality of first patterns is less than a diameter of the plurality of light emitting elements.

5. The display device according to claim 1,

the plurality of first patterns are disposed between the first electrode and the second electrode, and

the width of the plurality of first patterns is smaller than a distance between the first electrode and the second electrode.

6. The display device according to claim 1,

the plurality of first patterns have a width greater than a distance between the first electrode and the second electrode, and

at least a portion of the first electrode and at least a portion of the second electrode are disposed on the plurality of first patterns.

7. The display device according to claim 1, further comprising:

a planarization layer disposed on the substrate, wherein the plurality of first banks and the first insulating layer are disposed on the planarization layer, and the plurality of first patterns and the planarization layer are integrated with each other.

8. The display device according to claim 1, wherein the plurality of first patterns overlap with a portion of the first electrode or the second electrode that does not overlap with the plurality of first banks and are arranged in the first direction.

9. The display device according to claim 8, wherein a first pattern of the plurality of first patterns overlapping the first electrode and a first pattern of the plurality of first patterns overlapping the second electrode are arranged parallel to a direction along which the first electrode and the second electrode are spaced apart from each other.

10. The display device according to claim 8, wherein a first pattern of the plurality of first patterns overlapping the first electrode and a first pattern of the plurality of first patterns overlapping the second electrode are arranged in an interleaved manner.

11. The display device according to claim 1, further comprising:

a first contact electrode disposed on the first electrode to electrically contact first ends of the plurality of light emitting elements; and

a second contact electrode disposed on the second electrode to electrically contact second ends of the plurality of light emitting elements.

12. The display device according to claim 11,

The first electrode includes: at least one curved portion extending in a second direction different from the first direction; an extension portion having a width greater than a width of the at least one bent portion; and at least one connection portion electrically connecting the at least one bent portion and the extension portion and extending in the first direction, and

the plurality of first patterns are disposed between the extension portion of the first electrode and the second electrode.

13. The display device according to claim 12,

the second electrode is symmetrical to the first electrode with respect to the plurality of first patterns disposed therebetween,

the plurality of first patterns are disposed between the extended portions of the first electrode and the extended portions of the second electrode, and

a first end and a second end of each of the plurality of light emitting elements are disposed on the extension portion of the first electrode and the extension portion of the second electrode, respectively.

14. The display device according to claim 12,

a first distance between the extended portion of the first electrode and the second electrode is smaller than a second distance between the at least one connection portion of the first electrode and the second electrode, and

A minimum distance between the at least one curved portion of the first electrode and the second electrode is greater than the first distance and less than the second distance.

15. A display device, the display device comprising:

a planarization layer disposed on the substrate;

a plurality of first banks disposed on the planarization layer and spaced apart from each other;

first and second electrodes disposed on different ones of the plurality of first banks and spaced apart from each other;

a first insulating layer disposed on the planarization layer and partially overlapping the first and second electrodes;

a first light emitting element disposed on the first insulating layer such that a first end and a second end of each of the first light emitting elements are disposed on the first electrode and the second electrode, respectively; and

second light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the second light emitting elements are disposed on the first electrode and the second electrode, respectively,

wherein a distance between the first light emitting element and the substrate is smaller than a distance between the second light emitting element and the substrate.

16. The display device according to claim 15,

the planarization layer includes a first pattern including a top surface partially protruding between the plurality of first banks, and

the second light emitting element is disposed on the first pattern.

17. The display device according to claim 16,

the planarization layer includes a portion between the plurality of first banks where the first pattern is not formed, and

the first light emitting element is disposed on the portion of the planarization layer where the first pattern is not formed.

18. The display device according to claim 15,

the planarization layer includes a recess between the plurality of first banks, a top surface of the planarization layer being depressed at the recess,

at least a portion of the first electrode and at least a portion of the second electrode are disposed in the recess, and

the first light emitting element is disposed in the recess.

19. The display device according to claim 18,

the planarization layer includes a portion between the plurality of first banks where the recess is not formed, and

the second light emitting element is disposed on the portion of the planarization layer where the recess is not formed.

20. The display device according to claim 15, further comprising:

a transistor disposed between the substrate and the planarization layer; and

a data conductive layer disposed between the transistor and the planarization layer and including a first voltage line and a second voltage line, wherein,

the first electrode is electrically connected to the first voltage line via the transistor, and

the second electrode is electrically connected to the second voltage line.

Technical Field

The present disclosure relates to a display device.

Background

With the development of multimedia, display devices have become very important, and various types of display devices, such as Organic Light Emitting Diode (OLED) display devices, Liquid Crystal Display (LCD) devices, and the like, have been used.

A display device, which is a device for displaying an image, includes a display panel (such as an OLED display panel or an LCD panel). The display panel may include light emitting elements such as Light Emitting Diodes (LEDs), and the LEDs may be classified into OLEDs using organic materials as fluorescent materials and inorganic LEDs (ileds) using inorganic materials as fluorescent materials.

Disclosure of Invention

Embodiments of the present disclosure provide a display device capable of minimizing the number of light emitting elements lost during the manufacture thereof.

Embodiments of the present disclosure provide a display device with improved alignment of light emitting elements on electrodes.

However, embodiments of the present disclosure are not limited to the embodiments set forth herein. The foregoing and other embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

In accordance with the foregoing and other embodiments of the present disclosure, there is provided a display device including a plurality of patterns disposed between banks on which electrodes are disposed. The patterns are disposed to be spaced apart from each other in a direction along which the electrodes and the banks extend, and thus a height difference may be formed between the banks. As with the banks, the patterns may provide a space in which the light emitting elements are arranged, and the light emitting elements may be guided to be placed between the patterns separated from each other during the manufacture of the display device.

Therefore, the number of light emitting elements that fail and are lost in connection with the electrode due to being disposed in the region other than the region between the banks can be minimized. In addition, since the light emitting element disposed between the patterns may have both ends thereof properly placed on the electrodes, alignment of the light emitting element may be improved.

Other features and embodiments may be apparent from the following detailed description, the accompanying drawings, and the claims.

According to an exemplary embodiment of the present disclosure, a display device may include: a plurality of first banks disposed on the substrate to extend in a first direction and spaced apart from each other; a plurality of first patterns disposed between the plurality of first banks and spaced apart from each other in a first direction; first and second electrodes extending in a first direction, disposed on different ones of the plurality of first banks, and spaced apart from each other; a first insulating layer overlapping the plurality of first patterns, disposed on the substrate, and partially overlapping the first and second electrodes; and a plurality of light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the plurality of light emitting elements are disposed on the first electrode and the second electrode, respectively, the plurality of light emitting elements including a first light emitting element disposed between the plurality of first patterns and not overlapping the plurality of first patterns in a thickness direction of the display device.

The plurality of light emitting elements may further include a second light emitting element overlapping the plurality of first patterns in a thickness direction of the display device, and a distance between the first light emitting element and the substrate may be smaller than a distance between the second light emitting element and the substrate.

The thickness of the plurality of first patterns may be greater than the thickness of the first electrode and the thickness of the second electrode.

The thickness of the plurality of first patterns may be less than a diameter of the plurality of light emitting elements.

The plurality of first patterns may be disposed between the first electrode and the second electrode, and a width of the plurality of first patterns may be smaller than a distance between the first electrode and the second electrode.

The plurality of first patterns may have a width greater than a distance between the first electrode and the second electrode, and at least a portion of the first electrode and at least a portion of the second electrode may be disposed on the plurality of first patterns.

The display device may further include a planarization layer disposed on the substrate. The plurality of first banks and the first insulating layer may be disposed on the planarization layer, and the plurality of first patterns and the planarization layer may be integrated with each other.

The plurality of first patterns may overlap portions of the first electrode or the second electrode that do not overlap the plurality of first banks and be arranged in the first direction.

The first pattern of the plurality of first patterns overlapping the first electrode and the first pattern of the plurality of first patterns overlapping the second electrode may be arranged in parallel to a direction along which the first electrode and the second electrode are spaced apart from each other.

The first pattern of the plurality of first patterns overlapping the first electrode and the first pattern of the plurality of first patterns overlapping the second electrode may be arranged in an interleaved manner.

The display device may further include a first contact electrode disposed on the first electrode to electrically contact the first ends of the plurality of light emitting elements, and a second contact electrode disposed on the second electrode to electrically contact the second ends of the plurality of light emitting elements.

The first electrode may include: at least one curved portion extending in a second direction different from the first direction; an extension portion having a width greater than a width of the at least one bent portion; and at least one connection portion electrically connecting the at least one bent portion and the extension portion and extending in the first direction, and a plurality of first patterns may be disposed between the extension portion of the first electrode and the second electrode.

The second electrode may be symmetrical to the first electrode with respect to a plurality of first patterns disposed therebetween, the plurality of first patterns may be disposed between the extension portion of the first electrode and the extension portion of the second electrode, and the first end and the second end of each of the plurality of light emitting elements may be disposed on the extension portion of the first electrode and the extension portion of the second electrode, respectively.

A first distance between the extended portion of the first electrode and the second electrode may be less than a second distance between the at least one connection portion of the first electrode and the second electrode, and a minimum distance between the at least one bent portion of the first electrode and the second electrode may be greater than the first distance and less than the second distance.

According to an exemplary embodiment of the present disclosure, a display device includes: a planarization layer disposed on the substrate; a plurality of first banks disposed on the planarization layer and spaced apart from each other; first and second electrodes disposed on different ones of the plurality of first banks and spaced apart from each other; a first insulating layer disposed on the planarization layer and partially overlapping the first and second electrodes; first light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the first light emitting elements are disposed on the first electrode and the second electrode, respectively; and second light emitting elements disposed on the first insulating layer such that a first end and a second end of each of the second light emitting elements are disposed on the first electrode and the second electrode, respectively, wherein a distance between the first light emitting element and the substrate is smaller than a distance between the second light emitting element and the substrate.

The planarization layer may include a first pattern including a top surface partially protruding between the plurality of first banks, and the second light emitting elements may be disposed on the first pattern.

The planarization layer may include a portion between the plurality of first banks where the first pattern is not formed, and the first light emitting element may be disposed on the portion of the planarization layer where the first pattern is not formed.

The planarization layer may include a recess between the plurality of first banks. The top surface of the planarization layer may be recessed, at least a portion of the first electrode and at least a portion of the second electrode may be disposed in the recess, and the first light emitting element may be disposed in the recess.

The planarization layer may include a portion between the plurality of first banks where the recess is not formed, and the second light emitting element may be disposed on the portion of the planarization layer where the recess is not formed.

The display device may further include: a transistor disposed between the substrate and the planarization layer; and a data conductive layer disposed between the transistor and the planarization layer and including a first voltage line and a second voltage line, wherein the first electrode may be electrically connected to the first voltage line via the transistor, and the second electrode may be electrically connected to the second voltage line.

Drawings

These and other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic plan view of a display device according to an embodiment of the present disclosure;

fig. 2 is a schematic plan view of a pixel of the display device of fig. 1;

FIG. 3 is a schematic cross-sectional view taken along line Q1-Q1', line Q2-Q2', and line Q3-Q3' of FIG. 2;

FIG. 4 is a schematic cross-sectional view taken along line Q4-Q4' of FIG. 2;

FIG. 5 is a schematic cross-sectional view taken along line Q5-Q5' of FIG. 2;

FIG. 6 is an enlarged schematic cross-sectional view of a portion QA of FIG. 4;

FIG. 7 is a schematic cross-sectional view taken along line Q6-Q6' of FIG. 2;

fig. 8 is a schematic partial cross-sectional view of a display device according to another embodiment of the present disclosure;

fig. 9 is a schematic perspective view of a light emitting element according to an embodiment of the present disclosure;

fig. 10 to 12 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure;

fig. 13 is a schematic plan view of a sub-pixel obtained by the process shown in fig. 12;

fig. 14 and 15 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure;

Fig. 16 is a schematic plan view of a sub-pixel obtained by the process shown in fig. 14 and 15;

fig. 17 to 19 are schematic cross-sectional views illustrating arrangements of light emitting elements and first patterns in the sub-pixel of fig. 16;

fig. 20 and 21 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure;

fig. 22-24 are schematic partial cross-sectional views of display devices according to other embodiments of the present disclosure;

fig. 25 and 26 are schematic partial cross-sectional views of display devices according to other embodiments of the present disclosure;

fig. 27 is a schematic partial cross-sectional view of a display device according to another embodiment of the present disclosure;

fig. 28 is a schematic plan view of a sub-pixel of the display device of fig. 27;

fig. 29 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure;

FIG. 30 is a schematic cross-sectional view taken along line QB-QB' of FIG. 29;

fig. 31 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure;

FIG. 32 is a schematic cross-sectional view taken along line QC-QC ', line QD-QD ', and line QE-QE ' of FIG. 31;

fig. 33 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure;

Fig. 34 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure; and

fig. 35 is a schematic sectional view taken along the line QX-QX' of fig. 34.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout the specification.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present invention. Similarly, a second element may also be referred to as a first element.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments will be described with reference to the accompanying drawings.

Fig. 1 is a schematic plan view of a display device according to an embodiment of the present disclosure.

As used herein, the terms "above … …", "top (top)" and "above … …" refer to a direction upward from display device 10 (i.e., one direction of third direction DR 3), and as used herein, the terms "below … …", "bottom (bottom)" and "below … …" refer to a direction downward from display device 10 (i.e., another direction of third direction DR 3). As used herein, the terms "left", "right", "upper" and "lower" refer to their respective directions as viewed from above the display device 10. For example, the terms "left", "right", "upper" and "lower" refer to one direction of the first direction DR1, another direction of the first direction DR1, one direction of the second direction DR2 and another direction of the second direction DR2, respectively.

Referring to fig. 1, a display device 10 displays a moving image or a still image. The display device 10 may refer to almost any type of electronic device that includes a display screen. Examples of the display device 10 may include a Television (TV), a notebook computer, a monitor, a billboard, an internet of things (IoT) device, a mobile phone, a smart phone, a tablet Personal Computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic organizer, an electronic book, a Portable Multimedia Player (PMP), a navigation device, a game console, a digital camera, and a video camera.

The display device 10 may include a display panel including a display screen. Examples of the display panel include an Inorganic Light Emitting Diode (ILED) display panel, an organic led (oled) display panel, a quantum dot light emitting diode (QLED) display panel, a Plasma Display Panel (PDP), and a Field Emission Display (FED) panel. The display panel of the display device 10 will be described hereinafter as an ILED display panel, but the present disclosure is not limited thereto.

The shape of the display device 10 may vary. For example, the display device 10 may have a rectangular shape that extends longer in the horizontal direction than in the vertical direction, a rectangular shape that extends longer in the vertical direction than in the horizontal direction, a square shape, a rectangular shape with rounded (rounded) corners, another polygonal shape, or a circular shape. The display area DPA of the display device 10 may have a shape similar to that of the display device 10. Fig. 1 shows that the display device 10 and the display area DPA have a rectangular shape extending longer in the horizontal direction than in the vertical direction.

The display device 10 may include a display area DPA and a non-display area NDA. The display region DPA is a region in which an image is displayed, and the non-display region NDA is a region in which an image is not displayed. The display region DPA may also be referred to as an active region, and the non-display region NDA may also be referred to as an inactive region. The display area DPA may substantially occupy a middle portion of the display apparatus 10.

The display area DPA may include pixels PX. The pixels PX may be arranged in a row direction and a column direction. The pixels PX may have a rectangular shape or a square shape in a plan view, but the present disclosure is not limited thereto. As another example, the pixels PX may have a tilted diamond shape with respect to the first direction DR1 or the second direction DR 2. As another example, the pixels PX may be in a stripe manner orThe mode is arranged. Each of the pixels PX may include one or more light emitting elements 30 (see fig. 2) emitting light of a predetermined wavelength range to emit light of a predetermined color.

The non-display area NDA may be disposed on the periphery of the display area DPA. The non-display area NDA may surround the entire display area DPA or a portion of the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a bezel of the display device 10. The wiring or the circuit driver included in the display device 10 may be disposed in the non-display area NDA, or an external device may be mounted in the non-display area NDA.

Fig. 2 is a schematic plan view of a pixel of the display device of fig. 1.

Referring to fig. 2, the pixel PX may include a subpixel PXn (where n is an integer of 1 to 3). For example, the pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX 3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. The first, second, and third colors may be blue, green, and red, respectively, but the present disclosure is not limited thereto. As another example, the subpixels PXn may emit the same color of light. Fig. 2 shows that the pixel PX includes three sub-pixels PXn, but the present disclosure is not limited thereto. As another example, the pixel PX may include more than three subpixels PXn.

Each of the subpixels PXn may include an emission area EMA and a non-emission area. The emission region EMA may be a region in which one or more light-emitting elements 30 are disposed to emit light of a specific wavelength range, and the non-emission region may be a region to which light emitted from the light-emitting elements 30 does not extend and from which light is therefore not emitted. The emission region EMA may include a region in which the light emitting element 30 is disposed and a region that outputs light emitted from the light emitting element 30.

However, the present disclosure is not limited thereto. The emission region EMA may further include a region in which light emitted from the light emitting element 30 is reflected or refracted by another element. The light emitting element 30 may be disposed in the subpixel PXn, and the emission area EMA including an area where the light emitting element 30 is disposed and an area adjacent to the area where the light emitting element 30 is disposed may be formed.

Each of the subpixels PXn may include a cutting area CBA disposed in the non-emission area. The cutting region CBA may be disposed on one side of the emission region EMA in the second direction DR 2. The cutting region CBA may be disposed between the emission regions EMA of a pair of adjacent subpixels PXn in the second direction DR 2. In the display area DPA of the display device 10, an emission area EMA and a cutting area CBA may be arranged. For example, the emission regions EMA and the cutting regions CBA may be arranged one after another in the first direction DR1, and the emission regions EMA and the cutting regions CBA may be alternately arranged in the second direction DR 2. The distance in the first direction DR1 between the cutting regions CBA may be smaller than the distance in the first direction DR1 between the emission regions EMA. The second bank (bank)45 may be disposed between the cutting region CBA and the emission region EMA, and a distance between the cutting region CBA and the emission region EMA may be determined by a width of the second bank 45. No light emitting element 30 is disposed in the cut regions CBA so that no light is emitted from the cut regions CBA, but the portions of the electrodes 21 and 22 disposed in each of the subpixels PXn may be disposed to be separated from each other in the corresponding cut regions CBA.

FIG. 3 is a schematic cross-sectional view taken along line Q1-Q1', line Q2-Q2', and line Q3-Q3' of FIG. 2. FIG. 4 is a schematic cross-sectional view taken along line Q4-Q4' of FIG. 2. FIG. 5 is a schematic cross-sectional view taken along line Q5-Q5' of FIG. 2. In particular, fig. 3 shows a schematic cross-sectional view of the first sub-pixel PX1 of fig. 2, but the structure of the first sub-pixel PX1 shown in fig. 3 may be directly applied to other pixels PX or other sub-pixels PXn. Fig. 3 shows a schematic cross-sectional view of the first and second light emitting elements 30A and 30B of the first sub-pixel PX1 taken along the first direction DR 1. Fig. 4 shows a schematic cross-sectional view of the first pattern 70 of the first sub-pixel PX1 on which no light emitting element 30 is disposed, and fig. 5 shows a schematic cross-sectional view of the first pattern 70 of the first sub-pixel PX1 on which a light emitting element 30 is disposed.

Referring to fig. 3 to 5 and with further reference to fig. 2, the display device 10 may include a first substrate 11 and a semiconductor layer, a conductive layer, and an insulating layer disposed on the first substrate 11.

The first substrate 11 may be an insulating substrate. The first substrate 11 may be formed of an insulating material such as glass, quartz, or polymer resin. In addition, the first substrate 11 may be a rigid substrate, but may be a bendable, foldable or rollable flexible substrate.

The light blocking layer BML may be disposed on the first substrate 11. The light blocking layer BML is disposed to overlap the active layer ACT of the first transistor TR 1. The light blocking layer BML may include a material capable of blocking light, and may prevent light from being incident on the active layer ACT of the first transistor TR 1. For example, the light blocking layer BML may be formed of an opaque metal capable of blocking the transmission of light, but the present disclosure is not limited thereto. In some embodiments, the light blocking layer BML may not be provided.

The buffer layer 12 may be disposed on the entire surface of the first substrate 11 and the light blocking layer BML. The buffer layer 12 may be formed on the first substrate 11 to protect the first transistor TR1, which is susceptible to moisture, from moisture that may penetrate the first substrate 11 and may perform a surface planarization function. The buffer layer 12 may include inorganic layers alternately stacked. For example, the buffer layer 12 may be formed as a multilayer film in which alternate stacks include silicon oxide (SiO)_x) Silicon nitride (SiN)_x) And silicon oxynitride (SiON).

The semiconductor layer is disposed on the buffer layer 12. The semiconductor layer may include the active layer ACT of the first transistor TR 1. The semiconductor layer may be disposed to partially overlap the gate electrode GE in the first gate conductive layer.

Fig. 3 shows only the first transistor TR1 of the first sub-pixel PX1, but the number of transistors included in the first sub-pixel PX1 is not particularly limited. The first subpixel PX1 may include more than one transistor. For example, the first sub-pixel PX1 may include more than one transistor, e.g., two or three transistors, including the first transistor TR 1.

The semiconductor layer may include polycrystalline silicon, single crystalline silicon, or an oxide semiconductor. In the case where the semiconductor layer includes an oxide semiconductor, the active layer ACT may include conductor regions ACT _ a and ACT _ b and a channel region ACT _ c between the conductor regions ACT _ a and ACT _ b. The oxide semiconductor may be an oxide semiconductor including indium (In). In some embodiments, the oxide semiconductor may be Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), Indium Gallium Oxide (IGO), Indium Zinc Tin Oxide (IZTO), Indium Gallium Tin Oxide (IGTO), Indium Gallium Zinc Oxide (IGZO), or Indium Gallium Zinc Tin Oxide (IGZTO), but the disclosure is not limited thereto.

As another example, the semiconductor layer may include polycrystalline silicon formed by crystallizing amorphous silicon. In this case, the conductor regions ACT _ a and ACT _ b of the active layer ACT may be regions doped with impurities.

The first gate insulating layer 13 is disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 may include a semiconductor layer, and may be disposed on the buffer layer 12. The first gate insulating layer 13 may function as a gate insulating film of each of the transistors. The first gate insulating layer 13 may be formed to include an inorganic material (such as in SiO)_x、SiN_xOr SiON, for example), or formed as SiO_x、SiN_xAnd/or a stack of SiON.

The first gate conductive layer is disposed on the first gate insulating layer 13. The first gate conductive layer may include the gate electrode GE of the first transistor TR1 and the first capacitor electrode CSE of the storage capacitor. The gate electrode GE may be disposed to overlap the channel region ACT _ c of the active layer ACT in a thickness direction. The first capacitor electrode CSE may be disposed to overlap the second source/drain electrode SD2 of the first transistor TR1 in the thickness direction. In some embodiments, the first capacitor electrode CSE may be connected to the gate electrode GE and integrated with the gate electrode GE into a single layer, and the single layer may partially include the gate electrode GE and the first capacitor electrode CSE. The first capacitor electrode CSE may be disposed to overlap the first source/drain electrode SD1 in the thickness direction, so that a storage capacitor may be formed between the first capacitor electrode CSE and the first source/drain electrode SD 1.

The first gate conductive layer may be formed as a single-layer film or a multi-layer film including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, but the present disclosure is not limited thereto.

A first passivation layer 15 is disposed on the first gate conductive layer. The first passivation layer 15 may cover or overlap the first gate conductive layer to protect the first gate conductive layer. The first passivation layer 15 may be formed to include an inorganic material (such as in SiO)_x、SiN_xOr SiON, for example), or formed as SiO_x、SiN_xAnd/or a stack of SiON.

The first data conductive layer is disposed on the first passivation layer 15. The first data conductive layer may include a first source/drain electrode SD1, a second source/drain electrode SD2, and a data line DTL.

The source/drain electrodes SD1 and SD2 of the first transistor TR1 may be in electrical contact with the conductor regions ACT _ a and ACT _ b of the active layer ACT via contact holes penetrating the first passivation layer 15 and the first gate insulating layer 13. The second source/drain electrode SD2 of the first transistor TR1 may be electrically connected to the light-blocking layer BML via another contact hole.

The data line DTL may apply a data signal to other transistors (not shown) of the first subpixel PX 1. Although not particularly shown, the data line DTL may be electrically connected to source/drain electrodes of other transistors and may transmit a data signal to the source/drain electrodes of the other transistors.

The first data conductive layer may be formed as a single layer film or a multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, but the present disclosure is not limited thereto.

The first interlayer insulating layer 17 is disposed on the first data conductive layer. The first interlayer insulating layer 17 may function as an insulating film between the first data conductive layer and a layer provided on the first data conductive layer. In addition, the first interlayer insulating layer 17 may cover or overlap the first data conductive layer to protect the first data conductive layer. The first interlayer insulating layer 17 may be formed to include an inorganic materialMaterial (such as in SiO)_x、SiN_xOr SiON, for example), or formed as SiO_x、SiN_xAnd/or a stack of SiON.

The second data conductive layer is disposed on the first interlayer insulating layer 17. The second data conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high potential voltage (or a first power supply voltage) supplied to the first transistor TR1 may be applied to the first voltage line VL1, and a low potential voltage (or a second power supply voltage) supplied to the second electrode 22 may be applied to the second voltage line VL 2. A light-emitting element alignment signal for aligning the light-emitting elements 30 may also be applied to the second voltage lines VL2 during the manufacture of the display device 10.

The first conductive pattern CDP may be electrically connected to the second source/drain electrode SD2 of the first transistor TR1 via a contact hole formed in the first interlayer insulating layer 17. The first conductive pattern CDP may be in electrical contact with a first electrode 21, which will be described below. The first transistor TR1 may transmit the first power supply voltage applied from the first voltage line VL1 to the first electrode 21 via the first conductive pattern CDP. The second data conductive layer is illustrated to include one first voltage line VL1 and one second voltage line VL2, but the present disclosure is not limited thereto. As another example, the second data conductive layer may include more than one first voltage line VL1 and more than one second voltage line VL 2.

The second data conductive layer may be formed as a single layer film or a multi-layer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof, but the present disclosure is not limited thereto.

The first planarization layer 19 is disposed on the second data conductive layer. The first planarization layer 19 may include an organic insulating material, such as Polyimide (PI) for example, and may perform a surface planarization function.

The first bank 40, the first pattern 70, the electrodes 21 and 22, the light emitting element 30, the second bank 45, and the contact electrodes 26 and 27 may be disposed on the first planarization layer 19. The insulating layers 51, 52, 53, and 54 may be further disposed on the first planarization layer 19.

The first bank 40 may be disposed directly on the first planarization layer 19. The first bank 40 may extend in the second direction DR2 within the first sub-pixel PX1, may not extend into an adjacent sub-pixel PXn of the first sub-pixel PX1 in the second direction DR2, and may be disposed in the emission area EMA of the first sub-pixel PX 1. The first dikes 40 may be disposed to be spaced apart from each other in the first direction DR1, and may form an area where the light emitting elements 30 are to be disposed. The first bank 40 may be disposed in each subpixel PXn to form a linear pattern in the display area DPA of the display apparatus 10. The two first banks 40 are illustrated as being disposed in the first subpixel PX1, but the present disclosure is not limited thereto. More than two first banks 40 may be disposed in the first subpixel PX1 according to the number of electrodes 21 and 22, which will be described below.

The first bank 40 may at least partially protrude from the top surface of the first planarization layer 19. The protruding portion of the first bank 40 may have an inclined side surface, and light emitted from the light emitting element 30 may travel toward the inclined side surface. The electrodes 21 and 22 disposed on the first bank 40 may include a material having a high reflectivity, and light emitted from the light emitting element 30 may be reflected to be emitted in an upward direction from the first planarization layer 19. For example, the first bank 40 may not only provide a region in which the light emitting element 30 is arranged, but also function as a reflective barrier capable of reflecting light emitted from the light emitting element 30 in an upward direction from the first planarizing layer 19. The side of the first bank 40 may be linearly inclined, but the present disclosure is not limited thereto. As another example, the first bank 40 may have a semicircular shape or an elliptical shape with a curved outer surface. The first bank 40 may include an organic insulating material (such as PI), but the present disclosure is not limited thereto.

The display device 10 may include a first pattern 70 disposed between the first banks 40. The first patterns 70 may have a width smaller than that of the first banks 40, and may be disposed to be spaced apart from each other in the second direction DR2 between the first banks 40. The width of the first pattern 70 may be less than the distance between the first banks 40, and the first pattern 70 may be spaced apart from the first banks 40. In some embodiments, the first pattern 70 and the first bank 40 may include the same material and may be formed simultaneously.

As already mentioned above, the first bank 40 may form an area where the light emitting element 30 is to be disposed. During the manufacture of the display device 10, ink having the light emitting elements 30 dispersed therein may be ejected on the electrodes 21 and 22, and the light emitting elements 30 may be disposed on the electrodes 21 and 22 by an electric field generated between the electrodes 21 and 22. Here, the first banks 40 may protrude from the top surface of the first planarization layer 19 to define a region between the first banks 40 and a region on the outside of the first banks 40, and the light emitting element 30 may be guided to be placed between the first banks 40. Similarly, the first pattern 70 disposed between the first banks 40 may generate a height difference in a region between the first banks 40 where the light emitting elements 30 are disposed. Accordingly, the region where the first patterns 70 are disposed may be distinguished from the region between the first patterns 70 spaced apart from each other in the second direction DR2, and the light emitting element 30 may be directed to be placed between the first patterns 70. As a result, the light emitting elements 30 may be densely arranged in a specific region between the first banks 40, and both ends of each of the light emitting elements 30 may be appropriately arranged on the electrodes 21 and 22. The first pattern 70 will be described in detail below.

Electrodes 21 and 22 are disposed on the first bank 40 and the first planarization layer 19. The electrodes 21 and 22 may include a first electrode 21 and a second electrode 22. The first and second electrodes 21 and 22 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR 1.

The first and second electrodes 21 and 22 may extend in the second direction DR2 in each subpixel PXn and may be separated from the other electrodes 21 and 22 by the cutting area CBA of the corresponding subpixel PXn. In some embodiments, the cutting area CBA may be disposed between the emission areas EMA of two adjacent subpixels PXn in the second direction DR2, and the first and second electrodes 21 and 22 of one of the two adjacent subpixels PXn may be separated from the first and second electrodes 21 and 22 of the other subpixel PXn, but the disclosure is not limited thereto. As another example, some of the electrodes 21 and 22 may not be segmented between the subpixels PXn, but may extend across the boundary between each pair of adjacent subpixels PXn in the second direction DR2, or only one of the first electrode 21 and the second electrode 22 may be segmented between the subpixels PXn.

The first electrode 21 may be electrically connected to the first transistor TR1 via a first contact hole CT1, and the second electrode 22 may be electrically connected to a second voltage line VL2 via a second contact hole CT 2. For example, the first electrode 21 may electrically contact the first conductive pattern CDP via a first contact hole CT1, the first contact hole CT1 penetrates the first planarization layer 19 in a region where the second bank 45 extends in the first direction DR1, and the second electrode 22 may electrically contact the second voltage line VL2 via a second contact hole CT2, the second contact hole CT2 penetrates the first planarization layer 19 in a region where the second bank 45 extends in the first direction DR 1. However, the present disclosure is not limited to this example. In another example, the first contact hole CT1 and the second contact hole CT2 may be disposed in the emission area EMA surrounded by the second bank 45 without overlapping the second bank 45.

One first electrode 21 and one second electrode 22 are shown as being disposed in each subpixel PXn, but the present disclosure is not limited thereto. More than one first electrode 21 and more than one second electrode 22 may be provided in each subpixel PXn. In addition, in each subpixel PXn, the first electrode 21 and the second electrode 22 may not necessarily extend in one direction, but may be arranged in various other ways. For example, the first electrode 21 and the second electrode 22 may be partially bent or bent, or one of the first electrode 21 and the second electrode 22 may be disposed to surround the other electrode.

The first and second electrodes 21 and 22 may be disposed on their respective first banks 40. In some embodiments, the first and second electrodes 21 and 22 may be formed to have a width greater than that of the first bank 40. For example, the first and second electrodes 21 and 22 may be formed to cover outer surfaces of their respective first banks 40. The first and second electrodes 21 and 22 may be disposed on sides of their respective first banks 40, and a distance between the first and second electrodes 21 and 22 may be smaller than a distance between the first banks 40. The first electrode 21 and the second electrode 22 may be at least partially disposed directly on the first planarization layer 19, and thus may be on the same plane.

The electrodes 21 and 22 may include a conductive material having a high reflectivity. For example, the electrodes 21 and 22 may include a metal having high reflectivity (such as Ag, Cu, or Al), or may include an alloy of Al, Ni, or La. The electrodes 21 and 22 may reflect light emitted from the light emitting element 30 to travel toward the side of the first bank 40 in an upward direction from each subpixel PXn.

However, the present disclosure is not limited thereto, and the electrodes 21 and 22 may further include a transparent conductive material. For example, the electrodes 21 and 22 may include a material such as ITO, IZO, or ITZO. In some embodiments, each of the electrodes 21 and 22 may form a structure in which the transparent conductive material and the metal having high reflectivity are stacked in more than one layer, or may be formed as a single layer including the transparent conductive material and the metal having high reflectivity. For example, each of the electrodes 21 and 22 may have a stack of ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The electrodes 21 and 22 may be electrically connected to the light emitting element 30, and a predetermined voltage may be applied to each of the electrodes 21 and 22 so that the light emitting element 30 may emit light. For example, the electrodes 21 and 22 may be electrically connected to the light emitting element 30 via contact electrodes 26 and 27 to be described below, and an electrical signal applied thereto may be transmitted to the light emitting element 30 via the contact electrodes 26 and 27.

One of the first electrode 21 and the second electrode 22 may be electrically connected to an anode electrode of the light emitting element 30, and the other of the first electrode 21 and the second electrode 22 may be electrically connected to a cathode electrode of the light emitting element 30. However, the present disclosure is not limited thereto. As another example, one of the first electrode 21 and the second electrode 22 may be electrically connected to a cathode electrode of the light emitting element 30, and the other of the first electrode 21 and the second electrode 22 may be electrically connected to an anode electrode of the light emitting element 30.

The electrodes 21 and 22 may be used to generate an electric field in each sub-pixel PXn to align the light emitting element 30. The light emitting element 30 may be disposed between the first electrode 21 and the second electrode 22 by an electric field formed between the first electrode 21 and the second electrode 22. The light emitting element 30 may be ejected on the electrodes 21 and 22 via inkjet printing. If ink including the light emitting element 30 is ejected on the electrodes 21 and 22, an alignment signal may be applied to the electrodes 21 and 22 to generate an electric field. The light emitting elements 30 dispersed in the ink may receive dielectrophoretic force from the electric field generated between the electrodes 21 and 22, and thus may be properly aligned on the electrodes 21 and 22.

The first insulating layer 51 is provided on the first planarizing layer 19. The first insulating layer 51 may be disposed to cover the first bank 40, the first and second electrodes 21 and 22, and the first pattern 70 over the first planarization layer 19, but to expose portions of the top surfaces of the first and second electrodes 21 and 22. In other words, the first insulating layer 51 may be formed substantially on the entire surface of the first planarization layer 19, and may include an opening (not shown) exposing portions of the first and second electrodes 21 and 22.

For example, a portion of the top surface of the first insulating layer 51 may be recessed between the first and second electrodes 21 and 22 to create a height difference. When the first insulating layer 51 is disposed to cover the first patterns 70 between the first banks 40, a height difference may be generated in a portion of the top surface of the first insulating layer 51 along a direction in which the first patterns 70 are arranged (i.e., along the second direction DR 2). Since the first insulating layer 51 is disposed to cover the first and second electrodes 21 and 22, a height difference may be generated even in a portion of the top surface of the first insulating layer 51 between the first and second electrodes 21 and 22 even in a region where the first pattern 70 is not disposed. However, the present disclosure is not limited thereto.

The first insulating layer 51 may protect the first electrode 21 and the second electrode 22, and may insulate the first electrode 21 and the second electrode 22 from each other. In addition, the first insulating layer 51 can prevent the light emitting element 30 provided on the first insulating layer 51 from being in direct contact with and damaged by other elements.

The second bank 45 may be disposed on the first insulating layer 51. The second bank 45 may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2 in a plan view, and may be arranged in a grid pattern over the entire surface of the display area DPA. The second bank 45 may be disposed along a boundary of each subpixel PXn to define each subpixel PXn.

The second bank 45 may be disposed to surround the emission area EMA and the cut area CBA of each subpixel PXn to separate the emission area EMA and the cut area CBA of each subpixel PXn. The first and second electrodes 21 and 22 may extend in the second direction DR2 across a portion of the second bank 45 extending in the first direction DR 1. The portion of the second bank 45 extending in the second direction DR2 may have a width between the emission areas EMA of each pair of adjacent subpixels PXn greater than a width between the cut areas CBA of each pair of adjacent subpixels PXn. Therefore, the distance between the cutting regions CBA may be smaller than the distance between the emission regions EMA.

The second bank 45 may be formed to have a height greater than that of the first bank 40. The second bank 45 may prevent ink from overflowing between different subpixels PXn during an inkjet printing process during the manufacture of the display device 10. The second bank 45 may separate the ink having the light emitting elements 30 dispersed therein between different subpixels PXn and may prevent mixing of the ink. The second bank 45 may include Polyimide (PI) as the first bank 40, but the present disclosure is not limited thereto.

The light emitting element 30 may be disposed on the first insulating layer 51. The light emitting elements 30 may be disposed to be spaced apart from each other in a direction along which the electrodes 21 and 22 extend (i.e., in the second direction DR 2), and may be aligned substantially parallel to each other. The distance between the light emitting elements 30 is not particularly limited. The light emitting element 30 may extend in one direction, and a direction along which the electrodes 21 and 22 extend may form substantially right angles with a direction along which the light emitting element 30 extends. However, the present disclosure is not limited thereto. As another example, the light emitting elements 30 may be arranged diagonally with respect to the direction in which the electrodes 21 and 22 extend.

The light emitting element 30 may include light emitting layers 36 (see fig. 9) having different materials, and may emit light of different wavelength ranges to the outside. The display device 10 may include light emitting elements 30 that emit light in different wavelength ranges. Accordingly, the first, second, and third sub-pixels PX1, PX2, and PX3 may emit light of the first, second, and third colors, respectively, but the disclosure is not limited thereto. As another example, the subpixels PXn may include the same type of light emitting elements 30 and may emit substantially the same color of light.

The light emitting element 30 may be disposed between the first banks 40 such that both ends of the light emitting element 30 may be placed on the electrodes 21 and 22. For example, a first end of the light emitting element 30 may be disposed on the first electrode 21, and a second end of the light emitting element 30 may be disposed on the second electrode 22. The length of the light emitting elements 30 may be greater than the distance between the first and second electrodes 21 and 22, and both ends of each of the light emitting elements 30 may be disposed on the first and second electrodes 21 and 22.

The light emitting elements 30 may be disposed between the first patterns 70 or on the first patterns 70. For example, the light emitting elements 30 may include first light emitting elements 30A disposed in regions where the first patterns 70 are not disposed and second light emitting elements 30B disposed on the first patterns 70. A first insulating layer 51 may be disposed between the first banks 40 and between the first and second electrodes 21 and 22 to cover the first pattern 70. The light emitting elements 30 disposed on the first insulating layer 51 may be disposed on portions of the first insulating layer 51 at positions relatively low between the first patterns 70, and at least some of the light emitting elements 30 may be disposed to overlap the first patterns 70 in a thickness direction. Fig. 3 shows a schematic cross-sectional view of one of the first light emitting elements 30A taken from one end to the other end, and fig. 5 shows a schematic cross-sectional view of one of the second light emitting elements 30B taken from one end to the other end. For example, the first patterns 70 may be disposed between the first banks 40 to create a height difference in the first insulating layer 51, and the light emitting elements 30 may include first light emitting elements 30A located at relatively low positions and second light emitting elements 30B located at relatively high positions. Although the first pattern 70 is provided, most of the light emitting elements 30 may be the first light emitting elements 30A located at relatively low positions. The first light emitting element 30A may be a light emitting element 30 guided by a height difference generated by the first pattern 70 such that both ends thereof are placed on the electrodes 21 and 22. Some of the light emitting elements 30 (e.g., the second light emitting elements 30B) may be located at relatively high positions (e.g., on the first patterns 70) and may be electrically connected to the first and second electrodes 21 and 22.

However, the present disclosure is not limited thereto. As another example, the light emitting elements 30 may not be disposed on the first patterns 70 according to the arrangement and shape of the first patterns 70, and this will be described below.

In each of the light emitting elements 30, a layer may be disposed in a direction perpendicular to the top surface of the first substrate 11 or the first planarizing layer 19. The light emitting elements 30 may be arranged such that a direction along which the light emitting elements 30 extend may be parallel to the first planarization layer 19, and the semiconductor layers included in each of the light emitting elements 30 may be sequentially disposed in a direction parallel to the top surface of the first planarization layer 19. However, the present disclosure is not limited thereto. As another example, the semiconductor layer included in each of the light emitting elements 30 may be disposed in a direction perpendicular to the first planarization layer 19.

Both ends of each of the light emitting elements 30 may be in electrical contact with the contact electrodes 26 and 27. For example, the insulating film 38 (see fig. 9) may not be formed on the end portion of each of the light emitting elements 30 so that some of the semiconductor layers included in each of the light emitting elements 30 may be exposed and thus may be in electrical contact with the contact electrodes 26 and 27, but the present disclosure is not limited thereto. As another example, the insulating film 38 may be removed from at least part of the light emitting elements 30 so that the side surface of the semiconductor layer of each of the light emitting elements 30 may be partially exposed at both ends of each of the light emitting elements 30 and thus may be in direct contact with the contact electrodes 26 and 27.

The second insulating layer 52 may be disposed on a portion of the light emitting element 30. For example, the second insulating layer 52 may be disposed to surround a portion of the outer surface of the light emitting elements 30, but not to cover both ends of each of the light emitting elements 30. The contact electrodes 26 and 27 may be in electrical contact with both ends of each of the light emitting elements 30, which are not covered with the second insulating layer 52. In a plan view, a portion of the second insulating layer 52 on the light emitting element 30 may be disposed on the first insulating layer 51 to extend in the second direction DR2, thus forming a linear pattern or an island pattern in the first sub-pixel PX 1. The second insulating layer 52 may protect and fix the light emitting element 30 during the manufacture of the display device 10.

The contact electrodes 26 and 27 and the third insulating layer 53 may be disposed on the second insulating layer 52.

The contact electrodes 26 and 27 may extend in one direction. The first and second contact electrodes 26 and 27 may be disposed on portions of the first and second electrodes 21 and 22, respectively. The first contact electrode 26 may be disposed on the first electrode 21, the second contact electrode 27 may be disposed on the second electrode 22, and the first and second contact electrodes 26 and 27 may extend in the second direction DR 2. The first and second contact electrodes 26 and 27 may be spaced apart from and face each other in the first direction DR1, and may form a stripe pattern in the emission area EMA of the first sub-pixel PX 1.

In some embodiments, the widths of the first and second contact electrodes 26 and 27 may be the same as or smaller than the widths of the first and second electrodes 21 and 22. The first and second contact electrodes 26 and 27 may be disposed to electrically contact both ends of each of the light emitting elements 30 and cover portions of the top surfaces of the first and second electrodes 21 and 22.

The contact electrodes 26 and 27 may be in electrical contact with the light emitting element 30 and the electrodes 21 and 22. The semiconductor layer included in each of the light emitting elements 30 may be exposed at both ends of each of the light emitting elements 30, and the first and second contact electrodes 26 and 27 may be electrically contacted with the light emitting elements 30 at both ends of each of the light emitting elements 30 at which the semiconductor layer is exposed. A first end of the light emitting element 30 may be electrically connected to the first electrode 21 via the first contact electrode 26, and a second end of the light emitting element 30 may be electrically connected to the second electrode 22 via the second contact electrode 27.

One first contact electrode 26 and one second contact electrode 27 are illustrated as being disposed in the first subpixel PX1, but the present disclosure is not limited thereto. The number of the first and second contact electrodes 26 and 27 may vary according to the number of the first and second electrodes 21 and 22 provided in the first subpixel PX 1.

The third insulating layer 53 is disposed on the first contact electrode 26. The third insulating layer 53 may electrically insulate the first contact electrode 26 and the second contact electrode 27 from each other. The third insulating layer 53 may be disposed to cover the first contact electrode 26, but may not be disposed on the second end of the light emitting element 30, so that the light emitting element 30 may be in electrical contact with the second contact electrode 27. The third insulating layer 53 may partially contact the first and second contact electrodes 26 and 27 on the top surface of the second insulating layer 52. A side surface of the third insulating layer 53 adjacent to the second electrode 22 or provided with the second electrode 22 may be aligned with a corresponding side surface of the second insulating layer 52. The third insulating layer 53 may also be disposed in the non-emission region of the first sub-pixel PX1, for example, on the first insulating layer 51 on the first planarization layer 19, but the present disclosure is not limited thereto.

The second contact electrode 27 is disposed on the second electrode 22, the second insulating layer 52, and the third insulating layer 53. The second contact electrode 27 may be in electrical contact with the second end of the light emitting element 30 and the exposed portion of the top surface of the second electrode 22. The second end of the light emitting element 30 may be electrically connected to the second electrode 22 via the second contact electrode 27.

The second contact electrode 27 may partially contact the second insulating layer 52, the third insulating layer 53, the second electrode 22, and the light emitting element 30. The first and second contact electrodes 26 and 27 may not be in contact with the second and third insulating layers 52 and 53, but the present disclosure is not limited thereto. In some embodiments, the third insulating layer 53 may not be provided.

The contact electrodes 26 and 27 may include a conductive material. The contact electrodes 26 and 27 may include ITO, IZO, ITZO, or Al. For example, the contact electrodes 26 and 27 may include a transparent conductive material, and light emitted from the light emitting element 30 may travel through the contact electrodes 26 and 27 toward the electrodes 26 and 27. However, the present disclosure is not limited thereto.

The fourth insulating layer 54 may be disposed on the entire surface of the first substrate 11. The fourth insulating layer 54 may protect elements disposed on the first substrate 11 from an external environment.

First insulating layer 51, second insulating layer 52, and third insulating layerThe insulating layer 53 and the fourth insulating layer 54 may include an inorganic insulating material or an organic insulating material. For example, the first, second, third, and fourth insulating layers 51, 52, 53, and 54 may include an inorganic insulating material (such as SiO)_x、SiN_xSilicon oxynitride (SiO) _xN_y) Alumina (Al)₂O₃) Or aluminum nitride (AlN)). In another example, the first, second, third, and fourth insulating layers 51, 52, 53, and 54 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene (polyphenylene) resin, a polyphenylene sulfide resin, benzocyclobutene, cardo resin, a siloxane resin, a silsesquioxane resin, polymethyl methacrylate, polycarbonate, or a polymethyl methacrylate-polycarbonate synthetic resin. However, the present disclosure is not limited to these examples.

Fig. 6 is an enlarged schematic cross-sectional view of a portion QA of fig. 4. FIG. 7 is a schematic cross-sectional view taken along line Q6-Q6' of FIG. 2. In particular, fig. 6 shows an enlarged schematic cross-sectional view of a portion provided with the first patterns 70 of fig. 4, and fig. 7 shows a schematic cross-sectional view of the light emitting elements 30 arranged in the second direction DR2 together with the first patterns 70 between the first banks 40.

Referring to fig. 6 and 7 and with further reference to fig. 3 to 5, the first patterns 70 may be disposed between the first banks 40 to be spaced apart from each other in the second direction DR 2. The first insulating layer 51 covering the first patterns 70 is disposed to conform to a height difference generated by the first patterns 70 disposed under the first insulating layer 51 between the first banks 40. During the manufacture of the display device 10, the ink including the light emitting element 30 may be ejected into the first subpixel PX1 after the first insulating layer 51 and the second bank 45 are formed. The light emitting element 30 may be ejected onto the electrodes 21 and 22 while being dispersed in the ink, and when the position and alignment direction of the light emitting element 30 are changed due to an electric field formed between the electrodes 21 and 22, the light emitting element 30 may be arranged such that both ends thereof may be placed on the electrodes 21 and 22.

The light emitting elements 30 dispersed in the ink may be randomly placed within the emission area EMA surrounded by the second bank 45, or may even be placed in an area other than the area between the first banks 40. The light emitting elements 30 placed in the regions other than the region between the first banks 40 may not be electrically connected to the electrodes 21 and 22 and may be lost during the manufacture of the display device 10. If the light emitting element 30 loss rate is high, the process yield may be reduced because a relatively large amount of ink needs to be ejected to maintain a predetermined number of light emitting elements 30 in each subpixel PXn.

Since the top surface of the first bank 40 protrudes from the first planarization layer 19, the emission area EMA may be appropriately defined, and a considerable number of light emitting elements 30 may be guided to be placed within the space defined by the first bank 40. Similarly, since the top surface of the first pattern 70 is raised from the first planarization layer 19, the region between the first banks 40 may be appropriately divided. The first insulating layer 51 may be located at a higher position on the first patterns 70 than between the first patterns 70, and if the positions of the light emitting elements 30 are changed due to an electric field, the light emitting elements 30 dispersed in the ink may be guided into regions where the first patterns 70 are spaced apart from each other. For example, as illustrated in fig. 6 and 7, the first insulating layer 51 may be located at a lower position between the first patterns 70 than on the first patterns 70 with respect to the top surface of the first substrate 11 or the top surface of the first planarization layer 19. Some of the light emitting elements 30 dispersed in the ink may be guided to be disposed on a portion of the first insulating layer 51 located at a relatively low position.

As with the first banks 40, the first pattern 70 may guide the light emitting elements 30 to be placed at specific positions in the emission area EMA, and as a result, a relatively large number of light emitting elements 30 may be arranged between the first banks 40. Accordingly, the number of light emitting elements 30 that may be lost during the manufacture of the display device 10 may be reduced, and the light emitting elements 30 may be disposed between the first banks 40 such that both ends thereof may be placed on the electrodes 21 and 22. As a result, any contact defect between the contact electrodes 26 and 27 and the light emitting element 30 can be prevented.

The light emitting element 30 may include a first light emitting element 30A disposed not to overlap the first pattern 70 in the thickness direction, and the first light emitting element 30A may be arranged such that both ends thereof may be placed on the first and second electrodes 21 and 22. The first light emitting element 30A may be aligned such that both ends thereof may be placed at desired positions. However, even if the light emitting element 30 is disposed on the first pattern 70, the light emitting element 30 may be electrically connected to the electrodes 21 and 22 as long as both ends of the light emitting element 30 may be properly electrically contacted with the contact electrodes 26 and 27.

The light emitting elements 30 may further include a second light emitting element 30B disposed to overlap the first pattern 70 in the thickness direction. Most of the light emitting elements 30 (i.e., the first light emitting elements 30A) may be disposed not to overlap the first patterns 70, but at least some of the light emitting elements 30 may be disposed on the first patterns 70 to electrically contact the contact electrodes 26 and 27. The second light emitting elements 30B may be disposed on the first patterns 70 to be located at a higher position than the first light emitting elements 30A. The first light emitting element 30A may be located at a lower position than the second light emitting element 30B with respect to the top surface of the first substrate 11 or the top surface of the first planarization layer 19. The height difference between the first and second light emitting elements 30A and 30B may vary according to the thickness of the first pattern 70.

The first patterns 70 may be thick enough to guide the light emitting elements 30 to be arranged between the first patterns 70 by a height difference generated between the first banks 40 by the first insulating layer 51. The thickness DP of the first pattern 70 may be greater than the thickness DE of the electrodes 21 and 22. Due to the presence of the electrodes 21 and 22, the first insulating layer 51 may generate a height difference between the first banks 40 with respect to the top surface of the first planarization layer 19. A portion of the first insulating layer 51 covering the first and second electrodes 21 and 22 may be located at a higher position than a portion of the first insulating layer 51 disposed on the top surface of the first planarization layer 19. Since the thickness DP of the first pattern 70 is greater than the thickness DE of the electrodes 21 and 22, a portion of the first insulating layer 51 disposed on the first pattern 70 may be located at a higher position than a portion of the first insulating layer 51 disposed on the first planarization layer 19 or the electrodes 21 and 22. The first pattern 70 may generate a significant height difference between the first banks 40, and as a result, may guide the light emitting elements 30 to be placed at specific positions.

For example, the width W1 of the first pattern 70 may be less than the distance W3 between the first and second electrodes 21 and 22, and the first pattern 70 may be disposed between the first and second electrodes 21 and 22. The electrodes 21 and 22 may be disposed to be spaced apart from both side surfaces of each of the first patterns 70, and a height difference generated between the electrodes 21 and 22 may effectively guide the light emitting element 30 to be placed at a specific position.

The width W1 of the first pattern 70 may be greater than the width W2 of the second insulation layer 52. The second insulating layer 52 may be disposed to surround a portion of the outer surface of the light emitting element 30, thus fixing the light emitting element 30. The width W2 of the second insulating layer 52 may be smaller than the length h of the light emitting elements 30 (see fig. 9) so that both ends of each of the light emitting elements 30 may be exposed to electrically contact the contact electrodes 26 and 27. The first pattern 70 may have such a predetermined width that even the second light emitting element 30B may be placed in parallel to the top surface of the first planarization layer 19. If the width W1 of the first pattern 70 is too small, the first insulating layer 51 disposed on the first pattern 70 may not provide a sufficient space for the arrangement of the second light emitting elements 30B, and the second light emitting elements 30B may be obliquely arranged. The first pattern 70 may be formed to have a width greater than that of the second insulating layer 52, and may provide a sufficient space for the second light emitting element 30B to be disposed thereon.

However, the width W1 and the thickness DP of the first pattern 70 are not particularly limited. As another example, the width W1 of the first pattern 70 may be equal to or greater than the distance W3 between the first and second electrodes 21 and 22, and may even be greater than the length h of the light emitting element 30. The first pattern 70 and the first bank 40 may be simultaneously formed, or the first pattern 70 may be formed by separate patterning after the first bank 40 is formed. In some embodiments, the first pattern 70 may be integrally formed with the first planarization layer 19 disposed under the first pattern 70.

The display device 10 may include a first pattern 70 disposed between the first banks 40 in one direction. During the manufacture of the display apparatus 10, most of the light emitting elements 30 may be guided to be aligned at specific positions, and the number of light emitting elements 30 that may be lost from each sub-pixel PXn may be minimized.

Fig. 8 is a schematic partial cross-sectional view of a display device according to another embodiment of the present disclosure. As with fig. 4, fig. 8 shows a schematic cross-sectional view of the first pattern 70 on which no light emitting element 30 is disposed.

Referring to fig. 8, the display device 10 may not include the third insulating layer 53 of fig. 4. The second contact electrode 27 may be directly disposed on a portion of the second insulating layer 52, and the first and second contact electrodes 26 and 27 may be spaced apart from each other over the second insulating layer 52. Even if the display device 10 does not include the third insulating layer 53, the second insulating layer 52 includes an organic insulating material and can fix the light emitting element 30. The first contact electrode 26 and the second contact electrode 27 may be simultaneously formed through a patterning process. The embodiment of fig. 8 is almost the same as the embodiment of fig. 4 except that the third insulating layer 53 is not provided, and thus, a detailed description thereof will be omitted.

Fig. 9 is a schematic perspective view of a light emitting element according to an embodiment of the present disclosure.

Referring to fig. 9, the light emitting element 30 may be a Light Emitting Diode (LED), and in particular, an ILED having a size of several micrometers to several nanometers and formed of an inorganic material. An ILED may be aligned between two electrodes formed with a polarity if an electric field is formed between the two opposing electrodes in a particular direction. The light emitting elements 30 may be aligned by an electric field formed between two electrodes.

The light emitting element 30 may have a shape extending in one direction. The light emitting element 30 may have the shape of a rod, a wire, or a tube. For example, the light emitting element 30 may have a cylindrical shape or a rod shape, but the present disclosure is not limited thereto. In another example, the light emitting element 30 may have a polygonal column shape such as a regular cube, a rectangular parallelepiped, or a hexagonal column, or may have a shape extending in one direction and having a partially inclined outer surface. The semiconductors included in the light emitting element 30 may be sequentially disposed or stacked in a direction along which the light emitting element 30 extends.

The light emitting element 30 may include a semiconductor layer doped with impurities of any conductivity type (e.g., p-type or n-type). The semiconductor layer may receive an electrical signal from an external power source to emit light of a specific wavelength range.

Referring to fig. 9, the light emitting element 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

The first semiconductor layer 31 may include an n-type semiconductor. For example, in the case where the light emitting element 30 emits light in the blue wavelength range, the first semiconductor layer 31 may include a semiconductor material Al_xGa_yIn_1-x-yN (wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x + y is more than or equal to 0 and less than or equal to 1). For example, the semiconductor material Al_xGa_yIn_1-x-yThe N may be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an N-type dopant. The first semiconductor layer 31 may be doped with an n-type dopant, and the n-type dopant may be, for example, Si, Ge, or Sn. For example, the first semiconductor layer 31 may be n-GaN doped with n-type Si. The first semiconductor layer 31 may have a length of about 1.5 μm to about 5 μm, but the present disclosure is not limited thereto.

The second semiconductor layer 32 is disposed on the light emitting layer 36. The second semiconductor layer 32 may include a p-type semiconductor. For example, in the case where the light emitting element 30 emits light in a blue wavelength range or a green wavelength range, the second semiconductor layer 32 may include a semiconductor material Al_xGa_yIn_1-x-yN (wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x + y is more than or equal to 0 and less than or equal to 1). For example, the semiconductor material Al _xGa_yIn_1-x-yThe N may be at least one of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The second semiconductor layer 32 may be doped with a p-type dopant, and the p-type dopant may be, for example, Mg, Zn, Ca, Se, or Ba. For example, the second semiconductor layer 32 may be p-GaN doped with p-type Mg. The second semiconductor layer 32 may have a length of about 0.05 μm to about 0.10 μm, but the present disclosure is not limited thereto.

The first semiconductor layer 31 and the second semiconductor layer 32 are illustrated as being formed as a single-layer film, but the present disclosure is not limited thereto. As another example, each of the first and second semiconductor layers 31 and 32 may include more than one layer, such as a cladding layer or a tensile strain barrier lowering (TSBR) layer, for example, depending on the material of the light emitting layer 36.

The light emitting layer 36 is provided between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a single quantum well structure material or a multiple quantum well structure material. In the case where the light emitting layer 36 includes a material having a multiple quantum well structure, the light emitting layer 36 may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The light emitting layer 36 can emit light by combining electron-hole pairs according to an electrical signal applied thereto through the first semiconductor layer 31 and the second semiconductor layer 32. For example, in the case where the light emitting layer 36 emits light in the blue wavelength range, the quantum layer may include a material such as AlGaN or AlGaInN. Specifically, in the case where the light emitting layer 36 has a multiple quantum well structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked, the quantum layers may include a material such as AlGaN or AlGaInN, and the well layers may include a material such as GaN or AlInN. In the case where the light emitting layer 36 includes AlGaInN as its quantum layer and AlInN as its well layer, the light emitting layer 36 may emit blue light having a central wavelength range of about 450nm to about 495 nm.

However, the present disclosure is not limited thereto. As another example, the light emitting layer 36 may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include a group III or group V semiconductor material according to the wavelength of light to be emitted. The type of light emitted by the light-emitting layer 36 is not particularly limited. The light emitting layer 36 may emit light in a red wavelength range or a green wavelength range instead of blue light as needed. The light emitting layer 36 may have a length of about 0.05 μm to about 0.10 μm, but the present disclosure is not limited thereto.

Light may be emitted not only from the circumferential surface of the light emitting element 30 in the longitudinal direction but also from both sides of the light emitting element 30. The directivity of light emitted from the light-emitting layer 36 is not particularly limited.

The electrode layer 37 may be an ohmic contact electrode, but the present disclosure is not limited thereto. As another example, the electrode layer 37 may be a Schottky (Schottky) contact electrode. The light emitting element 30 may include at least one electrode layer 37. Fig. 9 shows that the light emitting element 30 includes one electrode layer 37, but the present disclosure is not limited thereto. As another example, the light emitting element 30 may include more than one electrode layer 37, or the electrode layer 37 may not be provided. However, the following description of the light emitting element 30 may be directly applied to the light emitting element 30 having more than one electrode layer 37 or the light emitting element 30 having a structure different from that of the light emitting element 30 of fig. 9.

The electrode layer 37 can reduce the resistance between the light emitting element 30 and the electrode (or the contact electrode) if the light emitting element 30 is electrically connected to the electrode (or the contact electrode). The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of Al, Ti, In, Au, Ag, ITO, IZO, and ITZO. In addition, the electrode layer 37 may include a semiconductor material doped with an n-type dopant or a p-type dopant. The present disclosure is not so limited.

The insulating film 38 is provided so as to surround the first and second semiconductor layers 31 and 32 and the electrode layer 37. For example, the insulating film 38 may be provided so as to surround at least the light emitting layer 36, and may extend in a direction along which the light emitting element 30 extends. The insulating film 38 may protect the first semiconductor layer 31, the light emitting layer 36, the second semiconductor layer 32, and the electrode layer 37. For example, the insulating film 38 may be formed to surround the side faces of the first semiconductor layer 31, the light emitting layer 36, the second semiconductor layer 32, and the electrode layer 37, but to expose both ends of the light emitting element 30 in the length direction.

The insulating film 38 is illustrated as being formed to extend in the length direction of the light emitting element 30 and cover the side surfaces of the first semiconductor layer 31, the light emitting layer 36, the second semiconductor layer 32, and the electrode layer 37, but the present disclosure is not limited thereto. The insulating film 38 may cover only the side surfaces of the light emitting layer 36 and some of the first semiconductor layer 31 and the second semiconductor layer 32, or may cover only a part of the side surface of the electrode layer 37, so that the side surface of the electrode layer 37 may be partially exposed. The insulating film 38 may be formed to be circular in a cross-sectional view in a region adjacent to at least one end of the light emitting element 30.

The insulating film 38 may have a thickness of about 10nm to about 1.0 μm, but the present disclosure is not limited thereto. The insulating film 38 may have a thickness of about 40 nm.

The insulating film 38 may include a material having insulating properties, such as SiO_x、SiN_x、SiO_xN_yAlN or Al₂O₃For example. Accordingly, the insulating film 38 can prevent any short circuit that may occur if the light emitting layer 36 is placed in direct contact with an electrode that transmits an electrical signal directly to the light emitting element 30. Since the insulating film 38 protects the outer surface of the light emitting element 30 including the light emitting layer 36, any deterioration in the emission efficiency of the light emitting element 30 can be prevented.

In some embodiments, the outer surface of the insulating film 38 may be subjected to a surface treatment. The light emitting elements 30 may be ejected on the electrodes while being dispersed in a predetermined ink. Here, the surface of the insulating film 38 may be subjected to hydrophobic treatment or hydrophilic treatment to keep the light emitting elements 30 dispersed in the ink from aggregating with other adjacent light emitting elements 30.

The length h of the light emitting element 30 may be in a range of about 1 μm to about 10 μm, about 2 μm to about 6 μm, or about 3 μm to about 5 μm. The light emitting element 30 may have a diameter of about 30nm to about 700nm, and may have an aspect ratio of 1.2 to 100, but the present disclosure is not limited thereto. Different light-emitting elements 30 included in the display device 10 may have different diameters depending on the composition of the respective light-emitting layers 36 of the light-emitting elements 30. Preferably, the light emitting element 30 may have a diameter of about 500 nm.

A method of manufacturing the display device 10 will be described below.

Fig. 10 to 12 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure. Fig. 13 is a schematic plan view of a sub-pixel obtained by the process illustrated in fig. 12.

Referring first to fig. 10, a target substrate SUB on which the first insulating layer 51 and the electrodes 21 and 22 are to be disposed is prepared. Although not particularly shown, the target substrate SUB may include the first substrate 11, and may further include circuit elements including a conductive layer and an insulating layer. For convenience, the first substrate 11 and the circuit elements are hereinafter collectively referred to as a target substrate SUB.

Thereafter, the first banks 40 are formed to be spaced apart from each other on the target substrate SUB. As already mentioned above, the first bank 40 may protrude from the top surface of the target substrate SUB.

Thereafter, referring to fig. 11, a first pattern 70 is formed between the first banks 40 on the target substrate SUB. The first pattern 70 may be spaced apart from the first bank 40 and may have a thickness smaller than that of the first bank 40. The first pattern 70 is illustrated as being formed after the first bank 40 is formed, but the present disclosure is not limited thereto. As another example, the first pattern 70 and the first bank 40 may include the same material and may be formed simultaneously. For example, the first bank 40 and the first pattern 70 having a thickness different from that of the first bank 40 may be simultaneously formed using a half-tone mask during the formation of the first bank 40.

Thereafter, referring to fig. 12 and 13, a first electrode layer 21 'and a second electrode layer 22' are formed on the first bank 40. The first and second electrode layers 21 'and 22' extend in the second direction DR2 and are spaced apart from each other with the first pattern 70 between the first and second electrode layers 21 'and 22'. During the manufacture of the display device 10, the first electrode layer 21 'and the second electrode layer 22' may extend in the second direction DR2 to be disposed in the other sub-pixels PXn. After the light emitting element 30 is disposed, the first electrode layer 21 'and the second electrode layer 22' may be cut in the cutting region CBA of each sub-pixel PXn, and then the first electrode layer 21 'and the second electrode layer 22' may be formed as the first electrode 21 and the second electrode 22, respectively.

The first patterns 70 may be arranged to be spaced apart from each other in the second direction DR2 between the first banks 40 or between the first electrode layer 21 'and the second electrode layer 22'. An area between the first banks 40 may be divided into an area where the first patterns 70 are disposed and an area where the first patterns 70 are not disposed, and the area where the first patterns 70 are disposed may have a height different from that of the area where the first patterns 70 are not disposed. Thereafter, a first insulating layer 51 covering the first pattern 70 and the first and second electrode layers 21 'and 22' and a second bank 45 disposed on the first insulating layer 51 are formed, and the light emitting element 30 is disposed between the first banks 40.

Fig. 14 and 15 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure.

Referring to fig. 14 and 15, a first insulating material layer 51 'covering the first pattern 70 and the electrode layers 21' and 22 'is formed, and a second bank 45 disposed on the first insulating material layer 51' and surrounding the emission area EMA and the cutting area CBA of each subpixel PXn is formed. The first insulating material layer 51' may be disposed on the entire surface of the target substrate SUB and may cover the first pattern 70 and the electrode layers 21' and 22 '. The first insulating material layer 51' may be partially removed in a subsequent process so that the top surfaces of the electrode layers 21' and 22' may be exposed, and as a result, the first insulating layer 51 may be formed. As already mentioned above, the second bank 45 may be disposed to surround and separate each sub-pixel PXn, and may also separate the emission area EMA and the cut area CBA of each sub-pixel PXn.

Fig. 16 is a schematic plan view of a sub-pixel obtained by the process illustrated in fig. 14 and 15. Fig. 17 to 19 are schematic cross-sectional views illustrating arrangements of the light emitting element and the first pattern in the sub-pixel of fig. 16. In particular, fig. 17 shows the light emitting elements 30 disposed in the regions where the first patterns 70 are not disposed, and fig. 18 shows the light emitting elements 30 disposed in the regions where the first patterns 70 are disposed. Fig. 19 shows light-emitting elements 30 arranged between first patterns 70, the first patterns 70 being spaced apart from each other in the second direction DR 2.

Referring to fig. 16 to 19, the light emitting element 30 is disposed between the first banks 40. The light emitting element 30 may be disposed such that both ends of the light emitting element 30 may be placed on the first electrode layer 21 'and the second electrode layer 22'. The light emitting elements 30 may be ejected onto the target substrate SUB while being dispersed in the ink. For example, the light emitting elements 30 may be prepared to be dispersed in ink and then may be ejected onto the target substrate SUB through a printing process using an inkjet printing apparatus. The ink ejected by the inkjet printing apparatus may settle in each region surrounded by the second bank 45. The second bank 45 may prevent ink from overflowing between different sub-pixels PXn.

Once the ink including the light emitting element 30 is ejected, the light emitting element 30 may be disposed on the first insulating material layer 51' by applying an electrical signal to the electrode layers 21' and 22 '. When an electrical signal is applied to the electrode layers 21 'and 22', an electric field may be generated between the electrode layers 21 'and 22'. The light emitting elements 30 dispersed in the ink may receive dielectrophoretic force from the electric field, and as a result, the alignment direction and position of the light emitting elements 30 may be changed so that the light emitting elements 30 may be settled on the first insulating material layer 51'. Here, some of the light emitting elements 30 (i.e., the light emitting elements 30A) may be disposed between the first patterns 70 as illustrated in fig. 17, and some of the light emitting elements 30 (e.g., the light emitting elements 30B) may be disposed on the first patterns 70 as illustrated in fig. 18. In addition, some of the first patterns 70 may not have the light emitting elements 30 disposed thereon. The first pattern 70 may guide the light emitting elements 30 to be placed such that each of both ends of each of the light emitting elements 30 may be disposed on a corresponding one of the electrodes 21 and 22 or on a corresponding one of the electrode layers 21 'and 22', and most of the light emitting elements 30 may be disposed at a relatively lower position than the first pattern 70. However, as illustrated in fig. 5, at least some of the light emitting elements 30 may be disposed on the first pattern 70, and even these light emitting elements 30 may be electrically connected to the electrodes 21 and 22 via the contact electrodes 26 and 27.

Fig. 20 and 21 are schematic cross-sectional views illustrating processes of a method of manufacturing a display device according to an embodiment of the present disclosure. In particular, fig. 20 and 21 show schematic cross-sectional views of the first pattern 70 on which the light emitting element 30 is not disposed.

Referring to fig. 20, the first insulating layer 51 may be formed by removing portions of the first insulating material layer 51' to expose top surfaces of the first and second electrode layers 21' and 22 '. The first insulating layer 51 may include an opening OP exposing portions of the electrode layers 21 'and 22'. The top surfaces of the electrode layers 21 'and 22' exposed by the opening OP may be in electrical contact with the contact electrodes 26 and 27.

Thereafter, the first electrode 21 and the second electrode 22 are formed by cutting the first electrode layer 21 'and the second electrode layer 22' in the cut region CBA of each subpixel PXn, and the second insulating layer 52, the third insulating layer 53, and the contact electrodes 26 and 27 are formed on the light emitting element 30. An electrical signal for aligning the light emitting element 30 may be applied to the electrode layers 21 'and 22' electrically connected to each subpixel PXn. However, in order to drive the display apparatus 10, the electrode layers 21 'and 22' may be cut and separated in the cut region CBA of each subpixel PXn, thereby forming the electrodes 21 and 22, and as a result, the electrodes 21 and 22 may be individually driven via the first transistor TR1 of each subpixel PXn.

Thereafter, although not particularly shown, a fourth insulating layer 54 covering the elements provided on the target substrate SUB may be formed, thereby manufacturing the display device 10.

Display devices according to other embodiments of the present disclosure will be described below.

The display apparatus 10 includes a first pattern 70 disposed between the first banks 40 in each subpixel PXn. Fig. 6 shows that the width W1 of the first pattern 70 is less than the distance W3 between the electrodes 21 and 22, but the present disclosure is not limited thereto. For example, the width W1 and the thickness DP of the first pattern 70 may vary as long as the light emitting element 30 can be appropriately guided to be aligned at a specific position.

Fig. 22 to 24 are schematic partial sectional views of display devices according to other embodiments of the present disclosure. In particular, fig. 22 and 23 show schematic cross-sectional views of the first pattern 70_1 or 70_2 on which the light emitting element 30 is not disposed, and fig. 24 shows a schematic cross-sectional view of the first pattern 70_3 on which the second light emitting element 30B is disposed.

Referring to fig. 22, the width W1 of the first pattern 70_1 may be the same as the distance W3 between the electrodes 21_1 and 22_1, and the first pattern 70_1 may be in electrical contact with the electrodes 21_1 and 22_ 1. The first pattern 70_1 may be formed to have a relatively large width W1 and to be in electrical contact with the electrodes 21_1 and 22_1, and the first insulating layer 51 disposed on the first pattern 70_1 may provide a space in which the second light emitting elements 30B may be horizontally arranged.

Referring to fig. 23, the width W1 of the first pattern 70_2 may be greater than the distance W3 between the electrodes 21_2 and 22_2, and the first sides of the electrodes 21_2 and 22_2, which are not overlapped by the first bank 40, may be disposed on the first pattern 70_ 2. The embodiment of fig. 23 differs from the other embodiments at least in that: due to the first pattern 70_2 having the relatively large width W1, the first sides of the electrodes 21_2 and 22_2 are disposed on the first pattern 70_ 2. Although not particularly shown, the second light emitting elements 30B disposed on the first patterns 70_2 may be arranged such that both ends of the second light emitting elements 30B may be placed on the electrodes 21_2 and 22_2, and as a result, the second light emitting elements 30B may be appropriately electrically contacted with the contact electrodes 26 and 27. In the embodiment of fig. 23, unlike in the embodiment of fig. 5, the number of light emitting elements 30 electrically connected to the electrodes 21_2 and 22_2 between the first banks 40 may be further increased.

If the first pattern 70 has a relatively small width, the second light emitting element 30B may not be properly electrically contacted with the contact electrodes 26 and 27. According to the width of the first pattern 70, the light emitting elements 30 may be arranged obliquely rather than horizontally, and the electrical signal may not be properly transmitted to the light emitting elements 30 due to a contact defect. If the light emitting elements 30 are aligned by the electric field, the light emitting elements 30 may be guided to be placed between the first patterns 70, instead of on the first patterns 70, by controlling the thickness of the first patterns 70.

Referring to fig. 24, the thickness DP _3 of the first pattern 70_3 may be greater than the thickness DE of the electrodes 21 and 22, but less than the diameter DN of the light emitting element 30. If the thickness DP _3 of the first pattern 70_3 is smaller than the diameter DN of the light emitting element 30, the light emitting element 30 may be easily moved away from above the first pattern 70_3 by an electric field during the manufacturing of the display device 10. If an electric field for aligning the light emitting elements 30 is generated and the electric field lasts more than a predetermined amount of time, the light emitting elements 30 disposed on the first patterns 70_3 may move to positions where the first patterns 70_3 are not disposed. Even the light emitting elements 30 disposed in the regions other than the regions between the first banks 40 may move over the first pattern 70_ 3. The second light emitting elements 30B are shown to be disposed on the first patterns 70_3, but in the embodiment, a considerable number of light emitting elements 30 may be disposed not to overlap the first patterns 70_3, similar to the first light emitting elements 30A. Since the first pattern 70_3 has a thickness DP _3 smaller than the diameter DN of the light emitting element 30, most of the light emitting elements 30 may be arranged similarly to the first light emitting element 30A. For example, the thickness DP _3 of the first pattern 70_3 may be less than half the diameter DN of the light emitting element 30.

The shape of the first pattern 70 may vary as long as the first pattern 70 can generate a height difference between the first banks 40 and can appropriately guide the light emitting elements 30 to be placed at specific positions. For example, the shape of the first pattern 70 may vary as long as at least some of the light emitting elements 30 electrically connected to the first and second electrodes 21 and 22 may be located higher or lower than the other light emitting elements 30.

Fig. 25 and 26 are schematic partial cross-sectional views of display devices according to other embodiments of the present disclosure.

In particular, fig. 25 shows a schematic cross-sectional view of the first pattern 70_4 on which the light emitting element 30 is not disposed. Referring to fig. 25, the first pattern 70_4 may be integrally formed with the first planarization layer 19 disposed under the first pattern 70_ 4. During the formation of the first planarization layer 19, portions of the top surface of the first planarization layer 19 may be formed to protrude, and thus the first pattern 70_4 is formed. The first pattern 70_4 may be formed in various processes during the manufacture of the display device 10. As already mentioned above, the first pattern 70_4 may be formed during or after the formation of the first bank 40, and the first pattern 70_4 may be formed by protruding a portion of the top surface of the first planarization layer 19. The embodiment of fig. 25 differs from the embodiment of fig. 5 at least in that: the first pattern 70_4 is integrally formed with the first planarization layer 19. The first planarization layer 19 may include the first pattern 70_4 and a portion where the first pattern 70_4 is not formed, and the first pattern 70_4 is formed as a protrusion from the top surface of the first planarization layer 19. Among the light emitting elements 30, the first light emitting element 30A may be disposed on a portion of the first planarization layer 19 where the first pattern 70_4 is not formed, and the second light emitting element 30B may be disposed on the first pattern 70_ 4. During the manufacture of the display device 10, most of the light emitting elements 30 may be directed to be placed between the first patterns 70_4, rather than on the first patterns 70_ 4.

Referring to fig. 26, the first planarization layer 19_5 may include a recess where a portion of the top surface of the first planarization layer 19_5 is lowered between the first dikes 40, and at least some of the light emitting elements 30 may be disposed in the recess. During the formation of the first planarization layer 19_5, a recess may be formed between the first dikes 40. During the manufacturing of the display device 10, a process of generating a height difference may be performed to allow the light emitting elements 30 to be placed at different positions. For example, after the first planarization layer 19_5 is formed, a recess may be formed between the first banks 40 during the formation of the first and second contact holes CT1 and CT 2. When the recess is formed between the first dikes 40, a height difference is generated in the second direction DR2, and the light emitting elements 30 disposed between the first dikes 40 may be arranged to have a height different from that of the top surface of the first substrate 11. The embodiment of fig. 26 differs from the other embodiments at least in that: a portion of the top surface of the first planarization layer 19_5 is lowered.

For example, the width W4 of the recess may be greater than the distance W3 between the electrodes 21_5 and 22_5, and at least a portion of the electrodes 21_5 and 22_5 may be disposed in the recess. The light emitting elements 30 may be guided by the electric field to move into the recesses, and some or most of the light emitting elements 30 may be disposed in the recesses. The first light emitting element 30A is shown as being disposed in the recess, but the present disclosure is not limited thereto. The light emitting element 30 may further include a second light emitting element 30B, and the second light emitting element 30B is disposed on a portion of the first planarizing layer 19_5 where the recess is not formed, and is located at a higher position than the first light emitting element 30A.

The shapes of the first patterns 70, 70_1, 70_2, 70_3, and 70_4 are not particularly limited. The first patterns 70, 70_1, 70_2, 70_3, and 70_4 are illustrated in a plan view or a sectional view to have a rectangular shape, but the present disclosure is not limited thereto.

Fig. 27 is a schematic partial cross-sectional view of a display device according to another embodiment of the present disclosure. Fig. 28 is a schematic plan view of a sub-pixel of the display device of fig. 27.

Referring to fig. 27 and 28, the top surface of the first pattern 70_6 may be curved. In some embodiments, the first pattern 70_6 may have a hemispherical shape and/or may be circular in a plan view and may be semicircular in a sectional view. A portion of the first insulating layer 51_6 on the first pattern 70_6 may not have a flat top surface, and a position of the light emitting element 30 disposed on the portion of the first insulating layer 51_6 may be changed by an electric field, so that the light emitting element 30 may not overlap the first pattern 70_ 6. As a result, the light emitting element 30 may not be disposed on the first pattern 70_6, and a portion of the second insulating layer 52_6 overlapping the first pattern 70_6 may be in direct contact with the first insulating layer 51_ 6. The embodiment of fig. 27 and 28 differs from the other embodiments at least in that: the first pattern 70_6 may have a curved top surface, and only the first light emitting element 30A is disposed (and the second light emitting element 30B is not disposed).

Fig. 29 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure. Fig. 30 is a schematic sectional view taken along line QB-QB' of fig. 29. Fig. 31 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure. FIG. 32 is a schematic cross-sectional view taken along line QC-QC ', line QD-QD ', and line QE-QE ' of FIG. 31. Fig. 30 and 32 show schematic cross-sectional views of the first pattern 70_7 or 70_8 and the light emitting element 30 taken in the second direction DR 2.

Referring to fig. 29 to 32, the first pattern 70_7 or 70_8 may be disposed to overlap the first electrode 21 or the second electrode 22. The first pattern 70_7 or 70_8 may be directly disposed on the first planarization layer 19 provided with the first electrode 21 and the second electrode 22, and may generate a height difference in the first electrode 21 and the second electrode 22. The first pattern 70_7 or 70_8 may have such a small width that the light emitting elements 30 can be easily moved away from the first pattern 70_7 or 70_8 even if they are disposed on the first pattern 70_7 or 70_8 and can be disposed to overlap the electrodes 21 and 22. In the embodiment of fig. 29 to 32, unlike in the embodiment in which the first pattern 70_7 or 70_8 is disposed between the electrodes 21 and 22, because a height difference is generated in portions of the electrodes 21 and 22 at which the ends of the light emitting elements 30 are disposed, some or most of the light emitting elements 30 (e.g., the first light emitting elements 30A of fig. 30 and 32) may be disposed not to overlap the first pattern 70_7 or 70_ 8.

In some embodiments, the first pattern 70_7 or 70_8 overlapping the first electrode 21 and the first pattern 70_7 or 70_8 overlapping the second electrode 22 may be arranged in parallel with each other or in a staggered manner between the first banks 40. For example, as shown in fig. 29 and 30, the first pattern 70_7 overlapping the first electrode 21 and the first pattern 70_7 overlapping the second electrode 22 may be arranged in parallel to each other between the first banks 40. In another example, as shown in fig. 31 and 32, the first patterns 70_8 overlapping the first electrodes 21 and the first patterns 70_8 overlapping the second electrodes 22 may be arranged between the first banks 40 in a staggered manner.

During the manufacture of the display device 10, even if the first ends of the light emitting elements 30 are disposed on the first patterns 70_7 or 70_8, the second ends of the light emitting elements 30 may not be disposed on the first patterns 70_7 or 70_8, or vice versa. In this case, the light emitting element 30 may move to a region where the first pattern 70_7 or 70_8 is not formed in the presence of an electric field. Since the first pattern 70_7 or 70_8 has a relatively small width and is disposed to overlap the electrodes 21 and 22, even if the end of the light emitting element 30 is disposed on the first pattern 70_7 or 70_8, the light emitting element 30 can be appropriately directed toward a position where the first pattern 70_7 or 70_8 is not disposed.

The first electrode 21 and the second electrode 22 may not necessarily extend in one direction. In some embodiments, the electrodes 21 and 22 may include a portion extending in one direction to have a different width and a portion extending in the other direction.

Fig. 33 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure.

Referring to fig. 33, each of the electrodes 21_9 and 22_9 may include an extension portion RE-E extending substantially in the second direction DR2 and having a width greater than that of the remaining portion of the corresponding electrode, bent portions RE-B1 and RE-B2 extending in a diagonal direction with respect to the first direction DR1 or the second direction DR2, and connection portions RE-C1 and RE-C2 connecting the bent portions RE-B1 and RE-B2 and the extension portion RE-E, bent portions RE-B1 and RE-B2, and connection portions RE-C1 and RE-C2. The electrodes 21_9 and 22_9 may generally extend in the second direction DR2, but portions of the electrodes 21_9 and 22_9 may have a relatively large width or may be bent in a diagonal direction with respect to the second direction DR 2. The first electrode 21_9 and the second electrode 22_9 may be symmetrically arranged with respect to the first pattern 70_9 disposed therebetween. The shape of the first electrode 21_9 will be described below.

The first electrode 21_9 may include an extension portion RE-E having a width greater than that of the remaining portion of the first electrode 21_ 9. The extension portion RE-E of the first electrode 21_9 and the extension portion RE-E of the second electrode 22_9 may be disposed on the first bank 40 in the emission area EMA of the first sub-pixel PX1 to extend in the second direction DR 2. The first pattern 70_9 may be disposed between the extension portions RE-E, and the light emitting element 30 may be disposed on the extension portions RE-E. The first and second contact electrodes 26_9 and 27_9 may be disposed on the extension portion RE-E, but may have a width smaller than that of the extension portion RE-E.

The connecting portions RE-C1 and RE-C2 may extend in the second direction DR2 or be connected to both sides of each of the extending portions RE-E. The first connection portion RE-C1 may be disposed on a first side of the extension portion RE-E in the second direction DR2, and the second connection portion RE-C2 may be disposed on a second side of the extension portion RE-E in the second direction DR 2. The connection portions RE-C1 and RE-C2 may extend or be connected to the extension portions RE-E of the corresponding electrodes, and may be disposed in and across the emission area EMA and the second bank 45.

The first and second connecting portions RE-C1 and RE-C2 may have a width smaller than that of the extension RE-E. The first sides of the connecting portions RE-C1 and RE-C2 extending in the second direction DR2 may extend or be connected to the first sides of the respective extending portions RE-E extending in the second direction DR2 and fall on the same line as the first sides of the respective extending portions RE-E extending in the second direction DR 2. For example, the outer side of the extension portion RE-E of each of the electrodes 21_9 and 22_9 may extend to be electrically connected to the outer sides of the connection portions RE-C1 and RE-C2 of the corresponding electrodes. Accordingly, the distance DE1 between the extension RE-E of the first electrode 21_9 and the extension RE-E of the second electrode 22_9 may be smaller than the distance DE2 between the connection RE-C1 of the first electrode 21_9 and the connection RE-C2 of the second electrode 22_ 9.

The curved portions RE-B1 and RE-B2 extend or are connected to the linking portions RE-C1 and RE-C2. The curved portions RE-B1 and RE-B2 may include a first curved portion RE-B1 and a second curved portion RE-B2, the first curved portion RE-B1 extending or being connected to the first connecting portion RE-C1 and being disposed on the second bank 45 and in the cut region CBA, the second curved portion RE-B2 extending or being connected to the second connecting portion RE-C2 and being disposed on the second bank 45 and in the cut region CBA of the other sub-pixel PXn. The bending portions RE-B1 and RE-B2 may be electrically connected to the connection portions RE-C1 and RE-C2, and may be bent in a diagonal direction with respect to the second direction DR2 (e.g., in a direction toward the center of the first subpixel PX 1). The minimum distance DE3 between the curved portion RE-B1 and RE-B2 may be less than the distance DE2 between the connecting portion RE-C1 and RE-C2, but may be greater than the distance DE1 between the extending portions RE-E.

The contact portion RE-P may be formed in a region where the first connection portion RE-C1 and the first bent portion RE-B1 are electrically connected. The contact portion RE-P may overlap the second bank 45 such that the first contact hole CT1 of the first electrode 21_9 and the second contact hole CT2 of the second electrode 22_9 may be formed.

The segment portion RE-D obtained when the first and second electrodes 21_9 and 22_9 are separated into the pieces in the cutting area CBA may be formed at the first end of the first bent portion RE-B1. The segment portion RE-D may be the portions of the first electrode 21_9 and the second electrode 22_9 of the adjacent sub-pixel PXn in the second direction DR2 remaining in the cutting area CBA.

The embodiment of fig. 33 differs from the embodiment of fig. 4 at least in that: each of the first and second electrodes 21_9 and 22_9 includes an extension portion RE-E, connection portions RE-C1 and RE-C2, and bending portions RE-B1 and RE-B2, and is symmetrically arranged with respect to the center of the first sub-pixel PX 1. However, the present disclosure is not limited thereto. As another example, the first electrode 21_9 and the second electrode 22_9 may have different shapes.

Fig. 34 is a schematic plan view of a sub-pixel of a display device according to another embodiment of the present disclosure. Fig. 35 is a schematic sectional view taken along the line QX-QX' of fig. 34.

Referring to fig. 34 and 35, the display device 10 may include a first electrode 21_10, a second electrode 22_10, and a first pattern 70_10 in each subpixel PXn thereof (e.g., in the first subpixel PX 1). The first electrodes 21_10 may have the same shape as that of their corresponding first electrodes 21_9 of fig. 33, and the first electrodes 21_10 (e.g., two first electrodes 21_10) may be symmetrically arranged with respect to the center of the first subpixel PX 1. The second electrodes 22_10 may have the same shape as their corresponding second electrodes 22 of fig. 2, and the second electrodes 22_10 (e.g., two second electrodes 22_10) may be disposed between the first electrodes 21_ 10. The distance between the first electrode 21_10 and the second electrode 22_10 may be different from one position to another position on the first electrode 21_ 10. For example, the distance DE1 between the extension portion RE-E of the first electrode 21_10 and the second electrode 22_10 may be smaller than the distance DE2 between the connection portions RE-C1 and RE-C2 of the first electrode 21_10 and the second electrode 22_10 and the distance DE3 between the bent portions RE-B1 and RE-B2 of the first electrode 21_10 and the second electrode 22_ 10. The distance DE2 between the connection portions RE-C1 and RE-C2 of the first electrode 21_10 and the second electrode 22_10 may be greater than the distance DE3 between the bent portions RE-B1 and RE-B2 of the first electrode 21_10 and the second electrode 22_ 10. However, the present disclosure is not limited thereto. The shape of the electrodes 21_10 and 22_10 is the same as that of their respective corresponding electrodes of any one of fig. 2 to 33, and thus detailed description thereof will be omitted.

The arrangement and shape of the first sub bank 41_10, the first insulating layer 51_10, and the contact electrodes 26_10, 27_10, and 28_10 may vary according to the arrangement of the first electrode 21_10 and the second electrode 22_ 10.

The first insulating layer 51_10 may be disposed between the extended portion RE-E of the first electrode 21_10 and the second electrode 22_10 and in contact with the extended portion RE-E of the first electrode 21_10 and the second electrode 22_ 10. A first end of the light emitting element 30 may be disposed on the extension portion RE-E of the first electrode 21_10, and a second end of the light emitting element 30 may be disposed on the second electrode 22_ 10.

The first bank 40 may include a first sub-bank 41_10 and a second sub-bank 42_ 10. The first and second sub-banks 41_10 and 42_10 may extend in the second direction DR2, and the first sub-bank 41_10 may have a width different from that of the second sub-bank 42_10 in the first direction DR 1. Since the first sub bank 41_10 has a width greater than that of the second sub bank 42_10 in the first direction DR1, the first sub bank 41_10 may be disposed to cross a boundary between the first sub pixel PX1 and an adjacent sub pixel PXn of the first sub pixel PX1 in the first direction DR 1. For example, the first sub-bank 41_10 may be disposed not only in the emission area EMA of the first sub-pixel PX1 but also between the emission area EMA of the first sub-pixel PX1 and the emission area EMA of the adjacent sub-pixel PXn. Accordingly, a portion of the second bank 45_10 extending in the second direction DR2 may be disposed on the first sub-bank 41_ 10. Two first sub-banks 41_10 may be partially disposed in each sub-pixel PXn, and one second sub-bank 42_10 may be disposed between the two first sub-banks 41_ 10.

The second sub-bank 42_10 may extend in the second direction DR2 in the middle of the emission area EMA of the first sub-pixel PX 1. The second sub bank 42_10 may have a width smaller than that of the first sub bank 41_10 and may be spaced apart from the first sub bank 41_ 10.

The extended portion RE-E of the first electrode 21_10 and the second bank 45_10 may be disposed on the first sub-bank 41_ 10. The extension portion RE-E of the first electrode 21_10 of the adjacent subpixel PXn may be disposed on the first sub bank 41_ 10. For example, the extension portions RE-E of the two first electrodes 21_10 may be disposed on one first sub-bank 41_10, and the two second electrodes 22_10 may be disposed on one second sub-bank 42_ 10. The second electrodes 22_10 may be disposed along both sides of the second sub-bank 42_10 extending in the second direction DR2, and may be spaced apart from each other with the second sub-bank 42_10 between the second electrodes 22_ 10.

One of the first electrodes 21_10 may include a contact portion RE-P in which the first contact hole CT1 is formed, and the other first electrode 21_10 may not include the contact portion RE-P. Similarly, one of the second electrodes 22_10 may include the contact portion RE-P in which the second contact hole CT2 is formed, and the other second electrode 22_10 may not include the contact portion RE-P. Some of the electrodes 21_10 and 22_10 electrically connected to the first transistor TR1 or the second voltage line VL2 may receive an electrical signal via the contact holes CT1 and CT2, and the other electrodes 21_10 and 22_10 may receive an electrical signal via the contact electrodes 26_10, 27_10, and 28_ 10.

Both ends of each of the light emitting elements 30 are disposed on the extension portion RE-E of the first electrode 21_10 and the second electrode 22_10 on the first insulating layer 51_ 10. A first end of the light emitting element 30 where the second semiconductor layer 32 is disposed may be disposed on the first electrode 21_ 10. Accordingly, the first end of the first type light emitting element 30-1 disposed between the left electrodes 21_10 and 22_10 disposed on the left side of the center of the first sub-pixel PX1 and the first end of the second type light emitting element 30-2 disposed between the right electrodes 21_10 and 22_10 disposed on the right side of the center of the first sub-pixel PX1 may face opposite directions.

The display device 10 may include a relatively large number of electrodes 21_10 and 22_10, and thus may include a relatively large number of contact electrodes 26_10, 27_10, and 28_ 10.

The contact electrodes 26_10, 27_10, and 28_10 may include a first contact electrode 26_10 disposed on one of the first electrodes 21_10, a second contact electrode 27_10 disposed on one of the second electrodes 22_10, and a third contact electrode 28_10 disposed on the other first electrode 21_10 and the other second electrode 22_10 and surrounding the second contact electrode 27_ 10.

The first contact electrode 26_10 may be disposed on one of the first electrodes 21_ 10. For example, the first contact electrode 26_10 may be disposed on the extension portion RE-E of the first electrode 21_10 at which the first end of the first type light emitting element 30-1 is disposed. The first contact electrode 26_10 may be in electrical contact with the first end of the first type light emitting element 30-1 and in electrical contact with the extended portion RE-E of the first electrode 21_10 where the first end of the first type light emitting element 30-1 is disposed. The second contact electrode 27_10 may be disposed on one of the second electrodes 22_ 10. For example, the second contact electrode 27_10 may be disposed on the second electrode 22_10 provided with the first end of the second type light emitting element 30-2. The second contact electrode 27_10 may be in electrical contact with the first end of the second type light emitting element 30-2 and in electrical contact with the second electrode 22_10 provided with the first end of the second type light emitting element 30-2. The first and second contact electrodes 26_10 and 27_10 may be in electrical contact with the electrodes 21_10 and 22_10 formed with the first and second contact holes CT1 and CT 2. The first contact electrode 26_10 may be in electrical contact with the first electrode 21_10 electrically connected to the first transistor TR1 via the first contact hole CT1, and the second contact electrode 27_10 may be in electrical contact with the second electrode 22_10 electrically connected to the second voltage line VL2 via the second contact hole CT 2. The first and second contact electrodes 26_10 and 27_10 may transfer an electric signal applied thereto from the first transistor TR1 or the second voltage line VL2 to the light emitting element 30. The first contact electrode 26_10 and the second contact electrode 27_10 may be substantially the same as their respective corresponding contact electrodes of any one of fig. 2 to 33.

The electrodes 21_10 and 22_10 where the contact holes CT1 and CT2 are not formed may be further disposed in the first sub-pixel PX 1. The electrodes 21_10 and 22_10 where the contact holes CT1 and CT2 are not formed may be in a floating state and substantially no electric signal is directly applied to the electrodes 21_10 and 22_10 from the first transistor TR1 or the second voltage line VL 2. The third contact electrode 28_10 may be disposed on the electrodes 21_10 and 22_10 where the contact holes CT1 and CT2 are not formed, and the electric signal transmitted to the light emitting element 30 may flow via the third contact electrode 28_ 10.

The third contact electrode 28_10 may be disposed on the electrodes 21_10 and 22_10 where the contact holes CT1 and CT2 are not formed, and may be disposed to surround the second contact electrode 27_ 10. The third contact electrode 28_10 may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1 to connect portions extending in the second direction DR2, and thus may surround the second contact electrode 27_ 10. A portion of the third contact electrode 28_10 extending in the second direction DR2 may be disposed on the electrodes 21_10 and 22_10 where the contact holes CT1 and CT2 are not formed, to electrically contact the light emitting element 30. For example, a portion of the third contact electrode 28_10 disposed on the second electrode 22_10 where the second contact hole CT2 is not formed may be in electrical contact with the second end of the first type light emitting element 30-1, and a portion of the third contact electrode 28_10 disposed on the first electrode 21_10 where the first contact hole CT1 is not formed may be in electrical contact with the first end of the second type light emitting element 30-2. Since there is an insulating layer (not shown) between the third contact electrode 28_10 and the second electrode 22_10, a portion of the third contact electrode 28_10 extending in the first direction DR1 may overlap the second electrode 22_10 formed with the second contact hole CT2, but may not be directly connected to the second electrode 22_10 formed with the second contact hole CT 2.

An electrical signal transmitted from the first contact electrode 26_10 to the first end of the first type light emitting element 30-1 may be transferred to the third contact electrode 28_10, and the third contact electrode 28_10 is in electrical contact with the second end of the first type light emitting element 30-1. The third contact electrode 28_10 may transmit the electrical signals to the first end of the second light emitting element 30B, so that the signals may be transmitted to the second electrode 22_10 via the second contact electrode 27_ 10. Accordingly, an electrical signal for light emission of the light emitting element 30 may be transmitted to only one of the first electrode 21_10 and the second electrode 22_10, and the first type light emitting element 30-1 and the second type light emitting element 30-2 may be electrically connected in series via the third contact electrode 28_ 10.

At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.