阅读说明：本技术 显示装置和电子装置 (Display device and electronic device ) 是由 严努力 郭源奎 金京勋 金美海 金才源 朴亨埈 卞昌洙 吴暻焕 崔埈源 于 2021-04-13 设计创作，主要内容包括：本公开涉及一种显示装置和一种电子装置,所述显示装置包括：基底,基底包括显示区域、孔和围绕孔的孔边缘区域；多条第一数据线,多条第一数据线设置在基底上,在显示区域中在第一方向上延伸并且在与第一方向交叉的第二方向上布置,并且沿着孔边缘区域绕过孔；以及多条第二数据线,多条第二数据线设置在基底上,在显示区域中在第一方向上延伸并且在第二方向上与多条第一数据线交替地布置,并且沿着孔边缘区域绕过孔。在孔边缘区域中,多条第一数据线中的至少一条与多条第二数据线中的至少一条交叉,使得多条第一数据线设置为彼此相邻并且多条第二数据线设置为彼此相邻。(The present disclosure relates to a display device and an electronic device, the display device including: a substrate including a display area, a hole, and a hole edge area surrounding the hole; a plurality of first data lines disposed on the substrate, extending in a first direction in the display area and arranged in a second direction crossing the first direction, and bypassing the holes along the hole edge area; and a plurality of second data lines disposed on the substrate, extending in the first direction in the display area and alternately arranged with the plurality of first data lines in the second direction, and bypassing the holes along the hole edge area. In the hole edge region, at least one of the plurality of first data lines crosses at least one of the plurality of second data lines such that the plurality of first data lines are disposed adjacent to each other and the plurality of second data lines are disposed adjacent to each other.)

1. A display device, wherein the display device comprises:

a substrate including a display area, a hole, and a hole edge area surrounding the hole;

a plurality of first data lines disposed on the substrate, extending in a first direction in the display area and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge area; and

a plurality of second data lines disposed on the substrate, extending in the first direction in the display area and alternately arranged with the plurality of first data lines in the second direction, and bypassing the hole along the hole edge area,

wherein, in the hole edge region, at least one of the plurality of first data lines crosses at least one of the plurality of second data lines such that the plurality of first data lines are disposed adjacent to each other and the plurality of second data lines are disposed adjacent to each other.

2. The display device according to claim 1, wherein, in the hole edge region,

the plurality of first data lines overlap each other in a plan view, and

the plurality of second data lines overlap each other in a plan view.

3. The display device according to claim 1, wherein, in the hole edge region,

the plurality of first data lines are adjacent to each other in a plan view, and

the plurality of second data lines are adjacent to each other in a plan view.

4. The display device according to claim 1,

the plurality of first data lines includes two first data lines and the plurality of second data lines includes two second data lines, and

first data lines of the plurality of first data lines disposed between the plurality of second data lines cross second data lines of the plurality of second data lines disposed between the plurality of first data lines.

5. The display device according to claim 4, wherein, in a region where the first data line crosses the second data line,

the second data line extends in a third direction different from the first direction and the second direction, and

the first data line extends in a fourth direction crossing the third direction.

6. The display device according to claim 4, wherein, in a region where the first data line crosses the second data line,

the second data line extends in a third direction different from the first direction and the second direction, and

the first data line extends in the first direction.

7. The display device according to claim 1, wherein the display device further comprises:

a semiconductor layer disposed in the display region on the substrate;

a gate electrode disposed over the semiconductor layer;

a capacitor electrode disposed over the gate electrode;

a source electrode and a drain electrode disposed over the capacitor electrode and electrically connected to the semiconductor layer;

a connection electrode disposed over and electrically connected to the source electrode and the drain electrode; and

a light emitting element disposed over the connection electrode and electrically connected to the connection electrode.

8. The display device according to claim 7,

at least one wiring of the plurality of first data lines and at least one wiring of the plurality of second data lines in the hole edge region are disposed on the same layer as at least one of the gate electrode, the capacitor electrode, the source electrode, the drain electrode, and the connection electrode in the display region.

9. The display device according to claim 7, wherein the display device further comprises: an emission control line disposed on the substrate, extending in the second direction in the display area, and bypassing the hole along the hole edge area.

10. The display device according to claim 9,

at least one wiring of the plurality of first data lines and at least one wiring of the plurality of second data lines in the hole edge region are disposed on the same layer as at least one of the gate electrode and the capacitor electrode in the display region, and

the emission control line in the hole edge region is disposed on the same layer as the connection electrode in the display region.

11. The display device according to claim 1,

the hole has a circular shape, and

the hole edge region has a circular ring shape.

12. A display device, wherein the display device comprises:

a substrate including a display area, a hole, and a hole edge area surrounding the hole; and

first, second, third, and fourth wirings each provided on the substrate, extending in a first direction in the display region and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge region,

wherein, in the hole edge region, the second wiring crosses the third wiring such that the first wiring and the third wiring are disposed adjacent to each other and the second wiring and the fourth wiring are disposed adjacent to each other.

13. The display device according to claim 12, wherein, in the hole edge region,

the first wiring and the third wiring overlap with each other in a plan view, and

the second wiring and the fourth wiring overlap with each other in a plan view.

14. The display device according to claim 12, wherein, in the hole edge region,

the first wiring and the third wiring are adjacent to each other in a plan view, and

the second wiring and the fourth wiring are adjacent to each other in a plan view.

15. The display device according to claim 12, wherein in a region where the second wiring and the third wiring intersect,

the second wiring extends in a third direction different from the first direction and the second direction, and

the third wiring extends in a fourth direction that intersects the third direction.

16. The display device according to claim 15,

the first direction is orthogonal to the second direction, and

the fourth direction is orthogonal to the third direction.

17. The display device according to claim 12, wherein in a region where the second wiring and the third wiring intersect,

the second wiring extends in a third direction different from the first direction and the second direction, and

the third wiring extends in the first direction.

18. The display device according to claim 12,

the first wiring and the third wiring are electrically connected to a first pixel provided in the display region over the substrate, and

the second wiring and the fourth wiring are electrically connected to a second pixel provided in the display region on the substrate, the second pixel displaying a color different from a color of the first pixel.

19. An electronic device, wherein the electronic device comprises:

a display device including a display area, an aperture, and an aperture edge area surrounding the aperture; and

a functional module disposed below the display device and overlapping the hole, wherein,

the display device includes:

a plurality of first data lines extending in a first direction in the display area and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge area; and

a plurality of second data lines extending in the first direction in the display area and alternately arranged with the plurality of first data lines in the second direction, and bypassing the hole along the hole edge area, and

in the hole edge region, at least one of the plurality of first data lines crosses at least one of the plurality of second data lines such that the plurality of first data lines are disposed adjacent to each other and the plurality of second data lines are disposed adjacent to each other.

20. The electronic device of claim 19, wherein the functional module comprises: at least one of a camera module, a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

Technical Field

The present disclosure relates to a display device and an electronic device. More particularly, the present disclosure relates to a display device in which a hole is formed in a display region and an electronic device.

Background

A display device may include a display area for displaying an image and a non-display area positioned outside the display area. Pixels for displaying an image and wirings connected to the pixels may be provided in the display region. A driver for driving the pixels and functional modules such as a camera module and a sensor module may be disposed in the non-display region.

In order to reduce dead space (dead space) caused by the non-display area, a hole may be formed in the display area. The function module may be provided on the rear surface of the display device to correspond to the hole, and the function module may detect or recognize an object or a user, etc. positioned on the front surface of the display device through the hole. In the case where a hole is formed in the display region, a wiring provided in the display region may bypass the hole. Accordingly, a hole edge region surrounding the hole, in which the wirings are adjacent to each other so as not to display an image, may be formed at the edge of the hole.

Disclosure of Invention

The present disclosure provides a display device preventing coupling between wirings located in a hole edge region surrounding a hole.

A display device according to an embodiment may include: a substrate including a display area, a hole, and a hole edge area surrounding the hole; a plurality of first data lines disposed on the substrate, extending in a first direction in the display area and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge area; and a plurality of second data lines disposed on the substrate, extending in the first direction in the display area and alternately arranged with the plurality of first data lines in the second direction, and bypassing the hole along the hole edge area. In the hole edge region, at least one of the plurality of first data lines crosses at least one of the plurality of second data lines such that the plurality of first data lines are disposed adjacent to each other and the plurality of second data lines are disposed adjacent to each other.

In an embodiment, in the hole edge region, the plurality of first data lines may overlap each other in a plan view, and the plurality of second data lines may overlap each other in a plan view.

In an embodiment, in the hole edge region, the plurality of first data lines may be adjacent to each other in a plan view, and the plurality of second data lines may be adjacent to each other in a plan view.

In an embodiment, the plurality of first data lines may include two first data lines and the plurality of second data lines may include two second data lines, and first data lines of the plurality of first data lines disposed between the plurality of second data lines cross second data lines of the plurality of second data lines disposed between the plurality of first data lines.

In an embodiment, in a region where the first data line crosses the second data line, the second data line may extend in a third direction different from the first direction and the second direction, and the first data line may extend in a fourth direction crossing the third direction.

In an embodiment, in a region where the first data line crosses the second data line, the second data line may extend in a third direction different from the first direction and the second direction, and the first data line may extend in the first direction.

In an embodiment, the display device may further include: a semiconductor layer disposed in the display region on the substrate; a gate electrode disposed over the semiconductor layer; a capacitor electrode disposed over the gate electrode; a source electrode and a drain electrode disposed over the capacitor electrode and electrically connected to the semiconductor layer; a connection electrode disposed over and electrically connected to the source electrode and the drain electrode; and a light emitting element disposed over the connection electrode and electrically connected to the connection electrode.

In an embodiment, at least one wiring of the plurality of first data lines and at least one wiring of the plurality of second data lines in the hole edge region may be disposed on the same layer as at least one of the gate electrode, the capacitor electrode, the source electrode, the drain electrode, and the connection electrode in the display region.

In an embodiment, the display device may further include: an emission control line disposed on the substrate, extending in the second direction in the display area, and bypassing the hole along the hole edge area.

In an embodiment, at least one wiring of the plurality of first data lines and at least one wiring of the plurality of second data lines in the hole edge region and at least one of the gate electrode and the capacitor electrode in the display region may be disposed on the same layer, and the emission control line in the hole edge region and the connection electrode in the display region may be disposed on the same layer.

In an embodiment, the hole may have a circular shape, and the hole edge region may have a circular ring shape.

A display device according to an embodiment may include: a substrate including a display area, a hole, and a hole edge area surrounding the hole; and first, second, third, and fourth wirings each provided on the substrate, extending in a first direction in the display region and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge region. In the hole edge region, the second wiring may cross the third wiring such that the first wiring and the third wiring may be disposed adjacent to each other and the second wiring and the fourth wiring may be disposed adjacent to each other.

In an embodiment, in the hole edge region, the first wiring and the third wiring may overlap each other in a plan view, and the second wiring and the fourth wiring may overlap each other in a plan view.

In an embodiment, in the hole edge region, the first wiring and the third wiring may be adjacent to each other in a plan view, and the second wiring and the fourth wiring may be adjacent to each other in a plan view.

In an embodiment, in a region where the second wiring crosses the third wiring, the second wiring may extend in a third direction different from the first direction and the second direction, and the third wiring may extend in a fourth direction crossing the third direction.

In an embodiment, the first direction may be orthogonal to the second direction, and the fourth direction may be orthogonal to the third direction.

In an embodiment, in a region where the second wiring crosses the third wiring, the second wiring may extend in a third direction different from the first direction and the second direction, and the third wiring may extend in the first direction.

In an embodiment, the first wiring and the third wiring may be electrically connected to a first pixel provided in the display region on the substrate, and the second wiring and the fourth wiring may be electrically connected to a second pixel provided in the display region on the substrate, the second pixel displaying a color different from a color of the first pixel.

An electronic device according to an embodiment may include: a display device including a display area, an aperture, and an aperture edge area surrounding the aperture; and a functional module disposed under the display device and overlapping the hole. The display device may include: a plurality of first data lines extending in a first direction in the display area and arranged in a second direction crossing the first direction, and bypassing the hole along the hole edge area; and a plurality of second data lines extending in the first direction in the display area and alternately arranged with the plurality of first data lines in the second direction, and bypassing the hole along the hole edge area. In the hole edge region, at least one of the plurality of first data lines may cross at least one of the plurality of second data lines, such that the plurality of first data lines may be disposed adjacent to each other and the plurality of second data lines may be disposed adjacent to each other.

In an embodiment, the functional module may include: at least one of a camera module, a face recognition sensor module, a pupil recognition sensor module, an acceleration sensor module, a proximity sensor module, an infrared sensor module, and an illuminance sensor module.

In the display device according to the embodiment, at least one of the plurality of first data lines may cross at least one of the plurality of second data lines such that the plurality of first data lines may be disposed adjacent to each other and the plurality of second data lines may be disposed adjacent to each other in the hole edge region such that a distance between the plurality of first data lines and the plurality of second data lines may increase. Accordingly, coupling between the plurality of first data lines and the plurality of second data lines may be reduced or substantially prevented.

Drawings

Additional understanding of embodiments in accordance with the present invention will become apparent by describing in detail embodiments thereof with reference to the attached drawings, wherein:

fig. 1 is a schematic block diagram showing a display apparatus according to an embodiment;

fig. 2 is a schematic plan view showing a part of a display device according to an embodiment;

fig. 3 is a schematic cross-sectional view illustrating a display area of the display device of fig. 2;

fig. 4 is a schematic plan view showing an example of the periphery of the hole of the display device of fig. 2;

FIG. 5 is a schematic cross-sectional view taken along line I-I' of FIG. 4;

fig. 6 is a schematic plan view showing an example of the periphery of the hole of the display device of fig. 2;

FIG. 7 is a schematic cross-sectional view taken along line II-II' of FIG. 6;

fig. 8 is a schematic plan view showing an example of the periphery of the hole of the display device of fig. 2;

FIG. 9 is a schematic cross-sectional view taken along line III-III' of FIG. 8;

fig. 10 is a schematic plan view showing an example of the periphery of the hole of the display device of fig. 2;

FIG. 11 is a schematic cross-sectional view taken along line IV-IV' of FIG. 10;

fig. 12 is a schematic plan view showing an example of the periphery of the hole of the display device of fig. 2;

FIG. 13 is a schematic cross-sectional view taken along line V-V' of FIG. 12;

fig. 14 is a schematic plan view showing a part of a display device according to the embodiment; and is

Fig. 15 is a schematic sectional view illustrating an electronic device according to an embodiment.

Detailed Description

Since the present disclosure is susceptible to various modifications and alternative embodiments, there is shown in the drawings and will be described in detail herein preferred embodiments. However, this disclosure is not limited to the specific embodiments, and it should be understood that the disclosure covers all modifications, equivalents, and alternatives falling within the spirit and technical scope of the present invention.

In this specification, it will also be understood that when an element (or region, layer, or portion) is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on or connected or coupled to the element or intervening third elements may also be present.

In the present application, it will be understood that when a layer, film, region or panel is "in direct contact" with another layer, film, region or panel, there are no intervening layers, films, regions or panels between them. For example, if one layer is "directly disposed" on another layer, the layer may be disposed on the other layer without using an additional member such as an adhesive member.

Like reference numerals refer to like elements throughout. In addition, in the drawings, the thickness, ratio, and size of components may be exaggerated for clarity of illustration.

The term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that, although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first element could be termed a second element in one embodiment, and a second element could be termed a first element in another embodiment, without departing from the scope of the appended claims. Unless indicated to the contrary, singular terms may include the plural.

The terms "below … …," "below … …," "above … …," "above," "around," and "adjacent," etc. are used to explain the relative association of components shown in the figures. These terms may be relative concepts and may be described based on the orientations shown in the drawings. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be disposed on the other element or layer.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be further understood that the terms "comprises," "comprising," "includes" and "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In the specification and claims, for the purposes of meaning and explanation of the phrase "at least one (species) of … …, the phrase" at least one (species) of … … "is intended to include the meaning of" at least one (species) selected from the group of … … ". For example, "at least one of a and B" may be understood to mean "A, B or a and B".

Hereinafter, a display device and an electronic device according to an embodiment will be explained in detail with reference to the drawings.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 1 to 5.

Fig. 1 is a schematic block diagram illustrating a display apparatus 100 according to an embodiment.

Referring to fig. 1, according to an embodiment, a display device 100 may include a display unit 110, a scan driver 120, a data driver 130, an emission control driver 140, a power supply 150, and a timing controller 160.

The display unit 110 may be positioned at an intersection of the scan line SL, the data lines DL1 and DL2, the emission control line EML, and the driving voltage line DVL, and may include pixels PX1 and PX2 arranged substantially in a matrix form. The scan lines SL and the emission control lines EML may generally extend in a row direction, and the data lines DL1 and DL2 and the driving voltage line DVL may generally extend in a column direction.

The pixels PX1 and PX2 may be electrically connected to the scan lines SL, the data lines DL1 and DL2, the emission control line EML, and the driving voltage line DVL. The pixels PX1 and PX2 may include a first pixel PX1 and a second pixel PX 2. The second pixel PX2 may display a color different from that of the first pixel PX 1. In an embodiment, the first pixel PX1 may display a red color or a blue color, and the second pixel PX2 may display a green color.

The scan driver 120 may be electrically connected to the scan lines SL. The scan driver 120 may transmit a scan signal to the pixels PX1 and PX2 through the scan lines SL.

The data driver 130 may be electrically connected to the data lines DL1 and DL 2. The data lines DL1 and DL2 may include a first data line DL1 and a second data line DL 2. The first data line DL1 may be electrically connected to the first pixel PX1, and the second data line DL2 may be electrically connected to the second pixel PX 2. The data driver 130 may transmit data signals to the pixels PX1 and PX2 through the data lines DL1 and DL 2. In the case where the scan signal is supplied through the scan line SL, the data signal may be supplied to the pixels PX1 and PX2 selected by the scan signal.

The emission control driver 140 may be electrically connected to the emission control line EML. The emission control driver 140 may transmit the emission control signal to the pixels PX1 and PX2 through the emission control line EML. The emission control signals may control the emission time of the pixels PX1 and PX 2.

The pixels PX1 and PX2 may receive a driving voltage and a common voltage from the power supply 150. The driving voltage may be a predetermined high-level voltage, and the common voltage may be a voltage lower than the driving voltage or a ground voltage. The power supply 150 may be electrically connected to the driving voltage line DVL. The power supply 150 may transmit the driving voltage to the pixels PX1 and PX2 through the driving voltage line DVL.

The timing controller 160 may convert an image signal transmitted from an external source into an image data signal, and may transmit the image data signal to the data driver 130. The timing controller 160 may receive a vertical synchronization signal, a horizontal synchronization signal, and a clock signal to generate control signals for controlling the driving of the scan driver 120, the data driver 130, and the emission control driver 140, and the timing controller 160 may transmit the generated control signals to the scan driver 120, the data driver 130, and the emission control driver 140.

The pixels PX1 and PX2 may emit light having a predetermined luminance in response to a driving current supplied to the light emitting elements according to data signals transmitted through the data lines DL1 and DL 2. For convenience, a display device including an Organic Light Emitting Diode (OLED) as a light emitting element will be described below, but the embodiment is not limited thereto. The present disclosure may be applied to various types of display devices such as a liquid crystal display device, an electrophoretic display device, a Light Emitting Diode (LED) display device, and the like.

Fig. 2 is a schematic plan view illustrating a portion of the display device 100 according to the embodiment.

Referring to fig. 1 and 2, according to an embodiment, the display device 100 may include a substrate 200 on which pixels PX1 and PX2, lines SL, DL1, DL2, EML and DVL, a scan driver 120, a data driver 130, an emission control driver 140, a power supply 150, and a timing controller 160 are disposed. The substrate 200 may include a display area DA, a peripheral area PA, and a hole edge area HEA.

The pixels PX1 and PX2 and the lines SL, DL1, DL2, EML, and DVL may be disposed in the display area DA on the substrate 200. The display area DA may display an image by light emitted from each of the pixels PX1 and PX 2.

The peripheral area PA may surround the display area DA. The peripheral area PA may form (or constitute) a bezel of the display apparatus 100. The scan driver 120 and the emission control driver 140 may be disposed in the peripheral area PA on the substrate 200. The data driver 130, the power supply 150, and the timing controller 160 may be disposed in the peripheral area PA on the substrate 200, or may be disposed on a printed circuit board or a flexible printed circuit, etc., which are electrically connected to the substrate 200. The peripheral area PA may be a non-display area.

A hole HL may be formed in the display area DA. The hole HL may be formed through the substrate 200. A functional module may be disposed under the substrate 200 to correspond to the hole HL. The function module may receive external light through the hole HL, or may transmit signals such as infrared rays and ultrasonic waves.

In an embodiment, the functional module may include: a camera module for photographing (or recognizing) an image of an object positioned above the front surface of the display device 100; a facial recognition sensor module for detecting a user's face; the pupil identification sensor module is used for detecting the pupil of the user; an acceleration sensor module and a geomagnetic sensor module for determining a motion of the display apparatus 100; a proximity sensor module and an infrared sensor module for detecting proximity with respect to a front surface of the display device 100; and an illuminance sensor module for measuring a degree of brightness of the outside.

The hole edge area HEA may surround the hole HL. Lines SL, DL1, DL2, EML, and DVL may be disposed in the hole edge area HEA on the substrate 200. Lines SL, DL1, DL2, EML, and DLV may bypass hole HL along hole edge region HEA. For example, the lines SL, DL1, DL2, EML, and DVL may be bent or curved according to the shape of the hole edge region HEA, without passing through the hole HL. On the substrate 200, the pixels PX1 and PX2 may not be disposed in the hole edge area HEA, so that the hole edge area HEA may be a non-display area.

In an embodiment, the hole HL may have a circular shape in a plan view, and the hole edge region HEA may have a circular ring shape in a plan view, but the embodiment is not limited thereto. In another embodiment, the hole HL may have a polygonal shape or an elliptical shape, etc. in a plan view. Although fig. 2 illustrates that one hole HL is formed in the display area DA, the embodiment is not limited thereto, and a plurality of holes HL may be formed in the display area DA.

Fig. 3 is a schematic cross-sectional view illustrating the display area DA of the display device 100 of fig. 2. For example, fig. 3 shows the first pixel PX1 or the second pixel PX2 of the display device 100 of fig. 1.

Referring to fig. 3, the display device 100 (see fig. 1) may include a transistor TR, a capacitor CAP, a light emitting element EL, and an encapsulation layer 290 disposed on a substrate 200.

The substrate 200 may be a transparent insulating substrate. For example, the substrate 200 may be formed of (or may include) glass, quartz, plastic, or the like.

A semiconductor layer 210 may be disposed on the substrate 200. The semiconductor layer 210 may be formed of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The semiconductor layer 210 may include a source region, a drain region, and a channel region disposed between the source region and the drain region. The source and drain regions may be doped with P-type impurities or N-type impurities, and the channel region may be doped with impurities having a type different from that of the source and drain regions.

A first insulating layer 211 may be disposed on the semiconductor layer 210. The first insulating layer 211 may be formed on the substrate 200 to cover the semiconductor layer 210 or to overlap the semiconductor layer 210. The first insulating layer 211 may insulate the gate electrode 220 from the semiconductor layer 210. The first insulating layer 211 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

The gate electrode 220 may be disposed on the first insulating layer 211. The gate electrode 220 may overlap with a channel region of the semiconductor layer 210. The gate electrode 220 may be formed of a conductive material such as a metal or a metal alloy. For example, the gate electrode 220 may be formed of molybdenum (Mo), copper (Cu), or the like.

A second insulating layer 212 may be disposed on the gate electrode 220. The second insulating layer 212 may be formed on the first insulating layer 211 to cover the gate electrode 220 or overlap the gate electrode 220. The second insulating layer 212 may insulate the capacitor electrode 230 from the gate electrode 220. The second insulating layer 212 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

The capacitor electrode 230 may be disposed on the second insulating layer 212. The capacitor electrode 230 may overlap the gate electrode 220. The capacitor electrode 230 may be formed of a conductive material such as a metal or a metal alloy. For example, the capacitor electrode 230 may be formed of molybdenum (Mo), copper (Cu), or the like. The gate electrode 220 and the capacitor electrode 230 may form a capacitor CAP.

A third insulating layer 213 may be disposed on the capacitor electrode 230. The third insulating layer 213 may be formed on the second insulating layer 212 to overlap the capacitor electrode 230. The third insulating layer 213 may insulate the source and drain electrodes 241 and 242 from the capacitor electrode 230. The third insulating layer 213 may be formed of an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

The source electrode 241 and the drain electrode 242 may be disposed on the third insulating layer 213. The source electrode 241 may be electrically connected to a source region of the semiconductor layer 210, and the drain electrode 242 may be electrically connected to a drain region of the semiconductor layer 210. Each of the source electrode 241 and the drain electrode 242 may be formed of a conductive material such as a metal or a metal alloy. For example, each of the source electrode 241 and the drain electrode 242 may be formed of aluminum (Al), titanium (Ti), copper (Cu), or the like. The semiconductor layer 210, the gate electrode 220, the source electrode 241, and the drain electrode 242 may form a transistor TR.

A fourth insulating layer 214 may be disposed on the source electrode 241 and the drain electrode 242. A fourth insulating layer 214 may be formed on the third insulating layer 213 to overlap the source and drain electrodes 241 and 242. The fourth insulating layer 214 may protect the transistor TR and may provide a flat surface for an upper portion of the transistor TR. Therefore, the fourth insulating layer 214 may have a relatively large thickness. For example, the thickness of fourth insulating layer 214 may be greater than the thickness of first insulating layer 211, the thickness of second insulating layer 212, and the thickness of third insulating layer 213. The fourth insulating layer 214 may be formed of an organic insulating material such as Polyimide (PI).

A connection electrode 250 may be disposed on the fourth insulating layer 214. The connection electrode 250 may be electrically connected to the source electrode 241 or the drain electrode 242. The connection electrode 250 may be formed of a conductive material such as a metal or a metal alloy. For example, the connection electrode 250 may be formed of aluminum (Al), titanium (Ti), copper (Cu), or the like.

A fifth insulating layer 215 may be disposed on the connection electrode 250. The fifth insulating layer 215 may be formed on the fourth insulating layer 214 to cover the connection electrode 250 or to overlap the connection electrode 250. The fifth insulating layer 215 may be formed of an organic insulating material such as Polyimide (PI).

A first electrode 260 may be disposed on the fifth insulating layer 215. The first electrode 260 may be electrically connected to the connection electrode 250. The first electrode 260 may be formed of a conductive material such as a metal or a transparent conductive oxide.

A sixth insulating layer 216 may be disposed on the first electrode 260. The sixth insulating layer 216 may include a pixel opening exposing a central portion of the first electrode 260. The sixth insulating layer 216 may separate the second electrode 280 from the edge of the first electrode 260 to prevent an arc or the like from occurring between the edge of the first electrode 260 and the second electrode 280. The sixth insulating layer 216 may be formed of an organic insulating material such as Polyimide (PI).

A light emitting layer 270 may be disposed on the first electrode 260. The light emitting layer 270 may be disposed on the first electrode 260 exposed by the pixel opening. The light emitting layer 270 may include at least one of an organic light emitting material and quantum dots.

In an embodiment, the organic light emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. For example, the low molecular weight organic compound may include copper phthalocyanine, N' -diphenylbenzidine, tris- (8-hydroxyquinoline) aluminum, and the like, and the high molecular weight organic compound may include poly (3, 4-ethylenedioxythiophene), polyaniline, polyphenylene vinylene (poly-phenylene vinylene), polyfluorene, and the like.

In embodiments, the quantum dots may include a core comprising a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, or a combination thereof. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may serve as a protective layer for maintaining semiconductor characteristics by preventing chemical modification of the core, and may serve as a charging layer for imparting electrophoretic characteristics to the quantum dot.

A second electrode 280 may be disposed on the light emitting layer 270. The second electrode 280 may also be disposed on the sixth insulating layer 216. The second electrode 280 may face the first electrode 260 with the light emitting layer 270 interposed between the first electrode 260 and the second electrode 280. The second electrode 280 may be formed of a conductive material such as a metal or a transparent conductive oxide. The first electrode 260, the light-emitting layer 270, and the second electrode 280 may form or constitute a light-emitting element EL. Since the first electrode 260 is electrically connected to the connection electrode 250, the light emitting element EL may be electrically connected to the connection electrode 250.

An encapsulation layer 290 may be disposed on the second electrode 280. The encapsulation layer 290 may include at least one inorganic layer and at least one organic layer. The encapsulation layer 290 may be disposed on the light emitting element EL to prevent external impurities from being introduced into the light emitting element EL, and the encapsulation layer 290 may protect the light emitting element EL from external impact.

In an embodiment, the encapsulation layer 290 may include a first inorganic layer, a second inorganic layer disposed over the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer. The first inorganic layer and the second inorganic layer can reduce or substantially prevent impurities such as oxygen and moisture from penetrating into the light emitting element EL. The organic layer may improve the sealing characteristics of the encapsulation layer 290, relieve internal stress of the first and second inorganic layers, compensate for defects in the first and second inorganic layers, and provide a flat top surface for the second inorganic layer.

Fig. 4 is a schematic plan view illustrating an example of the periphery of the hole HL of the display device 100 of fig. 2. Fig. 4 illustrates the first and second data lines DL1 and DL2 of the display device 100 of fig. 1.

Referring to fig. 2, 3 and 4, the first and second data lines DL1 and DL2 may be disposed in the display area DA and the hole edge area HEA on the substrate 200.

In the display area DA, the first data line DL1 may extend in a first direction DR1, and may be arranged in a second direction DR2 crossing or orthogonal to the first direction DR 1. The first data line DL1 may bypass the hole HL along the hole edge area HEA.

In the display area DA, the second data lines DL2 may extend in the first direction DR1, and may be alternately arranged with the first data lines DL1 in the second direction DR 2. The second data line DL2 may bypass the hole HL along the hole edge area HEA.

In an embodiment, the first data line DL1 may include a first wiring LN1 and a third wiring LN3 disposed in the second direction DR2 in the display area DA, and the second data line DL2 may include a second wiring LN2 and a fourth wiring LN4 disposed in the second direction DR2 in the display area DA. In this case, in the display area DA, the second wiring LN2 may be positioned adjacent to the first wiring LN1 in the second direction DR2, the third wiring LN3 may be positioned adjacent to the second wiring LN2 in the second direction DR2, and the fourth wiring LN4 may be positioned adjacent to the third wiring LN3 in the second direction DR 2. In other words, in the display area DA, the first wiring LN1, the second wiring LN2, the third wiring LN3, and the fourth wiring LN4 may be sequentially arranged in the second direction DR 2.

In the embodiment, the first portion of each of the first wiring LN1, the second wiring LN2, the third wiring LN3, and the fourth wiring LN4, which is provided in the display region DA, and the second portion of each of the first wiring LN1, the second wiring LN2, the third wiring LN3, and the fourth wiring LN4, which is provided in the hole edge region HEA, may be electrically connected to each other through a contact portion provided at a boundary of the display region DA and the hole edge region HEA. For example, the first portion of each of the first wiring LN1, the second wiring LN2, the third wiring LN3, and the fourth wiring LN4 and one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250 may be provided on the same layer. A second portion of each of the first wiring LN1, the second wiring LN2, the third wiring LN3, and the fourth wiring LN4 and another one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250 may be provided on the same layer. The contact portion may be disposed on the same layer as yet another one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250.

Since the hole edge area HEA is a non-display area, as the area of the hole edge area HEA is reduced, the dead space of the display device can be reduced. In the case where the area of the hole edge area HEA is reduced, the interval (or distance) between the respective wirings provided in the hole edge area HEA is reduced. However, in the case where the first and second data lines DL1 and DL2 are alternately arranged in the hole edge region HEA, the interval between the first and second data lines DL1 and DL2 is reduced, so that the coupling between the first and second data lines DL1 and DL2 may occur. In the case where the coupling between the first and second data lines DL1 and DL2 occurs, the data signal transmitted through the second data line DL2 may be distorted due to the voltage variation of the data signal transmitted through the first data line DL1, and the data signal transmitted through the first data line DL1 may be distorted due to the voltage variation of the data signal transmitted through the second data line DL 2.

In order to prevent coupling between the first and second data lines DL1 and DL2 in the hole edge region HEA, at least one of the first data lines DL1 may cross at least one of the second data lines DL2 in the hole edge region HEA such that the first data lines DL1 may be aggregated or adjacent to each other and the second data lines DL2 may be aggregated or adjacent to each other. In other words, in the hole edge region HEA, the first data lines DL1 may be concentrated on each other, and the second data lines DL2 may be concentrated on each other. For example, in the hole edge region HEA, the first wiring LN1 and the third wiring LN3 may be grouped with each other, and the second wiring LN2 and the fourth wiring LN4 may be grouped with each other.

In an embodiment, the first and second data lines DL1 and DL2 may include two data lines, respectively, and a first data line DL1 of the first data lines DL1 disposed between the second data lines DL2 may cross a second data line DL2 of the second data lines DL2 disposed between the first data lines DL 1. In this case, the first data line DL1 may be the third wiring LN3, and the second data line DL2 may be the second wiring LN 2. In other words, third wiring LN3 provided between second wiring LN2 and fourth wiring LN4 may cross second wiring LN2 provided between first wiring LN1 and third wiring LN 3.

In an embodiment, in a region CA where the second wiring LN2 intersects with the third wiring LN3, the second wiring LN2 may extend in a third direction DR3 different from the first direction DR1 and the second direction DR2, and the third wiring LN3 may extend in a fourth direction DR4 intersecting with the third direction DR 3. For example, the third direction DR3 may be at an acute angle with the first direction DR1 in a counterclockwise direction from the first direction DR1, and the fourth direction DR4 may be at an acute angle with the first direction DR1 in a clockwise direction from the first direction DR 1. In this case, the second wiring LN2 extending in the first direction DR1 in the display area DA may be bent in the third direction DR3 in the area CA where the second wiring LN2 crosses the third wiring LN3, and the third wiring LN3 extending in the first direction DR1 in the display area DA may be bent in the fourth direction DR4 in the area CA where the second wiring LN2 crosses the third wiring LN 3. In an embodiment, the fourth direction DR4 may be substantially orthogonal to the third direction DR 3.

In an embodiment, in the hole edge region HEA, the first data lines DL1 may overlap each other in a plan view, and the second data lines DL2 may overlap each other in a plan view. For example, in the hole edge region HEA, the third wiring LN3 may overlap with the first wiring LN1 in a plan view, and the second wiring LN2 may overlap with the fourth wiring LN4 in a plan view. Since the first data lines DL1 overlap each other in a plan view and the second data lines DL2 overlap each other in a plan view in the hole edge region HEA, coupling between the first data lines DL1 and the second data lines DL2 may be reduced or substantially prevented. The area occupied by the first and second data lines DL1 and DL2 in the hole edge region HEA may be reduced, so that the area of the hole edge region HEA may be reduced.

In an embodiment, as shown in fig. 4, in the hole edge region HEA, the first data lines DL1 may completely overlap each other in a plan view, and the second data lines DL2 may completely overlap each other in a plan view, but the embodiment is not limited thereto. In another embodiment, in the hole edge region HEA, the first data lines DL1 may partially overlap each other in a plan view, and the second data lines DL2 may partially overlap each other in a plan view.

Fig. 5 is a schematic sectional view taken along line I-I' of fig. 4.

Referring to fig. 3,4 and 5, the scan line SL, the first data line DL1, the second data line DL2 and the driving voltage line DVL bypassing the hole HL may be disposed in the hole edge region HEA on the substrate 200.

At least one wiring of the first data line DL1 and at least one wiring of the second data line DL2 in the hole edge area HEA may be disposed on the same layer as at least one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250 disposed in the display area DA. In an embodiment, at least one wiring in the first data line DL1 and at least one wiring in the second data line DL2 in the hole edge area HEA and at least one of the source electrode 241, the drain electrode 242, and the connection electrode 250 in the display area DA may be disposed on the same layer. For example, the first wiring LN1 and the second wiring LN2 in the hole edge region HEA and the connection electrode 250 in the display region DA may be provided on the same layer, and the third wiring LN3 and the fourth wiring LN4 in the hole edge region HEA and the source electrode 241 and the drain electrode 242 in the display region DA may be provided on the same layer. In other words, in the hole edge region HEA, the first wiring LN1 and the second wiring LN2 may be provided on the fourth insulating layer 214, and the third wiring LN3 and the fourth wiring LN4 may be provided on the third insulating layer 213. Since the second wiring LN2 and the third wiring LN3 are provided on mutually different layers in the hole edge region HEA, the second wiring LN2 and the third wiring LN3 can be insulated from each other in the region CA where the second wiring LN2 and the third wiring LN3 intersect.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 6 and 7. In the display device according to the embodiment to be described with reference to fig. 6 and 7, a description of components substantially the same as or similar to those of the display device according to one embodiment described with reference to fig. 4 and 5 will be omitted.

Fig. 6 is a schematic plan view illustrating an example of the periphery of the hole HL of the display device 100 of fig. 2. Fig. 6 illustrates the first and second data lines DL1 and DL2 of the display device 100 of fig. 1. Fig. 7 is a schematic sectional view taken along line II-II' of fig. 6.

Referring to fig. 6 and 7, in an embodiment, in the hole edge region HEA, the first data lines DL1 may be adjacent to each other in a plan view, and the second data lines DL2 may be adjacent to each other in a plan view. In other words, the first data lines DL1 may become closer to each other in the hole edge area HEA without overlapping each other in a plan view, and the second data lines DL2 may become closer to each other in the hole edge area HEA without overlapping each other in a plan view. For example, in the hole edge region HEA, the third wiring LN3 may be adjacent to the first wiring LN1 in a plan view, and the second wiring LN2 may be adjacent to the fourth wiring LN4 in a plan view. Since the first data lines DL1 are adjacent to each other in a plan view and the second data lines DL2 are adjacent to each other in a plan view in the hole edge region HEA, coupling between the first data lines DL1 and the second data lines DL2 may be reduced or substantially prevented.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 8 and 9. In the display device according to the embodiment to be described with reference to fig. 8 and 9, a description of components substantially the same as or similar to those of the display device according to the embodiment described with reference to fig. 6 and 7 will be omitted.

Fig. 8 is a schematic plan view illustrating an example of the periphery of the hole HL of the display device 100 of fig. 2. Fig. 8 illustrates the first and second data lines DL1 and DL2 of the display device 100 of fig. 1.

Referring to fig. 8, in the embodiment, in a region CA where the second wiring LN2 crosses the third wiring LN3, the second wiring LN2 may extend in a third direction DR3 different from the first direction DR1 and the second direction DR2, and the third wiring LN3 may extend in the first direction DR 1. For example, the third direction DR3 may be at an acute angle to the first direction DR1 in a counterclockwise direction from the first direction DR 1. In this case, the second wiring LN2 extending in the first direction DR1 in the display area DA may be bent in the third direction DR3 in the area CA where the second wiring LN2 crosses the third wiring LN3, and the third wiring LN3 extending in the first direction DR1 in the display area DA may not be bent in the area CA where the second wiring LN2 crosses the third wiring LN 3.

Fig. 9 is a schematic sectional view taken along line III-III' of fig. 8.

Referring to fig. 3, 8 and 9, in an embodiment, at least one wiring of the first data line DL1 and at least one wiring of the second data line DL2 in the hole edge area HEA and at least one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242 and the connection electrode 250 in the display area DA may be disposed on the same layer. For example, the first wiring LN1 in the hole edge region HEA and the source electrode 241 and the drain electrode 242 in the display region DA may be provided on the same layer, the second wiring LN2 in the hole edge region HEA and the capacitor electrode 230 in the display region DA may be provided on the same layer, the third wiring LN3 in the hole edge region HEA and the connection electrode 250 in the display region DA may be provided on the same layer, and the fourth wiring LN4 in the hole edge region HEA and the gate electrode 220 in the display region DA may be provided on the same layer. In other words, in the hole edge region HEA, the first wiring LN1 may be provided on the third insulating layer 213, the second wiring LN2 may be provided on the second insulating layer 212, the third wiring LN3 may be provided on the fourth insulating layer 214, and the fourth wiring LN4 may be provided on the first insulating layer 211.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 10 and 11. In the display device according to the embodiment to be described with reference to fig. 10 and 11, a description of components substantially the same as or similar to those of the display device according to the embodiment described with reference to fig. 8 and 9 will be omitted.

Fig. 10 is a schematic plan view illustrating an example of the periphery of the hole HL of the display device 100 of fig. 2. Fig. 10 illustrates the first data line DL1, the second data line DL2, and the driving voltage line DVL of the display device 100 of fig. 1.

Referring to fig. 2 and 10, the first data line DL1, the second data line DL2, and the driving voltage line DVL may be disposed in the display area DA and the hole edge area HEA on the substrate 200.

Some of the driving voltage lines DVL may extend in the first direction DR1 while being arranged in the second direction DR2 in the display area DA, and the remaining driving voltage lines DVL may extend in the second direction DR2 while being arranged in the first direction DR1 in the display area DA. The driving voltage line DVL may bypass the hole HL along the hole edge area HEA.

In an embodiment, the driving voltage line DVL may include a fifth wiring LN5 extending in the first direction DR1 in the display area DA, and a sixth wiring LN6 and a seventh wiring LN7 extending in the second direction DR2 in the display area DA. In the display region DA, a fifth wiring LN5 may be provided between the second wiring LN2 and the third wiring LN3 in a plan view.

In an embodiment, in the hole edge region HEA, the driving voltage line DVL may be disposed between the first data line DL1 and the second data line DL2 in a plan view. For example, in the hole edge region HEA, the fifth wiring LN5, the sixth wiring LN6, and the seventh wiring LN7 may overlap with each other in a plan view, and the fifth wiring LN5, the sixth wiring LN6, and the seventh wiring LN7 may be disposed between the second wiring LN2 and the third wiring LN3 in a plan view. Since the driving voltage line DVL configured to transmit the driving voltage, which may be a direct-current voltage, is disposed between the first data line DL1 and the second data line DL2 in a plan view in the hole edge region HEA, the driving voltage line DVL may be shielded between the first data line DL1 and the second data line DL2, so that coupling between the first data line DL1 and the second data line DL2 may be further reduced or substantially prevented.

Fig. 11 is a schematic sectional view taken along line IV-IV' of fig. 10.

Referring to fig. 3, 10 and 11, in an embodiment, at least one wiring of the first data line DL1, at least one wiring of the second data line DL2, and the driving voltage line DVL in the hole edge area HEA may be disposed on the same layer as at least one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250 disposed in the display area DA. In an embodiment, at least one wiring of the first data line DL1 and at least one wiring of the second data line DL2 in the hole edge area HEA and at least one of the gate electrode 220 and the capacitor electrode 230 in the display area DA may be disposed on the same layer, and the driving voltage line DVL in the hole edge area HEA and at least one of the gate electrode 220, the capacitor electrode 230, the source electrode 241, the drain electrode 242, and the connection electrode 250 in the display area DA may be disposed on the same layer. For example, the first wiring LN1, the fourth wiring LN4, and the fifth wiring LN5 in the hole edge region HEA and the gate electrode 220 in the display region DA may be provided on the same layer, the second wiring LN2 and the third wiring LN3 in the hole edge region HEA and the capacitor electrode 230 in the display region DA may be provided on the same layer, the sixth wiring LN6 in the hole edge region HEA and the source electrode 241 and the drain electrode 242 in the display region DA may be provided on the same layer, and the seventh wiring LN7 in the hole edge region HEA and the connection electrode 250 in the display region DA may be provided on the same layer. In other words, in the hole edge region HEA, the first wiring LN1, the fourth wiring LN4, and the fifth wiring LN5 may be provided on the first insulating layer 211, the second wiring LN2 and the third wiring LN3 may be provided on the second insulating layer 212, the sixth wiring LN6 may be provided on the third insulating layer 213, and the seventh wiring LN7 may be provided on the fourth insulating layer 214.

Hereinafter, a display device according to an embodiment will be described with reference to fig. 12 and 13. In the display device according to the embodiment to be described with reference to fig. 12 and 13, description of components substantially the same as or similar to those of the display device according to the embodiment described with reference to fig. 10 and 11 will be omitted.

Fig. 12 is a schematic plan view illustrating an example of the periphery of the hole HL of the display device 100 of fig. 2. Fig. 12 illustrates the first data line DL1, the second data line DL2, the emission control line EML, and the driving voltage line DVL of the display device 100 of fig. 1.

Referring to fig. 2 and 12, the first data line DL1, the second data line DL2, the emission control line EML, and the driving voltage line DVL may be disposed in the display area DA and the hole edge area HEA on the substrate 200.

The emission control lines EML may extend in the second direction DR2 in the display area DA, and may be arranged in the first direction DR 1. The emission control line EML may bypass the hole HL along the hole edge region HEA.

In an embodiment, the emission control line EML may include an eighth wiring LN8 and a ninth wiring LN9 arranged in the first direction DR1 in the display area DA.

In an embodiment, in the hole edge region HEA, the emission control line EML may overlap the first and second data lines DL1 and DL2 in a plan view. For example, in the hole edge region HEA, the eighth wiring LN8 may overlap with the first wiring LN1 in a plan view, and the ninth wiring LN9 may overlap with the fourth wiring LN4 in a plan view.

Fig. 13 is a schematic sectional view taken along line V-V' of fig. 12.

Referring to fig. 3, 12 and 13, in the embodiment, at least one wiring of the first data line DL1 and at least one wiring of the second data line DL2 in the hole edge area HEA and at least one of the gate electrode 220 and the capacitor electrode 230 in the display area DA may be disposed on the same layer, and the emission control line EML in the hole edge area HEA and the connection electrode 250 in the display area DA may be disposed on the same layer. For example, the first wiring LN1 and the fourth wiring LN4 in the hole edge region HEA and the gate electrode 220 in the display region DA may be provided on the same layer, the second wiring LN2 and the third wiring LN3 in the hole edge region HEA and the capacitor electrode 230 in the display region DA may be provided on the same layer, and the eighth wiring LN8 and the ninth wiring LN9 in the hole edge region HEA and the connection electrode 250 in the display region DA may be provided on the same layer. In other words, in the hole edge region HEA, the first wiring LN1, the fourth wiring LN4, and the fifth wiring LN5 may be provided on the first insulating layer 211, the second wiring LN2 and the third wiring LN3 may be provided on the second insulating layer 212, the sixth wiring LN6 may be provided on the third insulating layer 213, and the seventh wiring LN7, the eighth wiring LN8, and the ninth wiring LN9 may be provided on the fourth insulating layer 214.

Since the area of the hole edge region HEA is relatively small, in the case where the interval or distance between the first and second data lines DL1 and DL2 and the emission control line EML is reduced in the hole edge region HEA, the coupling between the first and second data lines DL1 and DL2 and the emission control line EML may occur. In the case where the coupling between the first and second data lines DL1 and DL2 and the emission control line EML occurs, the data signals transmitted through the first and second data lines DL1 and DL2 may be distorted due to a variation in the emission control signal transmitted through the emission control line EML.

However, in the embodiment, since at least one wiring of the first data line DL1 and at least one wiring of the second data line DL2 in the hole edge region HEA are disposed on the same layer as at least one of the gate electrode 220 and the capacitor electrode 230 in the display region DA, and the emission control line EML in the hole edge region HEA is disposed on the same layer as the connection electrode 250 in the display region DA, and since the thickness of the fourth insulating layer 214 disposed between the first data line DL1 and the second data line DL2 and the emission control line EML is relatively large, the interval between the first data line DL1 and the second data line DL2 and the emission control line EML in the vertical direction may be increased. Accordingly, coupling between the first and second data lines DL1 and DL2 and the emission control line EML may be reduced or substantially prevented.

Fig. 14 is a schematic plan view illustrating a part of the display device 100 according to the embodiment.

Referring to fig. 14, the substrate 200 of the display device 100 according to the embodiment may include a display area DA, a peripheral area PA, and a hole edge area HEA. The display apparatus 100 to be described with reference to fig. 14 may be substantially the same as or similar to the display apparatus 100 described with reference to fig. 2, except for the shape of the hole HL. Therefore, redundant description thereof will be omitted.

In an embodiment, the hole HL may have a rectangular shape with rounded corners in a plan view, and the hole edge region HEA may have a rectangular ring shape with rounded corners in a plan view.

Fig. 15 is a schematic sectional view illustrating an electronic device 1000 according to an embodiment.

Referring to fig. 15, the electronic device 1000 may include the display device 100 and the function module 300 according to an embodiment. The display device 100 may include a display area DA, a peripheral area PA, and a hole edge area HEA. The display apparatus 100 of fig. 15 may be substantially the same as the display apparatus 100 described with reference to fig. 1 to 14.

The function module 300 may be disposed under the display device 100. The function module 300 may be disposed under the display device 100 to overlap the hole HL.

In an embodiment, the functional module 300 may include: a camera module for photographing (or recognizing) an image of an object positioned above the front surface of the display device 100; a facial recognition sensor module for detecting a user's face; the pupil identification sensor module is used for detecting the pupil of the user; the device comprises an acceleration sensor module and a geomagnetic sensor module, wherein the acceleration sensor module and the geomagnetic sensor module are used for determining the movement of the display device; a proximity sensor module and an infrared sensor module for detecting a proximity with respect to a front surface of the display device; and an illuminance sensor module for measuring a degree of brightness of the outside.

The display device according to the embodiment may be applied to a display device included in a computer, a laptop computer, a mobile phone, a smart tablet, a PMP, a PDA, or an MP3 player, etc.

Although the display device and the electronic device according to some embodiments have been described with reference to the drawings, the illustrated embodiments are examples, and the illustrated embodiments may be modified and changed by a person having ordinary skill in the related art without departing from the technical spirit described in the present disclosure.