阅读说明：本技术 减少金属栅极的回蚀刻中的图案负载
(Reducing pattern loading in metal gate etch back
) 是由 张博钦
吴伟豪
林立德
林斌彦 于 2018-11-22 设计创作，主要内容包括：一种方法包括去除伪栅极以在栅极间隔件之间留下沟槽,形成延伸到沟槽中的栅极电介质,在栅极电介质上方沉积金属层,其中,金属层包括延伸到沟槽中的部分,将填充区沉积到沟槽中,其中,金属层具有位于填充区的相对侧上的第一垂直部分和第二垂直部分,回蚀刻金属层,其中,填充区至少比金属层凹进得更少,以及金属层的部分的剩余部分形成栅电极,将介电材料沉积到沟槽中,并且实施平坦化以去除介电材料的多余部分。介电材料的位于沟槽中的部分在栅电极上方形成介电硬掩模的至少部分。本发明的实施例涉及减少金属栅极的回蚀刻中的图案负载。(A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, wherein the metal layer includes a portion extending into the trench, depositing a fill region into the trench, wherein the metal layer has a first vertical portion and a second vertical portion on opposite sides of the fill region, etching back the metal layer, wherein the fill region is at least less recessed than the metal layer, and a remaining portion of the metal layer forms the gate electrode, depositing a dielectric material into the trench, and performing planarization to remove an excess portion of the dielectric material. The portion of the dielectric material located in the trench forms at least part of a dielectric hard mask over the gate electrode. Embodiments of the invention relate to reducing pattern loading in an etch-back of a metal gate.)
1. A method of forming a semiconductor device, comprising:
removing the first dummy gate to leave a first trench between the first gate spacers;
forming a first gate dielectric extending into the first trench;
depositing a metal layer over the first gate dielectric, wherein the metal layer includes a first portion that extends into the first trench;
depositing a fill region into the first trench, wherein the metal layer has a first vertical portion and a second vertical portion on opposite sides of the fill region;
etching back the metal layer, wherein the filled region is at least less recessed than the metal layer, and wherein a remaining portion of the first vertical portion of the metal layer forms a gate electrode;
depositing a dielectric material into the first trench; and
performing planarization to remove excess portions of the dielectric material outside of the first trench, wherein the portion of the dielectric material located in the first trench forms at least part of a dielectric hard mask over the gate electrode.
2. The method of claim 1, further comprising:
removing the second dummy gate to leave a second trench between the second gate spacers;
forming a first gate dielectric extending into the second trench, wherein the metal layer comprises a second portion that completely fills the second trench.
3. The method of claim 2, wherein a thickness of the first vertical portion of the metal layer is equal to half a width of the second vertical portion of the metal layer in the second trench.
4. The method of claim 1 wherein the fill region is formed of a non-dielectric material, and further comprising removing the fill region prior to depositing the dielectric material into the first trench.
5. The method of claim 4, wherein the fill region comprises amorphous silicon or polysilicon.
6. The method of claim 1, wherein the dielectric material is deposited on the fill region.
7. The method of claim 1, wherein the fill region is formed of an additional dielectric material.
8. The method of claim 1, wherein after etching back the metal layer, the gate electrode has a shape of a pot, and the pot includes:
a bottom; and
a sidewall portion surrounding a bottom of the filling region.
9. A method of forming a semiconductor device, comprising:
forming a gate dielectric extending into a trench, wherein the trench is located between opposing gate spacers;
depositing a work function layer over the gate dielectric;
depositing a fill region on the work function layer, wherein the fill region completely fills the trench;
performing planarization to remove the work function layer and the redundant part of the filling area to form a metal gate comprising the work function layer;
etching back the metal gate, wherein the filling region is not etched in the etching back;
removing the filling area; and
a dielectric hard mask is formed in the trench and over the etched back metal gate.
10. A semiconductor device, comprising:
a semiconductor region;
a gate spacer located over the semiconductor region;
a gate dielectric on the semiconductor region;
a gate electrode over the gate dielectric and between the gate spacers; wherein the gate electrode comprises a metal layer forming a tub;
a dielectric hard mask comprising a first portion over the gate electrode; and
a gate contact plug extending into the dielectric hard mask, wherein the gate contact plug comprises:
a first portion higher than a top surface of the gate electrode; and
a second portion extending into the gate electrode, wherein the gate electrode includes a first vertical portion and a second vertical portion contacting opposite sidewalls of the second portion of the gate contact plug.
Technical Field
Embodiments of the invention relate to reducing pattern loading in an etch-back of a metal gate.
Background
In the formation of a metal gate and corresponding gate contact plug for a fin field effect transistor (FinFET), the metal gate is typically recessed, and a hard mask is filled into the recess formed as a result of the recess of the metal gate. Portions of the hard mask are subsequently removed to form contact openings through which the metal gates are exposed. Forming a gate contact plug to connect to the metal gate.
The recessing of the hard mask results in metal gate loss, which requires the metal gate to be formed higher than its final height in order to compensate for the height of the loss. The increased height of the metal gate results in gap filling difficulties for forming the metal gate. Also, the recesses of the hard mask are subject to pattern loading effects in the etching of the hard mask, and the pattern loading effects cause some metal gates to be recessed more than other metal gates. For example, the transistors in the wafer/die may include short channel transistors, mid-channel transistors, and/or long channel transistors. When the metal gates of the short, medium, and/or long channel transistors are etched simultaneously, pattern loading effects may cause the metal gate of the long channel transistor to be recessed more than the metal gate of the medium channel transistor, and the metal gate of the medium channel transistor to be recessed more than the metal gate of the short channel transistor.
Disclosure of Invention
An embodiment of the present invention provides a method of forming a semiconductor device, including: removing the first dummy gate to leave a first trench between the first gate spacers; forming a first gate dielectric extending into the first trench; depositing a metal layer over the first gate dielectric, wherein the metal layer includes a first portion that extends into the first trench; depositing a fill region into the first trench, wherein the metal layer has a first vertical portion and a second vertical portion on opposite sides of the fill region; etching back the metal layer, wherein the filled region is at least less recessed than the metal layer, and wherein a remaining portion of the first vertical portion of the metal layer forms a gate electrode; depositing a dielectric material into the first trench; and performing planarization to remove excess portions of the dielectric material outside the first trench, wherein the portion of the dielectric material in the first trench forms at least part of a dielectric hard mask over the gate electrode.
Another embodiment of the present invention provides a method of forming a semiconductor device, including: forming a gate dielectric extending into a trench, wherein the trench is located between opposing gate spacers; depositing a work function layer over the gate dielectric; depositing a fill region on the work function layer, wherein the fill region completely fills the trench; performing planarization to remove the work function layer and the redundant part of the filling area to form a metal gate comprising the work function layer; etching back the metal gate, wherein the filling region is not etched in the etching back; removing the filling area; and forming a dielectric hard mask in the trench and over the etched back metal gate.
Still another embodiment of the present invention provides a semiconductor device including: a semiconductor region; a gate spacer located over the semiconductor region; a gate dielectric on the semiconductor region; a gate electrode over the gate dielectric and between the gate spacers; wherein the gate electrode comprises a metal layer forming a tub; a dielectric hard mask comprising a first portion over the gate electrode; and a gate contact plug extending into the dielectric hard mask, wherein the gate contact plug comprises: a first portion higher than a top surface of the gate electrode; and a second portion extending into the gate electrode, wherein the gate electrode includes a first vertical portion and a second vertical portion contacting opposite sidewalls of the second portion of the gate contact plug.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-4, 5A, 5B, and 6-17 are perspective and cross-sectional views of intermediate stages in forming fin field effect transistors (finfets) with different channel lengths (gate widths) in accordance with some embodiments.
Fig. 18-25 are perspective and cross-sectional views of intermediate stages in forming finfets with different gate widths in accordance with some embodiments.
Fig. 26 and 27 are cross-sectional and top views, respectively, of a replacement gate of a FinFET in accordance with some embodiments.
Fig. 28 illustrates a process flow for forming finfets with different gate widths in accordance with some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Transistors and methods of forming the same are provided according to various exemplary embodiments. An intermediate stage of forming a transistor is shown according to some embodiments. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and exemplary embodiments. In the illustrated embodiment, the concept of the present invention is explained using the formation of a fin field effect transistor (FinFET) as an example. Planar transistors may also employ the concepts of the present invention.
Fig. 1-17 illustrate cross-sectional and perspective views of intermediate stages in forming a FinFET in accordance with some embodiments of the present invention. The steps shown in fig. 1-17 are also schematically illustrated in the process flow 500 shown in fig. 25. Fig. 1 to 6 illustrate forming a semiconductor fin, a dummy gate stack, source and drain regions, a Contact Etch Stop Layer (CESL), an interlayer dielectric (ILD), and the like. The short channel transistor, the middle channel transistor, and the long channel transistor may employ the processes shown in fig. 1 to 6, and the transistors may be p-type or n-type.
Fig. 1 shows a perspective view of an initial structure. The initial structure comprises a wafer 10, wherein the wafer 10 further comprises a substrate 20. The substrate 20 may be a semiconductor substrate, wherein the semiconductor substrate may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. The substrate 20 may be doped with p-type impurities or n-type impurities. Isolation regions 22, such as Shallow Trench Isolation (STI) regions, may be formed to extend from the top surface of the substrate 20 into the substrate 20. The portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. According to some example embodiments, the top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other. According to some embodiments of the present invention, the semiconductor strips 24 are part of the original substrate 20, and thus the material of the semiconductor strips 24 is the same as the material of the substrate 20. According to an alternative embodiment of the present invention, the semiconductor strip 24 is a replacement strip formed by etching the portion of the substrate 20 between the STI regions 22 to form a recess, and performing epitaxy to regrow another semiconductor material in the recess. Thus, the semiconductor strips 24 are formed of a different semiconductor material than the substrate 20. According to some example embodiments, the semiconductor strips 24 are formed of silicon germanium, silicon carbon, or iii-v compound semiconductor materials.
STI regions 22 may include a pad oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High Density Plasma Chemical Vapor Deposition (HDPCVD), or Chemical Vapor Deposition (CVD). The STI region 22 also includes a dielectric material over the pad oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.
Referring to fig. 2, the STI region 22 is recessed such that the top of the semiconductor strip 24 protrudes higher than the top surface 22A of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding process is shown as process 502 in process flow 500 shown in fig. 28. The etching may be performed using a dry etching process in which NF is used3And NH3Or HF and NH3The mixture of (a) and (b) as an etching gas. During the etching process, a plasma may be generated. Argon may also be included. According to an alternative embodiment of the present invention, the recessed STI regions 22 are implemented using a wet etch process. For example, the etching chemistry may include an HF solution.
Referring to fig. 3, a dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fin 24'. The corresponding process is also illustrated as process 502 in process flow 500 shown in fig. 28. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate electrode 34 over the dummy gate dielectric 32. For example, polysilicon may be used to form dummy gate electrode 34, but other materials may also be used. Each of the dummy gate stacks 30 may further include one (or more) hard mask layer(s) 36 located over the dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or a multilayer thereof. The dummy gate stack 30 may span over a single or multiple protruding fins 24' and/or STI regions 22. The longitudinal direction of the dummy gate stack 30 is perpendicular to the longitudinal direction of the protruding fin 24'.
Next, gate spacers 38 are formed on sidewalls of the dummy gate stack 30. According to some embodiments of the present invention, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon carbonitride, or the like and may have a single layer structure or a multi-layer structure including a plurality of dielectric layers. According to some embodiments of the present invention, the gate spacers 38 are formed of silicon nitride, silicon oxycarbonitride, or the like. The thickness of the gate spacer 38 may be less than about 10 nm.
An etching step (hereinafter referred to as source/drain recess) is then performed to etch the portions of the protruding fins 24' not covered by the dummy gate stack 30 and the gate spacers 38, resulting in the structure shown in fig. 4. The recess may be anisotropic and thus the portion of the fin 24' directly under the dummy gate stack 30 and the gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 is lower than the top surface 22A of the STI region 22. Thus, a recess 40 is formed between the STI regions 22. The grooves 40 are located on opposite sides of the dummy gate stack 30.
Next, epitaxial regions (source/drain regions) 42 are formed by selectively growing semiconductor material in the recesses 40, resulting in the structure in fig. 5A. A corresponding process is shown in process flow 500 of fig. 28 as process 504. According to some exemplary embodiments, epitaxial region 42 comprises silicon germanium or silicon. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, either a p-type or n-type impurity may be doped in-situ as the epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), SiB, etc. may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like may be grown. According to an alternative embodiment of the present invention, epitaxial region 42 is formed of a group III-V compound semiconductor such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the epitaxial region 42 completely fills the recess 40, the epitaxial region 42 begins to expand horizontally and facets may be formed.
After the epitaxial step, the epitaxial region 42 may be further implanted with p-type impurities or n-type impurities to form source and drain regions, wherein the source and drain regions are denoted by reference numeral 42. According to an alternative embodiment of the present invention, the implantation step is skipped when the epitaxial region 42 is doped in-situ with a p-type impurity or an n-type impurity during the epitaxy to form the source/drain regions. The epitaxial source/drain regions 42 include lower portions formed in the STI regions 22 and upper portions formed above the top surfaces of the STI regions 22.
Fig. 5B illustrates the formation of source/drain regions 42 according to an alternative embodiment of the present invention. According to these embodiments, the protruding fin 24 'as shown in fig. 3 is not recessed and an epitaxial region 41 is grown on the protruding fin 24'. The material of epitaxial region 41 may be similar to the material of epitaxial semiconductor material 42 shown in fig. 5A, depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET. Thus, source/drain 42 includes protruding fin 24' and epitaxial region 41. Implantation may be performed to implant an n-type impurity or a p-type impurity.
Fig. 6 shows a perspective view of the structure after forming a Contact Etch Stop Layer (CESL)46 and an interlayer dielectric (ILD) 48. A corresponding process is shown in process flow 500 of fig. 28 as process 506. CESL 46 may be omitted. According to some embodiments of the present invention, and when forming the CESL 46, the CESL 46 may be formed of silicon nitride, silicon carbonitride, or the like. According to some embodiments of the invention, oxygen may be absent from CESL 46. For example, CESL 46 may be formed using a conformal deposition method such as ALD or CVD. ILD 48 may comprise a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition method. ILD 48 may also be formed of, for example, Tetraethylorthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) oxide (SiO)2) Silicon oxide-based oxygen-containing dielectric materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like. A planarization process, such as a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process, may be performed to planarize the ILD 48, the dummy gate stack 30 and the gateThe top surfaces of the spacers 38 are flush with each other.
Fig. 7 shows a cross-sectional view of an initial structure for forming an n-type FinFET short channel FinFET, a p-type FinFET short channel FinFET, a middle channel FinFET, and a long channel FinFET in device regions 100, 200, 300, and 400, respectively. The cross-sectional view of each of the illustrated FinFET regions shown in fig. 7 may correspond to a cross-sectional view taken from a vertical plane that includes line a-a in fig. 6. Details of the formation of each of the devices in regions 100, 200, 300 and 400 shown in fig. 7 can be found in fig. 1-6. The components in device regions 100, 200, 300, and 400 correspond to the components shown in fig. 6, except that some of the component numbers in fig. 6 are increased by the number "100", "200", "300", or "400" to distinguish these components from one another. For example, dummy gate stack 130 in device region 100 includes dummy gate dielectric 132, dummy gate electrode 134, and hard mask 136 corresponding to dummy gate dielectric 32, dummy gate electrode 34, and hard mask 36 in fig. 6. Source/ drain regions 142, 242, 342, and 442 are formed in device regions 100, 200, 300, and 400, respectively. Also, gate spacers 138, 238, 338 and 438 are formed in the device regions 100, 200, 300 and 400, respectively.
Line 22A is shown as a level representing the top surface of STI region 22 (fig. 7). The semiconductor fins 124 ', 224', 324 ', and 424' protrude higher than the top surface 22A. The channel lengths (gate widths) of the finfets in device regions 100, 200, 300, and 400 are L1, L2, L3, and L4, respectively. According to some embodiments of the invention, L1 ═ L2< L3< L4 is assumed. According to some embodiments of the invention, the gate lengths L1 and L2 of the short channel FinFET are less than about 17 nm. The gate length L3 of the mid-channel FinFET is in a range between about 38nm and about 50 nm. The gate length L4 of the long channel FinFET is in a range between about 90nm and about 260 nm. It should be understood that whether the gate is a long channel gate, a medium channel gate, or a short channel gate is relative and that the range of gate lengths may be different from that described previously.
Next, the dummy gate stacks 130, 230, 330, and 430 are removed, the openings 151, 251, 351, and 451, respectively, are formed, and the resulting structure is shown in fig. 8. A corresponding process is shown in the process flow 500 shown in fig. 28 as process 508. Top surfaces and sidewalls of the protruding semiconductor fins 124 ', 224', 324 ', and 424' may be exposed to the openings 151, 251, 351, and 451, respectively.
Next, referring to fig. 9, gate dielectric layers 152, 252, 352, and 452 are formed (replaced) in the device regions 100, 200, 300, and 400, respectively. The corresponding process is shown as process 510 in process flow 500 shown in fig. 28. Gate dielectric layers 152, 252, 352, and 452 extend into openings 151, 251, 351, and 451 (fig. 8), respectively. According to some embodiments of the present invention, gate dielectric layers 152, 252, 352, and 452 include Interfacial Layers (IL)154, 254, 354, and 454 as their respective lower portions. IL 154, 254, 354, and 454 are formed on exposed surfaces of the protruding fins. The ILs 154, 254, 354, and 454 may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition of the protruding fins 124 ', 224', 324 ', and 424'. IL 154, 254, 354, and 454 may be formed simultaneously in a common process.
Gate dielectric layers 152, 252, 352, and 452 may also include high-k dielectric layers 156, 256, 356, and 456 formed over respective ILs. High-k dielectric layers 156, 256, 356, and 456 may comprise a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, and the like. The high-k dielectric material has a dielectric constant (k value) greater than 3.9 and may be greater than about 7.0. The high-k dielectric layers 156, 256, 356, and 456 are formed as conformal layers and extend over the sidewalls of the protruding fins 124 ', 224', 324 ', and 424' and the sidewalls of the respective gate spacers 138, 238, 338, and 438. According to some embodiments of the invention, the high-k dielectric layers 156, 256, 356 and 456 are formed using ALD or CVD. The high-k dielectric layers 156, 256, 356, and 456 may be formed simultaneously in a common process.
Fig. 9-11 illustrate the formation of metal layers, wherein the metal layers form part of a replacement metal gate. The corresponding process is shown as process 512 in process flow 500 shown in fig. 28. The metal layer may include a work function layer, wherein a work function of the work function layer affects a threshold voltage of a corresponding FinFET. The metal layer may or may not include a non-work function metal layer below and/or above the work function layer, wherein the work function of the non-work function metal layer does not affect the threshold voltage of the resulting FinFET. For example, the metal layer may include a tungsten layer over the work function layer, and the tungsten layer is a non-work function layer. The metal layers presented in the illustrated embodiments are merely examples, and different combinations of metal layers may be employed. Also, according to other embodiments, each of the illustrated metal layers may or may not extend into any of the device regions 100, 200, 300, 400.
In fig. 9 to 11, stacked metal layers 58 are formed (fig. 11). The material of each of the stacked metal layers 58 may be selected based on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. Stacked metal layer 58 may include layers 58A, 58B, and 58C, which are referred to individually and in combination as metal layer 58. For example, when the FinFET is an n-type FinFET, the work function layer in the stacked metal layer 58 may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work function layer in the stacked metal layer 58 may include a TaN layer, a TiN layer over the TaN layer, and a TiAl layer over the TiN layer. The work function layer may also include TiAlC, TaSiC, and the like. The thickness of each of the work function layer and the diffusion barrier layer may be less than about 5nm, for example, between about 1nm and about 5 nm. According to some embodiments of the present invention, the stacked metal layers 58 are implemented using a conformal deposition method, such as ALD or CVD, such that the thickness of the vertical portions and the thickness of the horizontal portions of the stacked metal layers 58 (and each sub-layer) are equal or approximately equal to each other, e.g., the difference between the thickness of the horizontal portions and the vertical portions is less than about 20% or 10% of the thickness of the horizontal portions. In the discussion that follows, the materials and formation methods of layers 58A, 58B, and 58C are not separately discussed.
Referring to fig. 9, a first metal layer 58A, which may be a work function layer, is formed in the device region 200. The forming process may include blanket forming metal layer 58A and removing metal layer 58A from device regions 100, 300, and 400, for example, by a photolithography process.
Fig. 10 shows depositing metal layer 58B. The metal layer 58B extends into the openings 151, 251, 351, and 451, and covers the metal layer 58A. According to some embodiments of the invention, each of openings 151, 251, 351, and 451 has an unfilled portion.
Fig. 11 shows depositing metal layer 58C. According to some embodiments of the present invention, the remaining openings 151 and 251 are completely filled. The process is controlled so that the deposition of metal layer 58C stops once openings 151 and 251 are completely filled. In the example shown, deposition of metal layer 58C is stopped once opening 151 is completely filled, since opening 251 is filled earlier than opening 151. Overfill is selected to be as small as possible (providing process margin to ensure complete filling of openings 151 and 251). When the deposition of the metal layer 58C is stopped, the openings 351 and 451 still have unfilled portions. According to some embodiments of the present invention, after completely filling the opening 151, a metal layer 58C less than 5nm (or less than 2nm) thick is deposited as an overfill when deposition is stopped.
Next, referring to fig. 12, a fill layer 60 is deposited to fill the remaining portions of openings 351 and 451 (fig. 11). A corresponding process is shown as process 514 in process flow 500 shown in fig. 28. According to some embodiments of the present invention, the fill layer 60 is formed of a dielectric material, wherein the dielectric material is different from the material of the gate spacers 138/238/338/438 and ILD 48, and possibly different from the material of the CESL 46 (possibly the same as the material of the CESL 46). For example, the filling layer 60 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or the like. The filling layer 60 may be formed of polysilicon, amorphous silicon, or the like.
Fig. 13 illustrates a planarization process that removes the excess portion of stacked metal layer 58. A corresponding process is also shown as process 514 in the process flow 500 shown in fig. 28. The planarization process may be a Chemical Mechanical Polishing (CMP) process or a mechanical grinding process. Planarization may be performed using ILD 48 as a stop layer. According to an alternative embodiment, the planarization is performed using the horizontal portion of the high-k dielectric layer 156/256/356/456 as a stop layer, and thus the horizontal portion of the high-k dielectric layer may have some remaining portion after the planarization process. As a result of the planarization, replacement (metal) gate electrodes 164, 264, 364, and 464 are formed, as shown in fig. 13, wherein the replacement (metal) gate electrodes 164, 264, 364, and 464 include remaining portions 158, 258, 358, and 458 of the metal layer 58 located in the device regions 100, 200, 300, and 400, respectively. Throughout the specification, replacement gate electrodes 164, 264, 364, and 464 in combination with the respective underlying gate dielectric layers 152, 252, 352, and 452 are referred to as replacement gate stacks 166, 266, 366, and 466, respectively. The remaining portions of fill layer 60 are referred to as fill areas 360 and 460. Filled region 460 is wider than filled region 360, wherein width W4 is greater than width W3. According to some embodiments of the present invention, width W3 of fill region 360 is in a range between about 15nm and about 40nm, and width W4 of fill region 460 is in a range between about 70nm and about 245 nm.
Fig. 14 shows etching back replacement gate stacks 166, 266, 366, and 466. A corresponding process is shown as process 516 in process flow 500 shown in fig. 28. In the etch back, the high-k gate dielectric layers 156, 256, 356, and 456 are etched back. Further, the etch-back replaces the gate electrodes 164, 264, 364, and 464. Accordingly, the corresponding process is also referred to as an etch-back of the replacement gate electrodes 164, 264, 364, and 464. According to some embodiments of the present invention, the etch back is performed using a chemistry that attacks replacement gate electrodes 164, 264, 364, and 464 (as well as the high-k dielectric material and the metal thereon) and does not attack gate spacers 138/238/338/438, ILD 48, and fill regions 360 and 460. According to some embodiments of the invention, the etch-back is performed using a chlorine-based process gas. For example, Cl may be used2And BCl3The mixture of (2) is etched back. The chlorine-based gas has a high value of etch selectivity, wherein the etch selectivity is a ratio of an etch rate of the replacement gate electrode 164/264/364/464 to an etch rate of the fill regions 360 and 460. For example, the etch selectivity may be greater than about 25 or higher (such as greater than about 50).
According to some embodiments of the present invention, since the fill regions 360 and 460 are formed, which occupy the space to be occupied by the metal gate, the gate width (measured in the channel length direction) of the etched region is more uniform throughout the device regions 100, 200, 300, and 400. For example, as shown in fig. 14, assuming that the gate width L1 is equal to L2, the width of the etched regions in the device regions 100, 200, 300, and 400 are all equal to or close to L1. Thus, pattern loading effects in the etch-back are at least reduced and may be substantially eliminated. After etch back, the top surfaces of gate stacks 166, 266, 366, and 466 are substantially flush. As a result of the etch back, the top surfaces of gate stacks 166, 266, 366, and 466 are recessed by a depth D1, wherein depth D1 is greater than about 60nm and may be in a range between about 60nm and about 80 nm. The ratio of D1/H1 may be in a range between about 0.6 and about 0.8.
According to some embodiments of the present invention, the etch-back is stopped when the top surface of the remaining gate stacks 366 and 466 are higher than the bottom of the fill regions 360 and 460. According to some embodiments of the present invention, when the top surfaces of the remaining gate stacks 366 and 466 are substantially flush (with a slight process margin) with the bottom of the fill regions 360 and 460, the etch-back is stopped so that the fill regions 360 and 460 do not collapse. After etch back, the top surfaces of fill regions 360 and 460 are at substantially the same level as the top surface of ILD 48.
Fig. 15 illustrates the deposition of dielectric material 68. A corresponding process is shown as process 518 in process flow 500 shown in fig. 28. According to some embodiments in which fill regions 360 and 460 are formed of an non-dielectric material, such as polysilicon or amorphous silicon, fill regions 360 and 460 are first removed in an etching process before dielectric material 68 is deposited. According to some embodiments in which fill regions 360 and 460 are formed of a dielectric material, fill regions 360 and 460 may be removed by etching, or may remain unremoved, and dielectric material 68 is deposited over fill regions 360 and 460. Accordingly, fill areas 360 and 460 are shown with dashed lines to indicate that they may or may not be replaced. Dielectric material 68 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or the like. The formation methods may include plasma enhanced chemical vapor deposition, CVD, ALD, and the like. Dielectric material 68 and fill regions 360 and 460 may or may not have distinguishable interfaces, whether they are formed of the same or different materials. Furthermore, dielectric material 68 may be formed of the same dielectric material as fill regions 360 and 460 or a different material.
As shown in fig. 16, a planarization process, such as a CMP process or a mechanical polishing process, is then performed to remove the excess portions of dielectric material 68, resulting in hard masks 170, 270, 370, and 470. The corresponding process is shown as process 520 in process flow 500 shown in fig. 28. According to some embodiments of the present invention, the hard masks 170 and 270 are formed of a homogeneous material. In the cross-sectional view shown, hard masks 370 and 470 may or may not include remaining portions 360 and 460, respectively. Hard masks 370 and 470 also include remaining dielectric portions 368 and 468 of dielectric material 68, respectively. According to some embodiments of the present invention, the bottom of portions 360 and 460 protrude down to a level below the bottom surface of dielectric portions 368 and 468. Also, metal layers 358 and 458 form a basin, with portions 360 and 460 extending into the basin.
Fig. 17 illustrates the formation of contact plugs 172, 272, 372, and 472. A corresponding process is shown as process 522 in process flow 500 shown in fig. 28. The formation process includes etching the hard masks 170, 270, 370, and 470 to form contact openings, filling the openings with a conductive material (such as a metal), and performing a planarization process. Source/drain contact plugs 174, 274, 374 and 474 and silicide regions 176, 276, 376 and 476 are also formed to connect to source/ drain regions 142, 242, 342 and 442, respectively.
The gate contact plugs 172, 272, 372 and 472 and the source/drain contact plugs 174, 274, 374 and 474 may be formed of a metal such as tungsten, cobalt, aluminum, or the like. Each contact plug may include a barrier layer formed of, for example, titanium nitride, tantalum nitride, titanium, tantalum, or the like, and a metal located over the barrier layer. Forming the silicide regions 176, 276, 376, and 476 and the source/drain contact plugs 174, 274, 374, and 474 may include etching the ILD 48 and CESL 46 to form contact openings, depositing a conformal metal layer such as titanium or cobalt, forming a metal nitride layer such as titanium nitride, and performing an anneal to form the silicide regions 176, 276, 376, and 476. The remaining contact openings are filled with metal and there may be another metal nitride layer underneath the metal. Thus, short channel finfets 181 and 281, middle channel FinFET 380, and long channel FinFET 480 are formed.
The gate contact plug 372 includes a portion 372B higher than the top surface of the replacement gate electrode 364, and a protruding portion 372A protruding downward into the tub formed by the gate electrode 364. The ring formed by the top of the gate electrode 364 completely surrounds the protruding portion 372A. The gate contact plug 472 includes a portion 472B higher than the top surface of the replacement gate electrode 464, and a protruding portion 472A protruding downward into the tub formed by the gate electrode 464. The ring formed by the top of gate electrode 464 completely surrounds projection 472A.
Figure 17 also shows ILD 78 and contact plug 80. ILD 78 may be formed from a material selected from the same group of candidate materials as ILD 48. ILD 78 may also be formed of a different material than hard masks 170, 270, 370, and 470. Contact plugs 80 are formed in ILD 78 to connect to the underlying gate and source/drain contact plugs.
As shown in fig. 17, projection 372A has a depth D2 and a width W2. According to some embodiments of the invention, the depth D2 is in a range between about 10nm and about 20 nm. The width W2 is in a range between about 30nm and about 40 nm. The aspect ratio D2/W2 may be in a range between about 0.25 and about 0.67. Projection 472A has a depth D3 and a width W3. According to some embodiments of the invention, the depth D3 is in a range between about 10nm and about 20 nm. The width W3 is in a range between about 240nm and about 245 nm. The aspect ratio D3/W3 may be in a range between about 0.04 and about 0.08. The aspect ratio D2/W2 is greater than the aspect ratio D3/W3. Further, the ratio W3/W2 is greater than 1.0, and may be greater than about 6. According to some embodiments of the invention, the ratio W3/W2 may be in a range between about 6 and about 8.2.
Fig. 26 shows a cross-sectional view of the FinFET 381 or 481, in which the corresponding components shown in fig. 17 are shown. This cross-sectional view can be taken from the cross-plane line 26A-26A or line 26B-26B in FIG. 17. Contact plugs 372 or 472 (denoted 372/472) are also shown. Contact plugs 372/472 may be formed on top of fins 324 '/424' or at locations marked with dashed lines.
Fig. 27 illustrates a top view of a FinFET 381 or 481, according to some embodiments of the invention. Hard mask portions 368/468 of hard masks 370 and 470 are observed surrounding respective hard mask portions 360 and 460. Contact plugs 372/472 extend into hard masks 370 and 470, where hard mask portion 360/460 has portions on opposite sides of contact plug 372/472. In addition, the edges of the protruding portions 372A/472A and the corresponding edges of the remaining hard mask portion 360/460 are aligned with straight lines.
Fig. 18-25 illustrate the formation of short channel finfets 181 and 281, middle channel FinFET 381, and long channel FinFET 481 according to some embodiments of the present invention. Unless otherwise stated, the materials and methods of formation of the components in these embodiments are substantially the same as the same components identified by the same reference numerals in the embodiments shown in fig. 1-17. Accordingly, details regarding the formation processes and materials of the components shown in fig. 18-25 may be found in the discussion of the embodiments shown in fig. 1-17.
The initial steps of the formation process according to some embodiments are substantially the same as those shown in fig. 1-11. Next, as shown in fig. 18, the metal layer 82 is formed to extend into the openings 351 and 451. The metal layer 82 is formed using a conformal deposition method, and the metal layer 82 may be formed using ALD, CVD, or the like. The metal layer 82 may be formed of tungsten, cobalt, or the like. According to some embodiments of the invention, the thickness of the metal layer 82 may be less than about 10nm, and may be less than about 5 nm. Fig. 19 illustrates forming a fill layer 60, wherein the fill layer 60 fills the openings 351 and 451 (fig. 18).
As shown in fig. 20, planarization is then performed to remove excess portions of the material located above the top surface of ILD 48. Replacement gate electrodes 164, 264, 364, and 464, which are part of the replacement gate stacks 166, 266, 366, and 466, respectively, are thereby formed. Metal layer 82 has portions 382 and 482 that remain in device regions 300 and 400. Metal layer portions 382 and 482 form portions of gate electrodes 364 and 464.
Fig. 21 shows etching back the gate stacks 166 and 266. According to some embodiments of the present invention, patterned photoresist 84 is formed in device regions 300 and 400, and the structures in device regions 100 and 200 remain unprotected. The etching gas may be similar to that discussed with reference to fig. 14. As shown in fig. 22, after etching back the gate stacks 166 and 266, the photoresist 84 is removed and a photoresist 85 is formed to cover the device regions 100 and 200. Gate stacks 366 and 466 are then etched back. According to some embodiments of the invention, the etching gas comprises a gas (such as BCl) for etching the high-k dielectric layer3) Gases (such as Cl) used to etch metal layers 158, 258, 358, and 4582) And gases (such as NF) used to etch metal layers 382 and 4823). As a result, gate stacks 366 and 466 are recessed. It should be understood that each top surface of metal layers 382 and 482 may be higher than,Flush with or below the top surface of respective metal layers 358 and 458. Leaving fill areas 360 and 460 unremoved.
Fig. 23 illustrates the formation of dielectric material 68. The material of dielectric material 68 may be selected from the materials described above and may be the same as or different from the material of fill regions 360 and 460. Also, fill regions 360 and 460 may be replaced with dielectric material 68 or fill regions 360 and 460 may not be replaced with dielectric material 68.
A planarization process is then performed to remove the excess portions of dielectric material 68, as shown in fig. 24, leaving hard masks 170, 270, 370, and 470. Hard mask 370 includes portions 360 and 368, which may be formed of the same or different materials. Hard mask 470 includes portions 460 and 468, which may be formed of the same or different materials. Whether portions 360 and 368 (and portions 460 and 468) are formed of the same material or different materials, a distinguishable interface may exist between portions 360 and 368 (and portions 460 and 468) when they are not replaced.
As shown in fig. 25, contact plugs 172, 272, 372, 472, 174, 274, 374 and 474 and silicide regions 176, 276, 376 and 476 are then formed. And thus short channel finfets 181 and 281, middle channel FinFET 381, and long channel FinFET 481 are formed. Fig. 26 and 27 show cross-sectional and top views, respectively, of the structure shown in fig. 25, in which metal layers 382 and 482 are shown in phantom to indicate their possible presence or absence. Fig. 25 also illustrates the formation of the remaining features including ILD 78 and contact plug 80.
As shown in fig. 25, projection 372A has a depth D2 'and a width W2'. According to some embodiments of the invention, the depth D2' is in a range between about 5nm and about 15 nm. The width W2' is in a range between about 20nm and about 30 nm. The aspect ratio D2 '/W2' may be in a range between about 0.17 and about 0.75. Projection 472A has a depth D3 'and a width W3'. According to some embodiments of the invention, the depth D3' is in a range between about 5nm and about 15 nm. Width W3' is in a range between about 230nm and about 235 nm. The aspect ratio D3 '/W3' may be in a range between about 0.02 and about 0.07. The aspect ratio D3 '/W3' is less than the aspect ratio D2 '/W2'. Further, the ratio W3 '/W2' is greater than 1.0, and may be greater than about 7.7. According to some embodiments of the invention, the ratio W3 '/W2' may be in a range between about 7.7 and about 11.8.
In the above exemplary embodiments, the fin may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine lithographic and self-aligned processes, allowing for the creation of patterns with smaller pitches than, for example, those obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the fin may then be patterned using the remaining spacers or mandrels.
Embodiments of the present invention have some advantageous features. By filling the replacement gate with a fill region before etching back the metal gate, the width of the portion of the replacement gate that is subject to etching is more uniform regardless of the difference in channel length of the FinFET. Thus, the pattern loading effect in the etch-back of the metal gate is reduced.
According to some embodiments of the invention, a method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, wherein the metal layer includes a portion extending into the trench, depositing a fill region into the trench, wherein the metal layer has a first vertical portion and a second vertical portion on opposite sides of the fill region, etching back the metal layer, wherein the fill region is at least less recessed than the metal layer, and a remaining portion of the metal layer forms a gate electrode, depositing a dielectric material into the trench, and performing planarization to remove an excess portion of the dielectric material. The portion of the dielectric material located in the trench forms at least part of a dielectric hard mask over the gate electrode. In an embodiment, the method further comprises removing the second dummy gate to leave a second trench between the second gate spacers; and forming a first gate dielectric extending into the second trench, wherein the metal layer includes a second portion that completely fills the second trench. In an embodiment, the thickness of the first vertical portion of the metal layer is substantially equal to half the width of the second portion of the metal layer in the second trench. In an embodiment, the fill region is formed of a non-dielectric material, and the method further comprises removing the fill region prior to depositing the dielectric material into the first trench. In an embodiment, the fill region comprises amorphous silicon or polysilicon. In an embodiment, a dielectric material is deposited over the fill region. In an embodiment, the fill region is formed of an additional dielectric material. In an embodiment, after etching back the metal layer, the gate electrode has a shape of a tub, and the tub includes: a bottom; and a sidewall portion surrounding a bottom of the filling region. In an embodiment, the metal layer comprises a work function layer. In an embodiment, the metal layer further comprises a non-work function layer located above the work function layer.
According to some embodiments of the invention, a method comprises: forming a gate dielectric extending into the trench, wherein the trench is located between the opposing gate spacers; depositing a work function layer over the gate dielectric; depositing a filling area on the work function layer, wherein the filling area completely fills the trench; performing planarization to remove the unnecessary portions of the work function layer and the filling region to form a metal gate including the work function layer; etching back the metal gate, wherein the fill region is not substantially etched during the etching back; removing the filling area; and forming a dielectric hard mask in the trench and over the etched back metal gate. In an embodiment, the fill region comprises a dielectric material. In an embodiment, the fill region comprises polysilicon or amorphous silicon. In an embodiment, when the metal gate is etched back, the high-k gate dielectric portion of the gate dielectric is also etched. In an embodiment, etching back the metal gate is performed using a chlorine-based etching gas. In an embodiment, removing the fill region is performed using a fluorine-based etching gas.
According to some embodiments of the present invention, a device includes a semiconductor region; a gate spacer located over the semiconductor region; a gate dielectric located over the semiconductor region; a gate electrode over the gate dielectric and between the gate spacers; wherein the gate electrode comprises a metal layer forming a tub; a dielectric hard mask comprising a first portion over the gate electrode; and a gate contact plug extending into the dielectric hard mask, wherein the gate contact plug comprises: a first portion higher than a top surface of the gate electrode; and a second portion extending into the gate electrode, wherein the gate electrode includes a first vertical portion and a second vertical portion contacting opposite sidewalls of the second portion of the gate contact plug. In an embodiment, a dielectric hard mask includes: a first dielectric material; and a second dielectric material on an opposite side of the first dielectric material, wherein the first dielectric material and the second dielectric material have distinguishable interfaces, and wherein, in a top view of the device, the first dielectric material and a second portion of the gate contact plug are aligned with a straight line. In an embodiment, the first dielectric material and the second dielectric material are different materials. In an embodiment, the dielectric hard mask further comprises a second portion extending into the tub, wherein the second portion of the dielectric hard mask comprises opposing sidewalls in contact with the first vertical portion and the second vertical portion of the gate electrode.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
