Vertical Field Effect Transistor (VFET) device and method of forming the same
阅读说明:本技术 垂直场效应晶体管(vfet)器件及其形成方法 (Vertical Field Effect Transistor (VFET) device and method of forming the same ) 是由 洪思焕 朴容喜 徐康一 于 2019-07-16 设计创作,主要内容包括:提供了垂直场效应晶体管(VFET)器件和形成器件的方法。该方法可包括:形成包括第一沟道区域和第二沟道区域的沟道区域;在衬底中形成第一腔;在第一腔中形成第一底部源极/漏极;在衬底中形成第二腔;以及在第二腔中形成第二底部源极/漏极。第一腔可以暴露第一沟道区域的下表面,第二腔可以暴露第二沟道区域的下表面。该方法还可以包括:在形成第一底部源极/漏极和第二底部源极/漏极之后,去除第一沟道区域和第二沟道区域之间的沟道区域的一部分,以将第一沟道区域与第二沟道区域分离。(Vertical Field Effect Transistor (VFET) devices and methods of forming devices are provided. The method can comprise the following steps: forming a channel region including a first channel region and a second channel region; forming a first cavity in a substrate; forming a first bottom source/drain in the first cavity; forming a second cavity in the substrate; and forming a second bottom source/drain in the second cavity. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may further comprise: after forming the first and second bottom source/drains, a portion of the channel region between the first and second channel regions is removed to separate the first channel region from the second channel region.)
1. A method of forming a vertical field effect transistor device, the method comprising:
forming a channel region protruding from an upper surface of a substrate and extending longitudinally in a first horizontal direction, wherein the channel region includes first and second channel regions aligned in the first horizontal direction and overlapping first and second portions of the substrate, respectively;
forming a first cavity in the substrate by removing a first portion of the substrate, wherein the first cavity exposes a lower surface of the first channel region;
forming a first bottom source/drain in a first cavity of the substrate;
forming a second cavity in the substrate by removing a second portion of the substrate, wherein the second cavity exposes a lower surface of the second channel region;
forming a second bottom source/drain in a second cavity of the substrate;
removing a portion of the channel region between the first channel region and the second channel region after forming the first bottom source/drain and the second bottom source/drain to separate the first channel region from the second channel region; and
a first gate structure is formed on one side of the first channel region and a second gate structure is formed on one side of the second channel region.
2. The method of claim 1, wherein the first bottom source/drain includes a first protruding portion that protrudes from an upper surface of the first bottom source/drain toward the first channel region,
wherein the second bottom source/drain includes a second protruding portion protruding from an upper surface of the second bottom source/drain toward the second channel region, and
wherein the first protruding portion has a first thickness in a vertical direction, the second protruding portion has a second thickness in the vertical direction, and the first thickness and the second thickness are different.
3. The method of claim 1, wherein the first bottom source/drain comprises a different material than the second bottom source/drain.
4. The method of claim 3, wherein forming the first bottom source/drain is performed before forming the second bottom source/drain, and
wherein the first bottom source/drain comprises a bottom source/drain of an N-type field effect transistor and the second bottom source/drain comprises a bottom source/drain of a P-type field effect transistor.
5. The method of claim 1, further comprising forming a protective layer extending over a side of the channel region, wherein forming the first cavity and forming the second cavity are performed while the protective layer is on the side of the channel region.
6. The method of claim 1, wherein forming the first cavity comprises removing a lower portion of the first channel region, and forming the second cavity comprises removing a lower portion of the second channel region.
7. The method of claim 1, wherein forming the second cavity is performed after forming the first bottom source/drain.
8. The method of claim 1, wherein the first cavity exposes an entire lower surface of the first channel region, and
wherein the second cavity exposes an entire lower surface of the second channel region.
9. The method of claim 1, wherein forming the channel region comprises:
forming a mask layer on the substrate; and
etching the substrate using the mask layer as an etch mask to form the channel region.
10. The method of claim 1, wherein forming the channel region comprises forming a plurality of channel regions on the substrate,
wherein each of the plurality of channel regions extends longitudinally in the first horizontal direction and the plurality of channel regions are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction,
wherein each of the plurality of channel regions comprises a respective one of a plurality of first channel regions and a respective one of a plurality of second channel regions,
wherein the plurality of first channel regions overlap the first bottom source/drain,
wherein the plurality of second channel regions overlap the second bottom source/drain,
wherein removing a portion of the channel region between the first channel region and the second channel region comprises: removing portions of the plurality of channel regions, respectively, to separate the plurality of first channel regions from the plurality of second channel regions.
11. A method of forming a vertical field effect transistor device, the method comprising:
forming a channel region on a substrate, wherein the channel region extends longitudinally along a first horizontal direction and includes a first channel region and a second channel region, the first channel region and the second channel region being aligned in the first horizontal direction;
forming a first bottom source/drain in a substrate, the first channel region overlapping the first bottom source/drain;
forming a second bottom source/drain in the substrate, the second channel region overlapping the second bottom source/drain;
removing a portion of the channel region between the first channel region and the second channel region after forming the first bottom source/drain and the second bottom source/drain to separate the first channel region from the second channel region; and
a first gate structure is formed on one side of the first channel region and a second gate structure is formed on one side of the second channel region.
12. The method of claim 11, wherein the first channel region includes a lower surface facing the substrate, and wherein the entire lower surface of the first channel region contacts the first bottom source/drain, and
wherein the second channel region includes a lower surface facing the substrate, and wherein the entire lower surface of the second channel region contacts the second bottom source/drain.
13. The method of claim 12, wherein the first bottom source/drain includes a first protruding portion protruding from an upper surface of the first bottom source/drain toward a lower surface of the first channel region,
wherein the second bottom source/drain includes a second protruding portion protruding from an upper surface of the second bottom source/drain toward a lower surface of the second channel region, and
wherein the first protruding portion has a first thickness in a vertical direction, the second protruding portion has a second thickness in the vertical direction, and the first thickness is different from the second thickness.
14. The method of claim 11, wherein forming the channel region comprises:
forming a mask layer on the substrate; and
etching the substrate using the mask layer as an etch mask to form the channel region.
15. The method of claim 11, wherein forming the first bottom source/drain is performed before forming the second bottom source/drain, and
wherein the first bottom source/drain is a bottom source/drain of an N-type field effect transistor and the second bottom source/drain is a bottom source/drain of a P-type field effect transistor.
16. The method of claim 11, wherein the first channel region comprises a plurality of first channel regions spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, and each of the plurality of first channel regions overlaps the first bottom source/drain, and
wherein the second channel region includes a plurality of second channel regions spaced apart from each other in the second horizontal direction, and each of the plurality of second channel regions overlaps the second bottom source/drain.
17. A method of forming a vertical field effect transistor device, the method comprising:
forming an N-type field effect transistor on a substrate, wherein the N-type field effect transistor includes a first channel region, a first bottom source/drain between the first channel region and the substrate, a first gate structure located at one side of the first channel region, and wherein the first channel region includes a lower surface facing the substrate, and the first bottom source/drain separates the entire lower surface of the first channel region from the substrate in a vertical direction perpendicular to an upper surface of the substrate; and
forming a P-type field effect transistor on the substrate, wherein the P-type field effect transistor includes a second channel region, a second bottom source/drain between the second channel region and the substrate, a second gate structure on one side of the second channel region, and wherein the second channel region includes a lower surface facing the substrate, and the second bottom source/drain separates the entire lower surface of the second channel region from the substrate in the vertical direction.
18. The method of claim 17, wherein the first and second channel regions are spaced apart from each other in a horizontal direction parallel to an upper surface of the substrate, and
wherein the first channel region and the second channel region are aligned along the horizontal direction.
19. The method of claim 17, wherein forming the N-type field effect transistor and forming the P-type field effect transistor comprises:
forming a channel region including the first channel region and the second channel region on the substrate; and
after forming the first and second bottom source/drains, removing a portion of the channel region to separate the first and second channel regions.
20. The method of claim 17, wherein the first bottom source/drain includes a first protruding portion that protrudes toward a lower surface of the first channel region,
wherein the second bottom source/drain includes a second protruding portion protruding toward a lower surface of the second channel region, and
wherein the first protruding portion has a first thickness in the vertical direction, the second protruding portion has a second thickness in the vertical direction, the first thickness being different from the second thickness.
Technical Field
The present disclosure relates generally to the field of electronics, and more particularly to Vertical Field Effect Transistor (VFET) devices.
Background
Due to the high scalability of Vertical Field Effect Transistor (VFET) devices, various structures and fabrication processes for VFET devices have been investigated. In particular, structures and fabrication processes have been investigated to improve the performance of VFET devices that allow for control of the bottom source/drain side junction overlap and formation of abrupt junctions near the bottom source/drain.
Disclosure of Invention
According to some embodiments of the inventive concept, a method of forming a Vertical Field Effect Transistor (VFET) device may include: a channel region is formed that protrudes from the upper surface of the substrate and extends longitudinally in a first horizontal direction. The channel region may include a first channel region and a second channel region aligned in the first horizontal direction, and the first channel region and the second channel region may overlap with the first portion and the second portion of the substrate, respectively. The method may further comprise: forming a first cavity in the substrate by removing a first portion of the substrate; forming a first bottom source/drain in a first cavity of a substrate; forming a second cavity in the substrate by removing a second portion of the substrate; and forming a second bottom source/drain in the second cavity of the substrate. The first cavity may expose a lower surface of the first channel region, and the second cavity may expose a lower surface of the second channel region. The method may further comprise: after forming the first and second bottom source/drains, removing a portion of the channel region between the first and second channel regions to separate the first channel region from the second channel region; and forming a first gate structure at one side of the first channel region and a second gate structure at one side of the second channel region.
According to some embodiments of the inventive concept, a method of forming a Vertical Field Effect Transistor (VFET) device may include: a channel region is formed on a substrate. The channel region may extend longitudinally along the first horizontal direction and may include a first channel region and a second channel region aligned in the first horizontal direction. The method may further comprise: forming a first bottom source/drain in the substrate; forming a second bottom source/drain in the substrate; after forming the first and second bottom source/drains, removing a portion of the channel region between the first and second channel regions to separate the first channel region from the second channel region; and forming a first gate structure at one side of the first channel region and a second gate structure at one side of the second channel region. The first channel region may overlap the first bottom source/drain, and the second channel region may overlap the second bottom source/drain.
According to some embodiments of the inventive concept, a method of forming a Vertical Field Effect Transistor (VFET) device may include: an N-type field effect transistor is formed on a substrate and a P-type field effect transistor is formed on the substrate. The N-type field effect transistor may include a first channel region, a first bottom source/drain between the first channel region and the substrate, a first gate structure on one side of the first channel region. The first channel region may include a lower surface facing the substrate, and the first bottom source/drain may separate the entire lower surface of the first channel region from the substrate in a vertical direction perpendicular to the upper surface of the substrate. The P-type field effect transistor may include a second channel region, a second bottom source/drain between the second channel region and the substrate, a second gate structure on one side of the second channel region. The second channel region may include a lower surface facing the substrate, and the second bottom source/drain may separate the entire lower surface of the second channel region from the substrate in the vertical direction.
Drawings
Fig. 1 through 15C are views illustrating a method of forming a Vertical Field Effect Transistor (VFET) device according to some embodiments of the inventive concept. Fig. 1, 2, 3, 6, 9 and 12 are perspective views, each of fig. 4A, 5A, 7A, 8A, 10A, 11A, 13A, 14A and 15A is a sectional view taken along line I-I ' of its respective perspective view, each of fig. 4B, 5B, 7B, 8B, 10B, 11B, 13B, 14B and 15B is a sectional view taken along line II-II ' of its respective perspective view, and each of fig. 4C, 5C, 7C, 8C, 10C, 11C, 13C, 14C and 15C is a sectional view taken along line III-III ' of its respective perspective view.
Fig. 16 and 17 are flowcharts illustrating methods of forming VFET devices according to some embodiments of the present inventive concept.
Detailed Description
Example embodiments are described below with reference to the drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of the disclosure, and therefore the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
Example embodiments of the inventive concepts are described herein with reference to cross-sectional or plan views that are schematic illustrations of idealized embodiments, as well as intermediate structures of the example embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Accordingly, example embodiments of the inventive concept should not be construed as limited to the particular shapes shown herein but are to include deviations in shapes that result, for example, from manufacturing.
Fig. 1 through 15C are views illustrating methods of forming a VEFT device according to some embodiments of the inventive concept. Specifically, fig. 1, 2, 3, 6, 9 and 12 are perspective views, each of fig. 4A, 5A, 7A, 8A, 10A, 11A, 13A, 14A and 15A is a sectional view taken along line I-I ' of its respective perspective view, each of fig. 4B, 5B, 7B, 8B, 10B, 11B, 13B, 14B and 15B is a sectional view taken along line II-II ' of its respective perspective view, and each of fig. 4C, 5C, 7C, 8C, 10C, 11C, 13C, 14C and 15C is a sectional view taken along line III-III ' of its respective perspective view.
Referring to fig. 1, the method may include forming a channel region 12 protruding from an upper surface 10_ S of a
In some embodiments, forming channel region 12 may include forming a
The
Referring to fig. 2, a
Referring to fig. 3, the
Fig. 4A, 4B, and 4C are cross-sectional views taken along line I-I ', line II-II ', and line III-III ' of fig. 3, respectively, according to some embodiments of the inventive concept. The lines I-I ' and II-II ' are parallel to the second direction D2, and the line III-III ' is parallel to the first direction D1.
Referring to fig. 4A through 4C, a
In some embodiments, the
The
Fig. 5A, 5B, and 5C are cross-sectional views taken along line I-I ', line II-II ', and line III-III ' of fig. 3, respectively, according to some embodiments of the inventive concept. Referring to fig. 5A, 5B, and 5C, while the
Referring to fig. 6, a first bottom source/
It will also be appreciated that forming the
In some embodiments, two
Fig. 7A, 7B, and 7C are cross-sectional views taken along the line I-I ', the line II-II ', and the line III-III ' of fig. 6, respectively, according to some embodiments of the inventive concept. Referring to fig. 7A, 7B, and 7C, the
In some embodiments, the first bottom source/
Fig. 8A, 8B, and 8C are cross-sectional views taken along the line I-I ', the line II-II ', and the line III-III ' of fig. 6, respectively, according to some embodiments of the inventive concept. Referring to fig. 8A, 8B and 8C, the first bottom source/
In some embodiments, the
In some embodiments, the
Referring to fig. 9, a process similar to the process discussed with reference to fig. 3 and 6 may be performed on the second region B of the
It should be appreciated that forming the
In some embodiments, the second bottom source/
Fig. 10A, 10B, and 10C are sectional views taken along line I-I ', line II-II ', and line III-III ' of fig. 9, respectively, according to some embodiments of the inventive concept. Referring to fig. 10A, 10B, and 10C, the
In some embodiments, the
Fig. 11A, 11B, and 11C are cross-sectional views taken along the line I-I ', the line II-II ', and the line III-III ' of fig. 9, respectively, according to some embodiments of the inventive concept. Referring to fig. 11A, 11B and 11C, the second bottom source/
Referring to fig. 12 to 13C, a portion of the channel region 12 may be removed to separate the first and
Fig. 14A, 14B, and 14C are sectional views corresponding to fig. 13A, 13B, and 13C after subsequent processing is performed. Referring to fig. 14A, 14B and 14C, the
Further, an insulating
Each of the first and
Still referring to fig. 14A, 14B and 14C, a first top source/
Fig. 15A, 15B, and 15C are sectional views corresponding to fig. 13A, 13B, and 13C after subsequent processing is performed. Processes similar to those discussed with reference to fig. 14A, 14B, and 14C may be performed. The first bottom source/
According to the methods of forming VFET devices described herein, the first thickness X and the second thickness Y may have different values because the
According to the method of forming a VFET device described herein, the entire
Referring to fig. 16, a method according to some embodiments of the inventive concept may include: forming a channel region 12 on a substrate 10 (block 110) (see, e.g., fig. 1); forming first bottom source/drains 22A in the substrate 10 (block 120) (see, e.g., fig. 3-8C); forming a second bottom source/
Referring to fig. 17, in some embodiments, forming the first bottom source/
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concepts belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "… …," "includes" and/or "including … …," when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.
It should be understood that reference herein to "element a" vertically overlapping element B (or similar language) means that there is a vertical line that intersects both elements a and B.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the teachings of the present inventive concept.
It should also be noted that, in some alternative implementations, the functions/acts noted in the flowchart blocks herein may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the functionality of a given block of the flowchart and/or block diagrams may be split into multiple blocks and/or the functionality of two or more blocks of the flowchart and/or block diagrams may be at least partially integrated. Finally, other blocks may be added/inserted between the blocks shown and/or blocks/operations may be omitted without departing from the scope of the inventive concept.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the inventive concept. Thus, to the maximum extent allowed by law, the scope should be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
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